# Boards with NAND, without subpages
$(eval $(call NANDProfile,370-DB,armada-370-db,512KiB,4096))
$(eval $(call NANDProfile,370-RD,armada-370-rd,512KiB,4096))
+$(eval $(call NANDProfile,385-DB-AP,armada-385-db-ap,256KiB,4096))
$(eval $(call NANDProfile,Mirabox,armada-370-mirabox,512KiB,4096))
$(eval $(call NANDProfile,XP-DB,armada-xp-db,512KiB,4096))
$(eval $(call NANDProfile,XP-GP,armada-xp-gp,512KiB,4096))
--- /dev/null
+From 11aa9df4de06cc257327d783c5cb615989e87286 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Fri, 23 Jan 2015 15:18:27 +0100
+Subject: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
+
+The NDDB register holds the data that are needed by the read and write
+commands.
+
+However, during a read PIO access, the datasheet specifies that after each 32
+bits read in that register, when BCH is enabled, we have to make sure that the
+RDDREQ bit is set in the NDSR register.
+
+This fixes an issue that was seen on the Armada 385, and presumably other mvebu
+SoCs, when a read on a newly erased page would end up in the driver reporting a
+timeout from the NAND.
+
+Cc: <stable@vger.kernel.org> # v3.14
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ drivers/mtd/nand/pxa3xx_nand.c | 45 ++++++++++++++++++++++++++++++++++++------
+ 1 file changed, 39 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
+index 96b0b1d27df1..e6918befb951 100644
+--- a/drivers/mtd/nand/pxa3xx_nand.c
++++ b/drivers/mtd/nand/pxa3xx_nand.c
+@@ -23,6 +23,7 @@
+ #include <linux/mtd/partitions.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
++#include <linux/jiffies.h>
+ #include <linux/slab.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+@@ -480,6 +481,38 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
+ nand_writel(info, NDCR, ndcr | int_mask);
+ }
+
++static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
++{
++ u32 *dst = (u32 *)data;
++
++ if (info->ecc_bch) {
++ while (len--) {
++ u32 timeout;
++
++ *dst++ = nand_readl(info, NDDB);
++
++ /*
++ * According to the datasheet, when reading
++ * from NDDB with BCH enabled, after each 32
++ * bits reads, we have to make sure that the
++ * NDSR.RDDREQ bit is set
++ */
++ timeout = jiffies + msecs_to_jiffies(5);
++ while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
++ if (!time_before(jiffies, timeout)) {
++ dev_err(&info->pdev->dev,
++ "Timeout on RDDREQ while draining the FIFO\n");
++ return;
++ }
++
++ cpu_relax();
++ }
++ }
++ } else {
++ __raw_readsl(info->mmio_base + NDDB, data, len);
++ }
++}
++
+ static void handle_data_pio(struct pxa3xx_nand_info *info)
+ {
+ unsigned int do_bytes = min(info->data_size, info->chunk_size);
+@@ -496,14 +529,14 @@ static void handle_data_pio(struct pxa3xx_nand_info *info)
+ DIV_ROUND_UP(info->oob_size, 4));
+ break;
+ case STATE_PIO_READING:
+- __raw_readsl(info->mmio_base + NDDB,
+- info->data_buff + info->data_buff_pos,
+- DIV_ROUND_UP(do_bytes, 4));
++ drain_fifo(info,
++ info->data_buff + info->data_buff_pos,
++ DIV_ROUND_UP(do_bytes, 4));
+
+ if (info->oob_size > 0)
+- __raw_readsl(info->mmio_base + NDDB,
+- info->oob_buff + info->oob_buff_pos,
+- DIV_ROUND_UP(info->oob_size, 4));
++ drain_fifo(info,
++ info->oob_buff + info->oob_buff_pos,
++ DIV_ROUND_UP(info->oob_size, 4));
+ break;
+ default:
+ dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
+--
+2.2.2
+
--- /dev/null
+From 91b4c91f919abffa72cbf7545a944252f8e4f775 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Thu, 8 Jan 2015 18:38:08 +0100
+Subject: [PATCH 3/4] ARM: mvebu: Add a number of pinctrl functions
+
+Some pinctrl functions can be shared with all DTS out there, since they are
+generic, SoC-wide muxing options. Add a number of these to the DTSI to avoid
+duplication.
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+---
+ arch/arm/boot/dts/armada-38x.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
+index 40200084c6c8..98885c58be29 100644
+--- a/arch/arm/boot/dts/armada-38x.dtsi
++++ b/arch/arm/boot/dts/armada-38x.dtsi
+@@ -195,6 +195,45 @@
+
+ pinctrl@18000 {
+ reg = <0x18000 0x20>;
++
++ ge0_rgmii_pins: ge-rgmii-pins-0 {
++ marvell,pins = "mpp6", "mpp7", "mpp8",
++ "mpp9", "mpp10", "mpp11",
++ "mpp12", "mpp13", "mpp14",
++ "mpp15", "mpp16", "mpp17";
++ marvell,function = "ge0";
++ };
++
++ i2c0_pins: i2c-pins-0 {
++ marvell,pins = "mpp2", "mpp3";
++ marvell,function = "i2c0";
++ };
++
++ mdio_pins: mdio-pins {
++ marvell,pins = "mpp4", "mpp5";
++ marvell,function = "ge";
++ };
++
++ ref_clk0_pins: ref-clk-pins-0 {
++ marvell,pins = "mpp45";
++ marvell,function = "ref";
++ };
++
++ spi1_pins: spi-pins-1 {
++ marvell,pins = "mpp56", "mpp57", "mpp58",
++ "mpp59";
++ marvell,function = "spi1";
++ };
++
++ uart0_pins: uart-pins-0 {
++ marvell,pins = "mpp0", "mpp1";
++ marvell,function = "ua0";
++ };
++
++ uart1_pins: uart-pins-1 {
++ marvell,pins = "mpp19", "mpp20";
++ marvell,function = "ua1";
++ };
+ };
+
+ gpio0: gpio@18100 {
+--
+2.2.1
+
--- /dev/null
+From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Thu, 8 Jan 2015 18:38:09 +0100
+Subject: [PATCH 4/4] ARM: mvebu: Add Armada 385 Access Point Development Board
+ support
+
+The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB
+SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage.
+
+[gregory.clement@free-electrons.com: switch the license to the dual
+X11/GPL with the agreement of the author]
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++++++++++
+ 2 files changed, 179 insertions(+)
+ create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 6dc9c17f9ff5..d34837104949 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -536,6 +536,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \
+ armada-375-db.dtb
+ dtb-$(CONFIG_MACH_ARMADA_38X) += \
+ armada-385-db.dtb \
++ armada-385-db-ap.dtb \
+ armada-385-rd.dtb
+ dtb-$(CONFIG_MACH_ARMADA_XP) += \
+ armada-xp-axpwifiap.dtb \
+diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
+new file mode 100644
+index 000000000000..57b9119fb3e0
+--- /dev/null
++++ b/arch/arm/boot/dts/armada-385-db-ap.dts
+@@ -0,0 +1,178 @@
++/*
++ * Device Tree file for Marvell Armada 385 Access Point Development board
++ * (DB-88F6820-AP)
++ *
++ * Copyright (C) 2014 Marvell
++ *
++ * Nadav Haklai <nadavh@marvell.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without
++ * any warranty of any kind, whether express or implied.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "armada-385.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ model = "Marvell Armada 385 Access Point Development Board";
++ compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
++
++ chosen {
++ bootargs = "console=ttyS0,115200";
++ stdout-path = &uart1;
++ };
++
++ memory {
++ device_type = "memory";
++ reg = <0x00000000 0x80000000>; /* 2GB */
++ };
++
++ soc {
++ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
++ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
++
++ internal-regs {
++ spi1: spi@10680 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi1_pins>;
++ status = "okay";
++
++ spi-flash@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,m25p128";
++ reg = <0>; /* Chip select 0 */
++ spi-max-frequency = <54000000>;
++ };
++ };
++
++ i2c0: i2c@11000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins>;
++ status = "okay";
++
++ /*
++ * This bus is wired to two EEPROM
++ * sockets, one of which holding the
++ * board ID used by the bootloader.
++ * Erasing this EEPROM's content will
++ * brick the board.
++ * Use this bus with caution.
++ */
++ };
++
++ mdio@72004 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&mdio_pins>;
++
++ phy0: ethernet-phy@1 {
++ reg = <1>;
++ };
++
++ phy1: ethernet-phy@4 {
++ reg = <4>;
++ };
++
++ phy2: ethernet-phy@6 {
++ reg = <6>;
++ };
++ };
++
++ /* UART0 is exposed through the JP8 connector */
++ uart0: serial@12000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0_pins>;
++ status = "okay";
++ };
++
++ /*
++ * UART1 is exposed through a FTDI chip
++ * wired to the mini-USB connector
++ */
++ uart1: serial@12100 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart1_pins>;
++ status = "okay";
++ };
++
++ ethernet@30000 {
++ status = "okay";
++ phy = <&phy2>;
++ phy-mode = "sgmii";
++ };
++
++ ethernet@34000 {
++ status = "okay";
++ phy = <&phy1>;
++ phy-mode = "sgmii";
++ };
++
++ ethernet@70000 {
++ pinctrl-names = "default";
++
++ /*
++ * The Reference Clock 0 is used to
++ * provide a clock to the PHY
++ */
++ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
++ status = "okay";
++ phy = <&phy0>;
++ phy-mode = "rgmii-id";
++ };
++ };
++
++ pcie-controller {
++ status = "okay";
++
++ /*
++ * The three PCIe units are accessible through
++ * standard mini-PCIe slots on the board.
++ */
++ pcie@1,0 {
++ /* Port 0, Lane 0 */
++ status = "okay";
++ };
++
++ pcie@2,0 {
++ /* Port 1, Lane 0 */
++ status = "okay";
++ };
++
++ pcie@3,0 {
++ /* Port 2, Lane 0 */
++ status = "okay";
++ };
++ };
++ };
++};
+--
+2.2.1
+
--- /dev/null
+From 7eb1f09ec8e25aa2fc3f6fc5fc9405d9f917d503 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Thu, 11 Dec 2014 14:14:58 +0100
+Subject: [PATCH 1/2] ARM: mvebu: A385-AP: Enable the NAND controller
+
+The A385 AP has a 1GB NAND chip. Enable it.
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
+index 3a51531eb37b..02db04867d8f 100644
+--- a/arch/arm/boot/dts/armada-385-db-ap.dts
++++ b/arch/arm/boot/dts/armada-385-db-ap.dts
+@@ -122,6 +122,19 @@
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
++
++ nfc: flash@d0000 {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ num-cs = <1>;
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++ marvell,nand-keep-config;
++ marvell,nand-enable-arbiter;
++ nand-on-flash-bbt;
++ };
+ };
+
+ pcie-controller {
+--
+2.2.1
+
--- /dev/null
+From a95308d88c07e0093aedae7e64f92cb1e165f592 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Fri, 5 Dec 2014 15:44:57 +0100
+Subject: [PATCH] pinctrl: mvebu: a38x: Add UART1 muxing options
+
+The MPP19 and MMP20 pins also have the ability to be muxed to the uart1
+function.
+
+Add this case to the pinctrl driver.
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Jason Cooper <jason@lakedaemon.net>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
+index 224c6cff6aa2..7302f66f4f19 100644
+--- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
++++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
+@@ -145,14 +145,16 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
+ MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS),
+ MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS),
+ MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS),
+- MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)),
++ MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS),
++ MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
+ MPP_MODE(20,
+ MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
+ MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS),
+ MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
+ MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
+ MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS),
+- MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)),
++ MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS),
++ MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
+ MPP_MODE(21,
+ MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
+ MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS),
+--
+2.2.1
+
--- /dev/null
+From 4a25432b13090b57d257fa0ffb6712d8acf94523 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Thu, 8 Jan 2015 18:38:05 +0100
+Subject: [PATCH 1/4] ARM: mvebu: a38x: Fix node names
+
+Some nodes in the DTs have a reg property but no unit name in their node name.
+
+This contradicts the way the ePAPR defines the node names. Fix this.
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+---
+ arch/arm/boot/dts/armada-380.dtsi | 2 +-
+ arch/arm/boot/dts/armada-385-db.dts | 2 +-
+ arch/arm/boot/dts/armada-385-rd.dts | 2 +-
+ arch/arm/boot/dts/armada-385.dtsi | 2 +-
+ arch/arm/boot/dts/armada-38x.dtsi | 4 ++--
+ 5 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
+index 4173a8ab34e7..13400ce88c54 100644
+--- a/arch/arm/boot/dts/armada-380.dtsi
++++ b/arch/arm/boot/dts/armada-380.dtsi
+@@ -32,7 +32,7 @@
+
+ soc {
+ internal-regs {
+- pinctrl {
++ pinctrl@18000 {
+ compatible = "marvell,mv88f6810-pinctrl";
+ reg = <0x18000 0x20>;
+ };
+diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
+index 2aaa9d2ac284..212605ccc7b6 100644
+--- a/arch/arm/boot/dts/armada-385-db.dts
++++ b/arch/arm/boot/dts/armada-385-db.dts
+@@ -74,7 +74,7 @@
+ phy-mode = "rgmii-id";
+ };
+
+- mdio {
++ mdio@72004 {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts
+index aaca2861dc87..74a3bfe6efd7 100644
+--- a/arch/arm/boot/dts/armada-385-rd.dts
++++ b/arch/arm/boot/dts/armada-385-rd.dts
+@@ -67,7 +67,7 @@
+ };
+
+
+- mdio {
++ mdio@72004 {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
+index 6283d7912f71..5249a4d3c207 100644
+--- a/arch/arm/boot/dts/armada-385.dtsi
++++ b/arch/arm/boot/dts/armada-385.dtsi
+@@ -37,7 +37,7 @@
+
+ soc {
+ internal-regs {
+- pinctrl {
++ pinctrl@18000 {
+ compatible = "marvell,mv88f6820-pinctrl";
+ reg = <0x18000 0x20>;
+ };
+diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
+index 74391dace9e7..ada1f206028b 100644
+--- a/arch/arm/boot/dts/armada-38x.dtsi
++++ b/arch/arm/boot/dts/armada-38x.dtsi
+@@ -193,7 +193,7 @@
+ status = "disabled";
+ };
+
+- pinctrl {
++ pinctrl@18000 {
+ compatible = "marvell,mv88f6820-pinctrl";
+ reg = <0x18000 0x20>;
+ };
+@@ -373,7 +373,7 @@
+ status = "disabled";
+ };
+
+- mdio {
++ mdio@72004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+--
+2.2.1
+
--- /dev/null
+From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Tue, 13 Jan 2015 11:14:09 +0100
+Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
+index 02db04867d8f..2a58443e2504 100644
+--- a/arch/arm/boot/dts/armada-385-db-ap.dts
++++ b/arch/arm/boot/dts/armada-385-db-ap.dts
+@@ -134,6 +134,21 @@
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
++
++ mtd0@00000000 {
++ label = "u-boot";
++ reg = <0x00000000 0x00800000>;
++ };
++
++ mtd1@00800000 {
++ label = "kernel";
++ reg = <0x00800000 0x00800000>;
++ };
++
++ mtd2@01000000 {
++ label = "ubi";
++ reg = <0x01000000 0x3f000000>;
++ };
+ };
+ };
+
+--
+2.2.1
+
projects / openwrt / staging / ynezz.git / commitdiff