--- /dev/null
+/*
+ * Copyright 2016 Rockchip Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_QOS_RK3288_H
+#define _ASM_ARCH_QOS_RK3288_H
+
+#define PRIORITY_HIGH_SHIFT 2
+#define PRIORITY_LOW_SHIFT 0
+
+#define CPU_AXI_QOS_PRIORITY 0x08
+
+#define VIO0_VOP_QOS 0xffad0400
+#define VIO1_VOP_QOS 0xffad0000
+#define VIO1_ISP_R_QOS 0xffad0900
+#define VIO1_ISP_W0_QOS 0xffad0100
+#define VIO1_ISP_W1_QOS 0xffad0180
+
+#endif
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch/qos_rk3288.h>
#include <asm/arch/boot_mode.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
return 0;
}
+int rk3288_qos_init(void)
+{
+ int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
+ /* set vop qos to higher priority */
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
+
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+ "rockchip,rk3288-miniarm"))
+ {
+ /* set isp qos to higher priority */
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
+ }
+ return 0;
+}
+
int board_late_init(void)
{
setup_boot_mode();
+ rk3288_qos_init();
return rk_board_late_init();
}