ath9k: Add custom parameters for CUS198
authorSujith Manoharan <c_manoha@qca.qualcomm.com>
Thu, 13 Jun 2013 17:21:26 +0000 (22:51 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 14 Jun 2013 17:37:16 +0000 (13:37 -0400)
CUS198 is a card based on AR9485. There are differences
between the base reference design HB125 and CUS198.
Identify such cards based on the PCI subsystem IDs and
set HW parameters appropriately.

Addresses this bug - https://bugzilla.kernel.org/show_bug.cgi?id=49201

Cc: jkp@iki.fi
Cc: gfmichaud@gmail.com
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
drivers/net/wireless/ath/ath9k/ath9k.h
drivers/net/wireless/ath/ath9k/hw.h
drivers/net/wireless/ath/ath9k/init.c
drivers/net/wireless/ath/ath9k/pci.c

index 25b8bbbe74fe347f6f0f17fcc129ebd100f88301..9a00bc0a930422f47b749981b7270b774fcc83f6 100644 (file)
@@ -3563,16 +3563,22 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
 {
        struct ath9k_hw_capabilities *pCap = &ah->caps;
        int chain;
-       u32 regval, value;
+       u32 regval, value, gpio;
        static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
                        AR_PHY_SWITCH_CHAIN_0,
                        AR_PHY_SWITCH_CHAIN_1,
                        AR_PHY_SWITCH_CHAIN_2,
        };
 
-       if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0))
+       if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) {
+               if (ah->config.xlna_gpio)
+                       gpio = ah->config.xlna_gpio;
+               else
+                       gpio = AR9300_EXT_LNA_CTL_GPIO_AR9485;
+
                ath9k_hw_cfg_output(ah, AR9300_EXT_LNA_CTL_GPIO_AR9485,
                                    AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED);
+       }
 
        value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
 
@@ -3800,7 +3806,13 @@ static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
                        REG_RMW_FIELD(ah, ext_atten_reg[i],
                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
 
-                       value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
+                       if (AR_SREV_9485(ah) &&
+                           (ar9003_hw_get_rx_gain_idx(ah) == 0) &&
+                           ah->config.xatten_margin_cfg)
+                               value = 5;
+                       else
+                               value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
+
                        REG_RMW_FIELD(ah, ext_atten_reg[i],
                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
                                      value);
index a6e666bcc0a747fedd0edbba4285dd7295c0865a..74965eefbd1cde3d91638d1c73cb2aea548a6084 100644 (file)
@@ -631,6 +631,8 @@ void ath_ant_comb_update(struct ath_softc *sc);
 /* Main driver core */
 /********************/
 
+#define ATH9K_PCI_CUS198 0x0001
+
 /*
  * Default cache line size, in bytes.
  * Used when PCI device not fully initialized by bootrom/BIOS
@@ -715,6 +717,7 @@ struct ath_softc {
 
        unsigned int hw_busy_count;
        unsigned long sc_flags;
+       unsigned long driver_data;
 
        u32 intrstatus;
        u16 ps_flags; /* PS_* */
index 7d259b7dc2547062ab574373f967d8a7e18bd329..ed7d4fcbdcab6167927321198993baa37c12dba3 100644 (file)
@@ -307,6 +307,10 @@ struct ath9k_ops_config {
        u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
        u8 max_txtrig_level;
        u16 ani_poll_interval; /* ANI poll interval in ms */
+
+       /* Platform specific config */
+       u32 xlna_gpio;
+       bool xatten_margin_cfg;
 };
 
 enum ath9k_int {
index 818f22daa8ba88d2a2975f022e3c34f5a55ce76d..7c2ed1cef9b7a7c771d2fd62378737b16b7a7145 100644 (file)
@@ -513,6 +513,22 @@ static void ath9k_init_misc(struct ath_softc *sc)
        sc->spec_config.fft_period = 0xF;
 }
 
+static void ath9k_init_platform(struct ath_softc *sc)
+{
+       struct ath_hw *ah = sc->sc_ah;
+       struct ath_common *common = ath9k_hw_common(ah);
+
+       if (common->bus_ops->ath_bus_type != ATH_PCI)
+               return;
+
+       if (sc->driver_data & ATH9K_PCI_CUS198) {
+               ah->config.xlna_gpio = 9;
+               ah->config.xatten_margin_cfg = true;
+
+               ath_info(common, "Set parameters for CUS198\n");
+       }
+}
+
 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
                                    void *ctx)
 {
@@ -604,6 +620,11 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
        common->btcoex_enabled = ath9k_btcoex_enable == 1;
        common->disable_ani = false;
 
+       /*
+        * Platform quirks.
+        */
+       ath9k_init_platform(sc);
+
        /*
         * Enable Antenna diversity only when BTCOEX is disabled
         * and the user manually requests the feature.
index 0e0d39583837219a60a374d69494933b0ffc4e43..4ac00b4b0d2535ecd82f22a8e214580302ea1321 100644 (file)
@@ -34,6 +34,34 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
        { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
        { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
        { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
+
+       /* PCI-E CUS198 */
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
+                        0x0032,
+                        PCI_VENDOR_ID_AZWAVE,
+                        0x2086),
+         .driver_data = ATH9K_PCI_CUS198 },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
+                        0x0032,
+                        PCI_VENDOR_ID_AZWAVE,
+                        0x1237),
+         .driver_data = ATH9K_PCI_CUS198 },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
+                        0x0032,
+                        PCI_VENDOR_ID_AZWAVE,
+                        0x2126),
+         .driver_data = ATH9K_PCI_CUS198 },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
+                        0x0032,
+                        PCI_VENDOR_ID_AZWAVE,
+                        0x2152),
+         .driver_data = ATH9K_PCI_CUS198 },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
+                        0x0032,
+                        PCI_VENDOR_ID_FOXCONN,
+                        0xE075),
+         .driver_data = ATH9K_PCI_CUS198 },
+
        { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
        { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E  AR9580 */
        { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E  AR9462 */
@@ -221,6 +249,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        sc->hw = hw;
        sc->dev = &pdev->dev;
        sc->mem = pcim_iomap_table(pdev)[0];
+       sc->driver_data = id->driver_data;
 
        /* Will be cleared in ath9k_start() */
        set_bit(SC_OP_INVALID, &sc->sc_flags);