drm/amdgpu: fix several indentation issues

There are several statements that are incorrectly indented. Fix these.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bc62bf41b7e9b428a66b88e7d67a7f684133f7dd..b65e181011085cf880378500a50009cdb21937ca 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -207,7 +207,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
        if (!r) {
                acpi_status = amdgpu_acpi_init(adev);
                if (acpi_status)
-               dev_dbg(&dev->pdev->dev,
+                       dev_dbg(&dev->pdev->dev,
                                "Error during ACPI methods call\n");
        }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index db443ec53d3aeb5db36c09fdbf45f9287658f4d2..bea32f076b91c98dd346d178b73ea70f5dcfd845 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2980,7 +2980,7 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
                                 struct amdgpu_irq_src *source,
                                 struct amdgpu_iv_entry *entry)
 {
-               unsigned long flags;
+       unsigned long flags;
        unsigned crtc_id;
        struct amdgpu_crtc *amdgpu_crtc;
        struct amdgpu_flip_work *works;

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index e347b407bd03948d4ee214474ed6728970ba1ee1..727370ccd854526ad360b3437ade5eb8dd157054 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -32,7 +32,7 @@
 
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
-    u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+       u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
 
        tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
        tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 79c1a9bbcc215e450e4c1c439f0258a82608ca74..9d8df68893b9d8a1be221adc9e6f3ccddd59e916 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1436,7 +1436,7 @@ static int si_common_early_init(void *handle)
                        AMD_CG_SUPPORT_UVD_MGCG |
                        AMD_CG_SUPPORT_HDP_LS |
                        AMD_CG_SUPPORT_HDP_MGCG;
-                       adev->pg_flags = 0;
+               adev->pg_flags = 0;
                adev->external_rev_id = (adev->rev_id == 0) ? 1 :
                                        (adev->rev_id == 1) ? 5 : 6;
                break;

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index d138ddae563d2cfdf6ff9c878a42e971612509fb..58f5589aaf126add63407b058e80e7d4bd2a4319 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -1211,7 +1211,7 @@ int smu7_power_control_set_level(struct pp_hwmgr *hwmgr)
                                hwmgr->platform_descriptor.TDPAdjustment :
                                (-1 * hwmgr->platform_descriptor.TDPAdjustment);
 
-                if (hwmgr->chip_id > CHIP_TONGA)
+               if (hwmgr->chip_id > CHIP_TONGA)
                        target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
                else
                        target_tdp = ((100 + adjust_percent) * (int)(cac_table->usConfigurableTDP * 256)) / 100;

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 0769b1ec562b498fc6d75cc739cdeed1a8888cf5..aad79affb08123a6acb21dcf03d80bbfbf5609d3 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -3456,7 +3456,7 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
        disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
                            !hwmgr->display_config->multi_monitor_in_sync) ||
                             vblank_too_short;
-    latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
+       latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
 
        /* gfxclk */
        dpm_table = &(data->dpm_table.gfx_table);