imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
PAD_CTL_PKE |
PAD_CTL_DSE_HIGH));
+ gpio_request(IMX_GPIO_NR(1, 4), "USB_OTG_PWRON");
gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
/* USB OTG Over Current */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
PAD_CTL_PKE |
PAD_CTL_DSE_HIGH));
+ gpio_request(IMX_GPIO_NR(1, 2), "USB_HOST_PWRON");
gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
/* USB Host Over Current */
static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
{
+ gpio_request(IMX_GPIO_NR(6, 0), "LCD");
+
/* For ETM0430G0DH6 model, this must be enabled before the clock. */
gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
{
+ gpio_request(IMX_GPIO_NR(6, 0), "LCD");
+
/*
* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
const u32 dramclk = 400;
u32 cpuclk;
+ gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
+
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
gpio_direction_input(IMX_GPIO_NR(4, 0));
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_TARGET_M53MENLO=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
+CONFIG_DM_GPIO=y
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y