if (unlikely(clk->rate == clk->parent->rate / dsor))
return; /* No change, quick exit */
clk->rate = clk->parent->rate / dsor;
-
- if (unlikely(clk->flags & RATE_PROPAGATES))
- propagate_rate(clk);
}
static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
if (unlikely(clk->rate == clk->parent->rate / dsor))
return; /* No change, quick exit */
clk->rate = clk->parent->rate / dsor;
-
- if (unlikely(clk->flags & RATE_PROPAGATES))
- propagate_rate(clk);
}
/* MPU virtual clock functions */
WARN_ON(!clk->fixed_div);
clk->rate = clk->parent->rate / clk->fixed_div;
-
- if (clk->flags & RATE_PROPAGATES)
- propagate_rate(clk);
}
/**
clk->rate = clk->parent->rate / div;
pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
-
- if (unlikely(clk->flags & RATE_PROPAGATES))
- propagate_rate(clk);
}
/**
static void omap2_dpllcore_recalc(struct clk *clk)
{
clk->rate = omap2_get_dpll_rate_24xx(clk);
-
- propagate_rate(clk);
}
static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
static void omap2_osc_clk_recalc(struct clk *clk)
{
clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
- propagate_rate(clk);
}
static void omap2_sys_clk_recalc(struct clk *clk)
{
clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
- propagate_rate(clk);
}
/*
clk_init(&omap2_clk_functions);
omap2_osc_clk_recalc(&osc_ck);
+ propagate_rate(&osc_ck);
omap2_sys_clk_recalc(&sys_ck);
+ propagate_rate(&sys_ck);
for (clkp = onchip_24xx_clks;
clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
- .recalc = &propagate_rate,
};
/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
- .recalc = &propagate_rate,
};
/*
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
- .recalc = &propagate_rate,
};
static struct clk apll54_ck = {
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
- .recalc = &propagate_rate,
};
/*
static void omap3_dpll_recalc(struct clk *clk)
{
clk->rate = omap2_get_dpll_rate(clk);
-
- propagate_rate(clk);
}
/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
clk->rate = clk->parent->rate;
else
clk->rate = clk->parent->rate * 2;
-
- if (clk->flags & RATE_PROPAGATES)
- propagate_rate(clk);
}
/* Common clock code */
.ops = &clkops_null,
.rate = 32768,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
static struct clk secure_32k_fck = {
.ops = &clkops_null,
.rate = 32768,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
/* Virtual source clocks for osc_sys_ck */
.ops = &clkops_null,
.rate = 12000000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
static struct clk virt_13m_ck = {
.ops = &clkops_null,
.rate = 13000000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
static struct clk virt_16_8m_ck = {
.ops = &clkops_null,
.rate = 16800000,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
static struct clk virt_19_2m_ck = {
.ops = &clkops_null,
.rate = 19200000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
static struct clk virt_26m_ck = {
.ops = &clkops_null,
.rate = 26000000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
static struct clk virt_38_4m_ck = {
.ops = &clkops_null,
.rate = 38400000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
static const struct clksel_rate osc_sys_12m_rates[] = {
.name = "sys_altclk",
.ops = &clkops_null,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
/* Optional external clock input for some McBSPs */
.name = "mcbsp_clks",
.ops = &clkops_null,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
- .recalc = &propagate_rate,
};
/* PRM EXTERNAL CLOCK OUTPUT */
return;
clk->rate = clk->parent->rate;
- if (unlikely(clk->flags & RATE_PROPAGATES))
- propagate_rate(clk);
}
/* Propagate rate to children */
list_for_each_entry(clkp, &clocks, node) {
if (likely(clkp->parent != tclk))
continue;
- if (likely((u32)clkp->recalc))
+ if (clkp->recalc)
clkp->recalc(clkp);
+ if (clkp->flags & RATE_PROPAGATES)
+ propagate_rate(clkp);
}
}
struct clk *clkp;
list_for_each_entry(clkp, &clocks, node) {
- if (unlikely(!clkp->parent) && likely((u32)clkp->recalc))
- clkp->recalc(clkp);
+ if (!clkp->parent) {
+ if (clkp->recalc)
+ clkp->recalc(clkp);
+ if (clkp->flags & RATE_PROPAGATES)
+ propagate_rate(clkp);
+ }
}
}