i, targetPowerValT2[i]);
}
- ah->txpower_limit = regulatory->max_power_level;
-
/* Write target power array to registers */
ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
ar9003_hw_calibration_apply(ah, chan->channel);
AR_STA_ID1_MCAST_KSRCH;
if (AR_SREV_9100(ah))
ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
- ah->enable_32kHz_clock = DONT_USE_32KHZ;
ah->slottime = ATH9K_SLOT_TIME_9;
ah->globaltxtimeout = (u32) -1;
ah->power_mode = ATH9K_PM_UNDEFINED;
struct ar5416Stats stats;
struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
- int16_t curchan_rad_index;
enum ath9k_int imask;
u32 imrs2_reg;
u32 txok_interrupt_mask;
u32 sta_id1_defaults;
u32 misc_mode;
- enum {
- AUTO_32KHZ,
- USE_32KHZ,
- DONT_USE_32KHZ,
- } enable_32kHz_clock;
/* Private to hardware code */
struct ath_hw_private_ops private_ops;
u32 *analogBank7Data;
u32 *bank6Temp;
- u8 txpower_limit;
int coverage_class;
u32 slottime;
u32 globaltxtimeout;
struct ath_gen_timer_table hw_gen_timers;
struct ar9003_txs *ts_ring;
- void *ts_start;
u32 ts_paddr_start;
u32 ts_paddr_end;
u16 ts_tail;
}
/* Initialization, Detach, Reset */
-const char *ath9k_hw_probe(u16 vendorid, u16 devid);
void ath9k_hw_deinit(struct ath_hw *ah);
int ath9k_hw_init(struct ath_hw *ah);
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
int ar9003_paprd_init_table(struct ath_hw *ah);
bool ar9003_paprd_is_done(struct ath_hw *ah);
-void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
/* Hardware family op attach helpers */
void ar5008_hw_attach_phy_ops(struct ath_hw *ah);