--- /dev/null
+diff -urN -x CVS linux-2.6.19-final/arch/arm/Kconfig linux-2.6.19/arch/arm/Kconfig
+--- linux-2.6.19-final/arch/arm/Kconfig Mon Dec 4 16:39:27 2006
++++ linux-2.6.19/arch/arm/Kconfig Thu Nov 30 09:08:02 2006
+@@ -583,7 +591,7 @@
+ ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
+ ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
+ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
+- ARCH_AT91RM9200 || MACH_TRIZEPS4
++ ARCH_AT91 || MACH_TRIZEPS4
+ help
+ If you say Y here, the LEDs on your machine will be used
+ to provide useful information about your current system status.
+diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/at91rm9200dk_defconfig linux-2.6.19/arch/arm/configs/at91rm9200dk_defconfig
+--- linux-2.6.19-final/arch/arm/configs/at91rm9200dk_defconfig Mon Dec 4 16:39:28 2006
++++ linux-2.6.19/arch/arm/configs/at91rm9200dk_defconfig Mon Nov 20 10:46:02 2006
+@@ -357,9 +357,9 @@
+ #
+ # CONFIG_MTD_COMPLEX_MAPPINGS is not set
+ CONFIG_MTD_PHYSMAP=y
+-CONFIG_MTD_PHYSMAP_START=0x10000000
+-CONFIG_MTD_PHYSMAP_LEN=0x200000
+-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
++CONFIG_MTD_PHYSMAP_START=0
++CONFIG_MTD_PHYSMAP_LEN=0
++CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+ # CONFIG_MTD_ARM_INTEGRATOR is not set
+ # CONFIG_MTD_IMPA7 is not set
+ # CONFIG_MTD_PLATRAM is not set
+@@ -585,7 +585,9 @@
+ # CONFIG_USBPCWATCHDOG is not set
+ # CONFIG_NVRAM is not set
+ # CONFIG_RTC is not set
+-CONFIG_AT91_RTC=y
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_AT91RM9200=y
+ # CONFIG_DTLK is not set
+ # CONFIG_R3964 is not set
+
+diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/at91rm9200ek_defconfig linux-2.6.19/arch/arm/configs/at91rm9200ek_defconfig
+--- linux-2.6.19-final/arch/arm/configs/at91rm9200ek_defconfig Mon Dec 4 16:39:28 2006
++++ linux-2.6.19/arch/arm/configs/at91rm9200ek_defconfig Mon Nov 20 10:45:49 2006
+@@ -348,9 +348,9 @@
+ #
+ # CONFIG_MTD_COMPLEX_MAPPINGS is not set
+ CONFIG_MTD_PHYSMAP=y
+-CONFIG_MTD_PHYSMAP_START=0x10000000
+-CONFIG_MTD_PHYSMAP_LEN=0x800000
+-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
++CONFIG_MTD_PHYSMAP_START=0
++CONFIG_MTD_PHYSMAP_LEN=0
++CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+ # CONFIG_MTD_ARM_INTEGRATOR is not set
+ # CONFIG_MTD_IMPA7 is not set
+ # CONFIG_MTD_PLATRAM is not set
+@@ -566,7 +566,9 @@
+ # CONFIG_USBPCWATCHDOG is not set
+ # CONFIG_NVRAM is not set
+ # CONFIG_RTC is not set
+-CONFIG_AT91_RTC=y
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_AT91RM9200=y
+ # CONFIG_DTLK is not set
+ # CONFIG_R3964 is not set
+
+diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/at91sam9260ek_defconfig linux-2.6.19/arch/arm/configs/at91sam9260ek_defconfig
+--- linux-2.6.19-final/arch/arm/configs/at91sam9260ek_defconfig Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/configs/at91sam9260ek_defconfig Mon Nov 20 10:51:08 2006
+@@ -0,0 +1,950 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.19-rc6
++# Fri Nov 17 18:42:21 2006
++#
++CONFIG_ARM=y
++# CONFIG_GENERIC_TIME is not set
++CONFIG_MMU=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# Code maturity level options
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++# CONFIG_IPC_NS is not set
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_UTS_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++# CONFIG_RELAY is not set
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SHMEM=y
++CONFIG_SLAB=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++# CONFIG_SLOB is not set
++
++#
++# Loadable module support
++#
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++
++#
++# Block layer
++#
++CONFIG_BLOCK=y
++# CONFIG_BLK_DEV_IO_TRACE is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++CONFIG_ARCH_AT91=y
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_OMAP is not set
++
++#
++# Atmel AT91 System-on-Chip
++#
++# CONFIG_ARCH_AT91RM9200 is not set
++CONFIG_ARCH_AT91SAM9260=y
++# CONFIG_ARCH_AT91SAM9261 is not set
++
++#
++# AT91SAM9260 Board Type
++#
++CONFIG_MACH_AT91SAM9260EK=y
++
++#
++# AT91 Board Options
++#
++# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
++
++#
++# AT91 Feature Selections
++#
++# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_ARM926T=y
++CONFIG_CPU_32v5=y
++CONFIG_CPU_ABRT_EV5TJ=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_COPY_V4WB=y
++CONFIG_CPU_TLB_V4WBI=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
++# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
++
++#
++# Bus support
++#
++
++#
++# PCCARD (PCMCIA/CardBus) support
++#
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=100
++# CONFIG_AEABI is not set
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
++# CONFIG_XIP_KERNEL is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_BINFMT_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++# CONFIG_ARTHUR is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++# CONFIG_APM is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_NETDEBUG is not set
++CONFIG_PACKET=y
++# CONFIG_PACKET_MMAP is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++
++#
++# DCCP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_DCCP is not set
++
++#
++# SCTP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_SCTP is not set
++
++#
++# TIPC Configuration (EXPERIMENTAL)
++#
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++
++#
++# QoS and/or fair queueing
++#
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_IEEE80211 is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_SYS_HYPERVISOR is not set
++
++#
++# Connector - unified userspace <-> kernelspace linker
++#
++# CONFIG_CONNECTOR is not set
++
++#
++# Memory Technology Devices (MTD)
++#
++# CONFIG_MTD is not set
++
++#
++# Parallel port support
++#
++# CONFIG_PARPORT is not set
++
++#
++# Plug and Play support
++#
++
++#
++# Block devices
++#
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++CONFIG_BLK_DEV_INITRD=y
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++CONFIG_SCSI_MULTI_LUN=y
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++
++#
++# SCSI low-level drivers
++#
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_SCSI_DEBUG is not set
++
++#
++# Multi-device support (RAID and LVM)
++#
++# CONFIG_MD is not set
++
++#
++# Fusion MPT device support
++#
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++
++#
++# I2O device support
++#
++
++#
++# Network device support
++#
++# CONFIG_NETDEVICES is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++
++#
++# ISDN subsystem
++#
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_TSDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_ATMEL=y
++CONFIG_SERIAL_ATMEL_CONSOLE=y
++# CONFIG_SERIAL_ATMEL_TTYAT is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++
++#
++# IPMI
++#
++# CONFIG_IPMI_HANDLER is not set
++
++#
++# Watchdog Cards
++#
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_NOWAYOUT=y
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++
++#
++# Ftape, the floppy tape device driver
++#
++# CONFIG_RAW_DRIVER is not set
++
++#
++# TPM devices
++#
++# CONFIG_TCG_TPM is not set
++
++#
++# I2C support
++#
++# CONFIG_I2C is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++
++#
++# Dallas's 1-wire bus
++#
++# CONFIG_W1 is not set
++
++#
++# Hardware Monitoring support
++#
++# CONFIG_HWMON is not set
++# CONFIG_HWMON_VID is not set
++
++#
++# Misc devices
++#
++# CONFIG_TIFM_CORE is not set
++
++#
++# LED devices
++#
++# CONFIG_NEW_LEDS is not set
++
++#
++# LED drivers
++#
++
++#
++# LED Triggers
++#
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++
++#
++# Digital Video Broadcasting Devices
++#
++# CONFIG_DVB is not set
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++
++#
++# USB support
++#
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++# CONFIG_USB_BANDWIDTH is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++CONFIG_USB_STORAGE_DEBUG=y
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_DPCM is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++# CONFIG_USB_AIPTEK is not set
++# CONFIG_USB_WACOM is not set
++# CONFIG_USB_ACECAD is not set
++# CONFIG_USB_KBTAB is not set
++# CONFIG_USB_POWERMATE is not set
++# CONFIG_USB_TOUCHSCREEN is not set
++# CONFIG_USB_YEALINK is not set
++# CONFIG_USB_XPAD is not set
++# CONFIG_USB_ATI_REMOTE is not set
++# CONFIG_USB_ATI_REMOTE2 is not set
++# CONFIG_USB_KEYSPAN_REMOTE is not set
++# CONFIG_USB_APPLETOUCH is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET_MII is not set
++# CONFIG_USB_USBNET is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_PXA2XX is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++CONFIG_USB_GADGET_AT91=y
++CONFIG_USB_AT91=y
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++# CONFIG_USB_GADGET_DUALSPEED is not set
++CONFIG_USB_ZERO=m
++# CONFIG_USB_ETH is not set
++CONFIG_USB_GADGETFS=m
++CONFIG_USB_FILE_STORAGE=m
++# CONFIG_USB_FILE_STORAGE_TEST is not set
++CONFIG_USB_G_SERIAL=m
++# CONFIG_USB_MIDI_GADGET is not set
++
++#
++# MMC/SD Card support
++#
++# CONFIG_MMC is not set
++
++#
++# Real Time Clock
++#
++CONFIG_RTC_LIB=y
++# CONFIG_RTC_CLASS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_EXT4DEV_FS is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_ROMFS_FS is not set
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++# CONFIG_MSDOS_FS is not set
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_RAMFS=y
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++
++#
++# Network File Systems
++#
++# CONFIG_NFS_FS is not set
++# CONFIG_NFSD is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++# CONFIG_9P_FS is not set
++
++#
++# Partition Types
++#
++# CONFIG_PARTITION_ADVANCED is not set
++CONFIG_MSDOS_PARTITION=y
++
++#
++# Native Language Support
++#
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++CONFIG_NLS_CODEPAGE_850=y
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++
++#
++# Profiling support
++#
++# CONFIG_PROFILING is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_MUST_CHECK=y
++# CONFIG_MAGIC_SYSRQ is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_KERNEL=y
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_RWSEMS is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_INFO is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_WAITQ is not set
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++
++#
++# Cryptographic options
++#
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++CONFIG_CRC32=y
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_PLIST=y
+diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/at91sam9261ek_defconfig linux-2.6.19/arch/arm/configs/at91sam9261ek_defconfig
+--- linux-2.6.19-final/arch/arm/configs/at91sam9261ek_defconfig Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/configs/at91sam9261ek_defconfig Mon Nov 20 10:51:08 2006
+@@ -0,0 +1,1106 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.19-rc6
++# Fri Nov 17 18:00:38 2006
++#
++CONFIG_ARM=y
++# CONFIG_GENERIC_TIME is not set
++CONFIG_MMU=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# Code maturity level options
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++# CONFIG_IPC_NS is not set
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_UTS_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++# CONFIG_RELAY is not set
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SHMEM=y
++CONFIG_SLAB=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++# CONFIG_SLOB is not set
++
++#
++# Loadable module support
++#
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++
++#
++# Block layer
++#
++CONFIG_BLOCK=y
++# CONFIG_BLK_DEV_IO_TRACE is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++# CONFIG_IOSCHED_DEADLINE is not set
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++CONFIG_ARCH_AT91=y
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_OMAP is not set
++
++#
++# Atmel AT91 System-on-Chip
++#
++# CONFIG_ARCH_AT91RM9200 is not set
++# CONFIG_ARCH_AT91SAM9260 is not set
++CONFIG_ARCH_AT91SAM9261=y
++
++#
++# AT91SAM9261 Board Type
++#
++CONFIG_MACH_AT91SAM9261EK=y
++
++#
++# AT91 Board Options
++#
++# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
++
++#
++# AT91 Feature Selections
++#
++# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_ARM926T=y
++CONFIG_CPU_32v5=y
++CONFIG_CPU_ABRT_EV5TJ=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_COPY_V4WB=y
++CONFIG_CPU_TLB_V4WBI=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
++# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
++
++#
++# Bus support
++#
++
++#
++# PCCARD (PCMCIA/CardBus) support
++#
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=100
++# CONFIG_AEABI is not set
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
++# CONFIG_XIP_KERNEL is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_BINFMT_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++# CONFIG_ARTHUR is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++# CONFIG_APM is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_NETDEBUG is not set
++CONFIG_PACKET=y
++# CONFIG_PACKET_MMAP is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++
++#
++# DCCP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_DCCP is not set
++
++#
++# SCTP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_SCTP is not set
++
++#
++# TIPC Configuration (EXPERIMENTAL)
++#
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++
++#
++# QoS and/or fair queueing
++#
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_IEEE80211 is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_SYS_HYPERVISOR is not set
++
++#
++# Connector - unified userspace <-> kernelspace linker
++#
++# CONFIG_CONNECTOR is not set
++
++#
++# Memory Technology Devices (MTD)
++#
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++# CONFIG_MTD_CHAR is not set
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++# CONFIG_MTD_OBSOLETE_CHIPS is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++
++#
++# NAND Flash Device Drivers
++#
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++CONFIG_MTD_NAND_AT91=y
++# CONFIG_MTD_NAND_NANDSIM is not set
++
++#
++# OneNAND Flash Device Drivers
++#
++# CONFIG_MTD_ONENAND is not set
++
++#
++# Parallel port support
++#
++# CONFIG_PARPORT is not set
++
++#
++# Plug and Play support
++#
++
++#
++# Block devices
++#
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++CONFIG_BLK_DEV_INITRD=y
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++CONFIG_SCSI_MULTI_LUN=y
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++
++#
++# SCSI low-level drivers
++#
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_SCSI_DEBUG is not set
++
++#
++# Multi-device support (RAID and LVM)
++#
++# CONFIG_MD is not set
++
++#
++# Fusion MPT device support
++#
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++
++#
++# I2O device support
++#
++
++#
++# Network device support
++#
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++
++#
++# PHY device support
++#
++# CONFIG_PHYLIB is not set
++
++#
++# Ethernet (10 or 100Mbit)
++#
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_SMC91X is not set
++CONFIG_DM9000=y
++
++#
++# Ethernet (1000 Mbit)
++#
++
++#
++# Ethernet (10000 Mbit)
++#
++
++#
++# Token Ring devices
++#
++
++#
++# Wireless LAN (non-hamradio)
++#
++# CONFIG_NET_RADIO is not set
++
++#
++# Wan interfaces
++#
++# CONFIG_WAN is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++
++#
++# ISDN subsystem
++#
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_TSDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_ATMEL=y
++CONFIG_SERIAL_ATMEL_CONSOLE=y
++# CONFIG_SERIAL_ATMEL_TTYAT is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++
++#
++# IPMI
++#
++# CONFIG_IPMI_HANDLER is not set
++
++#
++# Watchdog Cards
++#
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_NOWAYOUT=y
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++
++#
++# Ftape, the floppy tape device driver
++#
++# CONFIG_RAW_DRIVER is not set
++
++#
++# TPM devices
++#
++# CONFIG_TCG_TPM is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++CONFIG_I2C_AT91=y
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_PCA is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_SENSORS_EEPROM is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++
++#
++# Dallas's 1-wire bus
++#
++# CONFIG_W1 is not set
++
++#
++# Hardware Monitoring support
++#
++# CONFIG_HWMON is not set
++# CONFIG_HWMON_VID is not set
++
++#
++# Misc devices
++#
++# CONFIG_TIFM_CORE is not set
++
++#
++# LED devices
++#
++# CONFIG_NEW_LEDS is not set
++
++#
++# LED drivers
++#
++
++#
++# LED Triggers
++#
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++
++#
++# Digital Video Broadcasting Devices
++#
++# CONFIG_DVB is not set
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++
++#
++# USB support
++#
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++# CONFIG_USB_BANDWIDTH is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++CONFIG_USB_STORAGE_DEBUG=y
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_DPCM is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++# CONFIG_USB_AIPTEK is not set
++# CONFIG_USB_WACOM is not set
++# CONFIG_USB_ACECAD is not set
++# CONFIG_USB_KBTAB is not set
++# CONFIG_USB_POWERMATE is not set
++# CONFIG_USB_TOUCHSCREEN is not set
++# CONFIG_USB_YEALINK is not set
++# CONFIG_USB_XPAD is not set
++# CONFIG_USB_ATI_REMOTE is not set
++# CONFIG_USB_ATI_REMOTE2 is not set
++# CONFIG_USB_KEYSPAN_REMOTE is not set
++# CONFIG_USB_APPLETOUCH is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET_MII is not set
++# CONFIG_USB_USBNET is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_PXA2XX is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++CONFIG_USB_GADGET_AT91=y
++CONFIG_USB_AT91=y
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++# CONFIG_USB_GADGET_DUALSPEED is not set
++CONFIG_USB_ZERO=m
++# CONFIG_USB_ETH is not set
++CONFIG_USB_GADGETFS=m
++CONFIG_USB_FILE_STORAGE=m
++# CONFIG_USB_FILE_STORAGE_TEST is not set
++CONFIG_USB_G_SERIAL=m
++# CONFIG_USB_MIDI_GADGET is not set
++
++#
++# MMC/SD Card support
++#
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_AT91=m
++# CONFIG_MMC_TIFM_SD is not set
++
++#
++# Real Time Clock
++#
++CONFIG_RTC_LIB=y
++# CONFIG_RTC_CLASS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_EXT4DEV_FS is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_ROMFS_FS is not set
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++# CONFIG_MSDOS_FS is not set
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_RAMFS=y
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_JFFS_FS is not set
++# CONFIG_JFFS2_FS is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++
++#
++# Network File Systems
++#
++# CONFIG_NFS_FS is not set
++# CONFIG_NFSD is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++# CONFIG_9P_FS is not set
++
++#
++# Partition Types
++#
++# CONFIG_PARTITION_ADVANCED is not set
++CONFIG_MSDOS_PARTITION=y
++
++#
++# Native Language Support
++#
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++CONFIG_NLS_CODEPAGE_850=y
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++
++#
++# Profiling support
++#
++# CONFIG_PROFILING is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_MUST_CHECK=y
++# CONFIG_MAGIC_SYSRQ is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_KERNEL=y
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_DETECT_SOFTLOCKUP=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_RWSEMS is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_INFO is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_WAITQ is not set
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++
++#
++# Cryptographic options
++#
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++CONFIG_CRC32=y
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_PLIST=y
+diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/carmeva_defconfig linux-2.6.19/arch/arm/configs/carmeva_defconfig
+--- linux-2.6.19-final/arch/arm/configs/carmeva_defconfig Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/configs/carmeva_defconfig Thu Oct 12 17:07:38 2006
+@@ -474,7 +474,7 @@
+ # CONFIG_WATCHDOG is not set
+ # CONFIG_NVRAM is not set
+ # CONFIG_RTC is not set
+-# CONFIG_AT91_RTC is not set
++# CONFIG_AT91RM9200_RTC is not set
+ # CONFIG_DTLK is not set
+ # CONFIG_R3964 is not set
+
+diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/csb637_defconfig linux-2.6.19/arch/arm/configs/csb637_defconfig
+--- linux-2.6.19-final/arch/arm/configs/csb637_defconfig Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/configs/csb637_defconfig Thu Oct 12 17:07:38 2006
+@@ -623,7 +623,7 @@
+ # CONFIG_USBPCWATCHDOG is not set
+ # CONFIG_NVRAM is not set
+ CONFIG_RTC=y
+-# CONFIG_AT91_RTC is not set
++# CONFIG_AT91RM9200_RTC is not set
+ # CONFIG_DTLK is not set
+ # CONFIG_R3964 is not set
+
+diff -urN -x CVS linux-2.6.19-final/arch/arm/configs/kb9202_defconfig linux-2.6.19/arch/arm/configs/kb9202_defconfig
+--- linux-2.6.19-final/arch/arm/configs/kb9202_defconfig Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/configs/kb9202_defconfig Thu Oct 12 17:07:38 2006
+@@ -437,7 +437,7 @@
+ # CONFIG_WATCHDOG is not set
+ # CONFIG_NVRAM is not set
+ # CONFIG_RTC is not set
+-# CONFIG_AT91_RTC is not set
++# CONFIG_AT91RM9200_RTC is not set
+ # CONFIG_DTLK is not set
+ # CONFIG_R3964 is not set
+
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/Kconfig linux-2.6.19/arch/arm/mach-at91rm9200/Kconfig
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/Kconfig Mon Dec 4 16:32:44 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/Kconfig Wed Nov 22 09:24:11 2006
+@@ -2,7 +2,8 @@
+
+ menu "Atmel AT91 System-on-Chip"
+
+-comment "Atmel AT91 Processors"
++choice
++ prompt "Atmel AT91 Processor"
+
+ config ARCH_AT91RM9200
+ bool "AT91RM9200"
+@@ -13,6 +14,8 @@
+ config ARCH_AT91SAM9261
+ bool "AT91SAM9261"
+
++endchoice
++
+ # ----------------------------------------------------------
+
+ if ARCH_AT91RM9200
+@@ -33,7 +36,6 @@
+ Select this if you are using Atmel's AT91RM9200-DK Development board.
+ (Discontinued)
+
+-
+ config MACH_AT91RM9200EK
+ bool "Atmel AT91RM9200-EK Evaluation Kit"
+ depends on ARCH_AT91RM9200
+@@ -90,6 +92,13 @@
+
+ comment "AT91SAM9260 Board Type"
+
++config MACH_AT91SAM9260EK
++ bool "Atmel AT91SAM9260-EK Evaluation Kit"
++ depends on ARCH_AT91SAM9260
++ help
++ Select this if you are using Atmel's AT91SAM9260-EK Evaluation Kit.
++ <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
++
+ endif
+
+ # ----------------------------------------------------------
+@@ -98,8 +107,31 @@
+
+ comment "AT91SAM9261 Board Type"
+
++config MACH_AT91SAM9261EK
++ bool "Atmel AT91SAM9261-EK Evaluation Kit"
++ depends on ARCH_AT91SAM9261
++ help
++ Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
++ <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
++
+ endif
+
++# ----------------------------------------------------------
++
++comment "AT91 Board Options"
++
++config MTD_AT91_DATAFLASH_CARD
++ bool "Enable DataFlash Card support"
++ depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK)
++ help
++ Enable support for the DataFlash card.
++
++config MTD_NAND_AT91_BUSWIDTH_16
++ bool "Enable 16-bit data bus interface to NAND flash"
++ depends on (MACH_AT91SAM9261EK || MACH_AT91SAM9260EK)
++ help
++ On AT91SAM926x boards both types of NAND flash can be present
++ (8 and 16 bit data bus width).
+
+ # ----------------------------------------------------------
+
+@@ -111,6 +143,13 @@
+ Select this if you need to program one or more of the PCK0..PCK3
+ programmable clock outputs.
+
++config AT91_SLOW_CLOCK
++ bool "Suspend-to-RAM uses slow clock mode (EXPERIMENTAL)"
++ depends on PM && EXPERIMENTAL
++ help
++ Select this if you wish to put the CPU into slow clock mode
++ while in the "Suspend to RAM" state, to save more power.
++
+ endmenu
+
+ endif
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/Makefile linux-2.6.19/arch/arm/mach-at91rm9200/Makefile
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/Makefile Mon Dec 4 16:32:44 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/Makefile Thu Nov 16 11:45:54 2006
+@@ -2,19 +2,20 @@
+ # Makefile for the linux kernel.
+ #
+
+-obj-y := clock.o irq.o gpio.o devices.o
++obj-y := clock.o irq.o gpio.o
+ obj-m :=
+ obj-n :=
+ obj- :=
+
+ obj-$(CONFIG_PM) += pm.o
++obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
+
+ # CPU-specific support
+-obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o
+-obj-$(CONFIG_ARCH_AT91SAM9260) +=
+-obj-$(CONFIG_ARCH_AT91SAM9261) +=
++obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
++obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
++obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
+
+-# AT91RM9200 Board-specific support
++# AT91RM9200 board-specific support
+ obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
+ obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
+ obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
+@@ -26,8 +27,10 @@
+ obj-$(CONFIG_MACH_KAFA) += board-kafa.o
+
+ # AT91SAM9260 board-specific support
++obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
+
+ # AT91SAM9261 board-specific support
++obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
+
+ # LEDs support
+ led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
+@@ -39,7 +42,7 @@
+ obj-$(CONFIG_LEDS) += $(led-y)
+
+ # VGA support
+-#obj-$(CONFIG_FB_S1D13XXX) += ics1523.o
++obj-$(CONFIG_FB_S1D13XXX) += ics1523.o
+
+
+ ifeq ($(CONFIG_PM_DEBUG),y)
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200.c linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200.c Fri Nov 3 19:22:15 2006
+@@ -14,8 +14,10 @@
+
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
++#include <asm/arch/at91rm9200.h>
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/at91_st.h>
+
+-#include <asm/hardware.h>
+ #include "generic.h"
+ #include "clock.h"
+
+@@ -26,32 +28,12 @@
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+- .virtual = AT91_VA_BASE_SPI,
+- .pfn = __phys_to_pfn(AT91RM9200_BASE_SPI),
+- .length = SZ_16K,
+- .type = MT_DEVICE,
+- }, {
+ .virtual = AT91_VA_BASE_EMAC,
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC),
+ .length = SZ_16K,
+ .type = MT_DEVICE,
+ }, {
+- .virtual = AT91_VA_BASE_TWI,
+- .pfn = __phys_to_pfn(AT91RM9200_BASE_TWI),
+- .length = SZ_16K,
+- .type = MT_DEVICE,
+- }, {
+- .virtual = AT91_VA_BASE_MCI,
+- .pfn = __phys_to_pfn(AT91RM9200_BASE_MCI),
+- .length = SZ_16K,
+- .type = MT_DEVICE,
+- }, {
+- .virtual = AT91_VA_BASE_UDP,
+- .pfn = __phys_to_pfn(AT91RM9200_BASE_UDP),
+- .length = SZ_16K,
+- .type = MT_DEVICE,
+- }, {
+- .virtual = AT91_SRAM_VIRT_BASE,
++ .virtual = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE,
+ .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE),
+ .length = AT91RM9200_SRAM_SIZE,
+ .type = MT_DEVICE,
+@@ -222,6 +204,16 @@
+ }
+ };
+
++static void at91rm9200_reset(void)
++{
++ /*
++ * Perform a hardware reset with the use of the Watchdog timer.
++ */
++ at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
++ at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
++}
++
++
+ /* --------------------------------------------------------------------
+ * AT91RM9200 processor initialization
+ * -------------------------------------------------------------------- */
+@@ -230,6 +222,12 @@
+ /* Map peripherals */
+ iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
+
++ at91_arch_reset = at91rm9200_reset;
++ at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
++ | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
++ | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
++ | (1 << AT91RM9200_ID_IRQ6);
++
+ /* Init clock subsystem */
+ at91_clock_init(main_clock);
+
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200_devices.c linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200_devices.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200_devices.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200_devices.c Fri Dec 1 16:10:47 2006
+@@ -0,0 +1,901 @@
++/*
++ * arch/arm/mach-at91rm9200/at91rm9200_devices.c
++ *
++ * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
++ * Copyright (C) 2005 David Brownell
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++
++#include <linux/platform_device.h>
++
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91rm9200.h>
++#include <asm/arch/at91rm9200_mc.h>
++
++#include "generic.h"
++
++#define SZ_512 0x00000200
++#define SZ_256 0x00000100
++#define SZ_16 0x00000010
++
++/* --------------------------------------------------------------------
++ * USB Host
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
++static u64 ohci_dmamask = 0xffffffffUL;
++static struct at91_usbh_data usbh_data;
++
++static struct resource usbh_resources[] = {
++ [0] = {
++ .start = AT91RM9200_UHP_BASE,
++ .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_UHP,
++ .end = AT91RM9200_ID_UHP,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91rm9200_usbh_device = {
++ .name = "at91_ohci",
++ .id = -1,
++ .dev = {
++ .dma_mask = &ohci_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = &usbh_data,
++ },
++ .resource = usbh_resources,
++ .num_resources = ARRAY_SIZE(usbh_resources),
++};
++
++void __init at91_add_device_usbh(struct at91_usbh_data *data)
++{
++ if (!data)
++ return;
++
++ usbh_data = *data;
++ platform_device_register(&at91rm9200_usbh_device);
++}
++#else
++void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * USB Device (Gadget)
++ * -------------------------------------------------------------------- */
++
++#ifdef CONFIG_USB_GADGET_AT91
++static struct at91_udc_data udc_data;
++
++static struct resource udc_resources[] = {
++ [0] = {
++ .start = AT91RM9200_BASE_UDP,
++ .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_UDP,
++ .end = AT91RM9200_ID_UDP,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91rm9200_udc_device = {
++ .name = "at91_udc",
++ .id = -1,
++ .dev = {
++ .platform_data = &udc_data,
++ },
++ .resource = udc_resources,
++ .num_resources = ARRAY_SIZE(udc_resources),
++};
++
++void __init at91_add_device_udc(struct at91_udc_data *data)
++{
++ if (!data)
++ return;
++
++ if (data->vbus_pin) {
++ at91_set_gpio_input(data->vbus_pin, 0);
++ at91_set_deglitch(data->vbus_pin, 1);
++ }
++ if (data->pullup_pin)
++ at91_set_gpio_output(data->pullup_pin, 0);
++
++ udc_data = *data;
++ platform_device_register(&at91rm9200_udc_device);
++}
++#else
++void __init at91_add_device_udc(struct at91_udc_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * Ethernet
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
++static u64 eth_dmamask = 0xffffffffUL;
++static struct eth_platform_data eth_data;
++
++static struct resource eth_resources[] = {
++ [0] = {
++ .start = AT91_VA_BASE_EMAC,
++ .end = AT91_VA_BASE_EMAC + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_EMAC,
++ .end = AT91RM9200_ID_EMAC,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91rm9200_eth_device = {
++ .name = "at91_ether",
++ .id = -1,
++ .dev = {
++ .dma_mask = ð_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = ð_data,
++ },
++ .resource = eth_resources,
++ .num_resources = ARRAY_SIZE(eth_resources),
++};
++
++void __init at91_add_device_eth(struct eth_platform_data *data)
++{
++ if (!data)
++ return;
++
++ if (data->phy_irq_pin) {
++ at91_set_gpio_input(data->phy_irq_pin, 0);
++ at91_set_deglitch(data->phy_irq_pin, 1);
++ }
++
++ /* Pins used for MII and RMII */
++ at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
++ at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
++ at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
++ at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
++ at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
++ at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
++ at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
++ at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
++ at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
++ at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
++
++ if (!data->is_rmii) {
++ at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
++ at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
++ at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
++ at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
++ at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
++ at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
++ at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
++ at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
++ }
++
++ eth_data = *data;
++ platform_device_register(&at91rm9200_eth_device);
++}
++#else
++void __init at91_add_device_eth(struct eth_platform_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * Compact Flash / PCMCIA
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
++static struct at91_cf_data cf_data;
++
++#define CF_BASE AT91_CHIPSELECT_4
++
++static struct resource cf_resources[] = {
++ [0] = {
++ .start = CF_BASE,
++ /* ties up CS4, CS5 and CS6 */
++ .end = CF_BASE + (0x30000000 - 1),
++ .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
++ },
++};
++
++static struct platform_device at91rm9200_cf_device = {
++ .name = "at91_cf",
++ .id = -1,
++ .dev = {
++ .platform_data = &cf_data,
++ },
++ .resource = cf_resources,
++ .num_resources = ARRAY_SIZE(cf_resources),
++};
++
++void __init at91_add_device_cf(struct at91_cf_data *data)
++{
++ unsigned int csa;
++
++ if (!data)
++ return;
++
++ data->chipselect = 4; /* can only use EBI ChipSelect 4 */
++
++ /* CF takes over CS4, CS5, CS6 */
++ csa = at91_sys_read(AT91_EBI_CSA);
++ at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
++
++ /*
++ * Static memory controller timing adjustments.
++ * REVISIT: these timings are in terms of MCK cycles, so
++ * when MCK changes (cpufreq etc) so must these values...
++ */
++ at91_sys_write(AT91_SMC_CSR(4),
++ AT91_SMC_ACSS_STD
++ | AT91_SMC_DBW_16
++ | AT91_SMC_BAT
++ | AT91_SMC_WSEN
++ | AT91_SMC_NWS_(32) /* wait states */
++ | AT91_SMC_RWSETUP_(6) /* setup time */
++ | AT91_SMC_RWHOLD_(4) /* hold time */
++ );
++
++ /* input/irq */
++ if (data->irq_pin) {
++ at91_set_gpio_input(data->irq_pin, 1);
++ at91_set_deglitch(data->irq_pin, 1);
++ }
++ at91_set_gpio_input(data->det_pin, 1);
++ at91_set_deglitch(data->det_pin, 1);
++
++ /* outputs, initially off */
++ if (data->vcc_pin)
++ at91_set_gpio_output(data->vcc_pin, 0);
++ at91_set_gpio_output(data->rst_pin, 0);
++
++ /* force poweron defaults for these pins ... */
++ at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
++ at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
++ at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
++ at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
++
++ /* nWAIT is _not_ a default setting */
++ at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
++
++ cf_data = *data;
++ platform_device_register(&at91rm9200_cf_device);
++}
++#else
++void __init at91_add_device_cf(struct at91_cf_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * MMC / SD
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
++static u64 mmc_dmamask = 0xffffffffUL;
++static struct at91_mmc_data mmc_data;
++
++static struct resource mmc_resources[] = {
++ [0] = {
++ .start = AT91RM9200_BASE_MCI,
++ .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_MCI,
++ .end = AT91RM9200_ID_MCI,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91rm9200_mmc_device = {
++ .name = "at91_mci",
++ .id = -1,
++ .dev = {
++ .dma_mask = &mmc_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = &mmc_data,
++ },
++ .resource = mmc_resources,
++ .num_resources = ARRAY_SIZE(mmc_resources),
++};
++
++void __init at91_add_device_mmc(struct at91_mmc_data *data)
++{
++ if (!data)
++ return;
++
++ /* input/irq */
++ if (data->det_pin) {
++ at91_set_gpio_input(data->det_pin, 1);
++ at91_set_deglitch(data->det_pin, 1);
++ }
++ if (data->wp_pin)
++ at91_set_gpio_input(data->wp_pin, 1);
++ if (data->vcc_pin)
++ at91_set_gpio_output(data->vcc_pin, 0);
++
++ /* CLK */
++ at91_set_A_periph(AT91_PIN_PA27, 0);
++
++ if (data->slot_b) {
++ /* CMD */
++ at91_set_B_periph(AT91_PIN_PA8, 1);
++
++ /* DAT0, maybe DAT1..DAT3 */
++ at91_set_B_periph(AT91_PIN_PA9, 1);
++ if (data->wire4) {
++ at91_set_B_periph(AT91_PIN_PA10, 1);
++ at91_set_B_periph(AT91_PIN_PA11, 1);
++ at91_set_B_periph(AT91_PIN_PA12, 1);
++ }
++ } else {
++ /* CMD */
++ at91_set_A_periph(AT91_PIN_PA28, 1);
++
++ /* DAT0, maybe DAT1..DAT3 */
++ at91_set_A_periph(AT91_PIN_PA29, 1);
++ if (data->wire4) {
++ at91_set_B_periph(AT91_PIN_PB3, 1);
++ at91_set_B_periph(AT91_PIN_PB4, 1);
++ at91_set_B_periph(AT91_PIN_PB5, 1);
++ }
++ }
++
++ mmc_data = *data;
++ platform_device_register(&at91rm9200_mmc_device);
++}
++#else
++void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * NAND / SmartMedia
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
++static struct at91_nand_data nand_data;
++
++#define NAND_BASE AT91_CHIPSELECT_3
++
++static struct resource nand_resources[] = {
++ {
++ .start = NAND_BASE,
++ .end = NAND_BASE + SZ_8M - 1,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct platform_device at91rm9200_nand_device = {
++ .name = "at91_nand",
++ .id = -1,
++ .dev = {
++ .platform_data = &nand_data,
++ },
++ .resource = nand_resources,
++ .num_resources = ARRAY_SIZE(nand_resources),
++};
++
++void __init at91_add_device_nand(struct at91_nand_data *data)
++{
++ unsigned int csa;
++
++ if (!data)
++ return;
++
++ /* enable the address range of CS3 */
++ csa = at91_sys_read(AT91_EBI_CSA);
++ at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
++
++ /* set the bus interface characteristics */
++ at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
++ | AT91_SMC_NWS_(5)
++ | AT91_SMC_TDF_(1)
++ | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
++ | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
++ );
++
++ /* enable pin */
++ if (data->enable_pin)
++ at91_set_gpio_output(data->enable_pin, 1);
++
++ /* ready/busy pin */
++ if (data->rdy_pin)
++ at91_set_gpio_input(data->rdy_pin, 1);
++
++ /* card detect pin */
++ if (data->det_pin)
++ at91_set_gpio_input(data->det_pin, 1);
++
++ at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
++ at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
++
++ nand_data = *data;
++ platform_device_register(&at91rm9200_nand_device);
++}
++#else
++void __init at91_add_device_nand(struct at91_nand_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * TWI (i2c)
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
++
++static struct resource twi_resources[] = {
++ [0] = {
++ .start = AT91RM9200_BASE_TWI,
++ .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_TWI,
++ .end = AT91RM9200_ID_TWI,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91rm9200_twi_device = {
++ .name = "at91_i2c",
++ .id = -1,
++ .resource = twi_resources,
++ .num_resources = ARRAY_SIZE(twi_resources),
++};
++
++void __init at91_add_device_i2c(void)
++{
++ /* pins used for TWI interface */
++ at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
++ at91_set_multi_drive(AT91_PIN_PA25, 1);
++
++ at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
++ at91_set_multi_drive(AT91_PIN_PA26, 1);
++
++ platform_device_register(&at91rm9200_twi_device);
++}
++#else
++void __init at91_add_device_i2c(void) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * SPI
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
++static u64 spi_dmamask = 0xffffffffUL;
++
++static struct resource spi_resources[] = {
++ [0] = {
++ .start = AT91RM9200_BASE_SPI,
++ .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_SPI,
++ .end = AT91RM9200_ID_SPI,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91rm9200_spi_device = {
++ .name = "at91_spi",
++ .id = 0,
++ .dev = {
++ .dma_mask = &spi_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = spi_resources,
++ .num_resources = ARRAY_SIZE(spi_resources),
++};
++
++static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
++
++void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
++{
++ int i;
++ unsigned long cs_pin;
++
++ at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
++ at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
++ at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
++
++ /* Enable SPI chip-selects */
++ for (i = 0; i < nr_devices; i++) {
++ if (devices[i].controller_data)
++ cs_pin = (unsigned long) devices[i].controller_data;
++ else
++ cs_pin = spi_standard_cs[devices[i].chip_select];
++
++#ifdef CONFIG_SPI_AT91_MANUAL_CS
++ at91_set_gpio_output(cs_pin, 1);
++#else
++ at91_set_A_periph(cs_pin, 0);
++#endif
++
++ /* pass chip-select pin to driver */
++ devices[i].controller_data = (void *) cs_pin;
++ }
++
++ spi_register_board_info(devices, nr_devices);
++ at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi");
++ platform_device_register(&at91rm9200_spi_device);
++}
++#else
++void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * RTC
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
++static struct platform_device at91rm9200_rtc_device = {
++ .name = "at91_rtc",
++ .id = -1,
++ .num_resources = 0,
++};
++
++static void __init at91_add_device_rtc(void)
++{
++ platform_device_register(&at91rm9200_rtc_device);
++}
++#else
++static void __init at91_add_device_rtc(void) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * Watchdog
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
++static struct platform_device at91rm9200_wdt_device = {
++ .name = "at91_wdt",
++ .id = -1,
++ .num_resources = 0,
++};
++
++static void __init at91_add_device_watchdog(void)
++{
++ platform_device_register(&at91rm9200_wdt_device);
++}
++#else
++static void __init at91_add_device_watchdog(void) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * LEDs
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_LEDS)
++u8 at91_leds_cpu;
++u8 at91_leds_timer;
++
++void __init at91_init_leds(u8 cpu_led, u8 timer_led)
++{
++ at91_leds_cpu = cpu_led;
++ at91_leds_timer = timer_led;
++}
++#else
++void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
++#endif
++
++
++#if defined(CONFIG_NEW_LEDS)
++
++static struct platform_device at91_leds = {
++ .name = "at91_leds",
++ .id = -1,
++};
++
++void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
++{
++ if (!nr)
++ return;
++
++ at91_leds.dev.platform_data = leds;
++
++ for ( ; nr; nr--, leds++) {
++ leds->index = nr; /* first record stores number of leds */
++ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
++ }
++
++ platform_device_register(&at91_leds);
++}
++#else
++void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * UART
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_SERIAL_ATMEL)
++static struct resource dbgu_resources[] = {
++ [0] = {
++ .start = AT91_VA_BASE_SYS + AT91_DBGU,
++ .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91_ID_SYS,
++ .end = AT91_ID_SYS,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data dbgu_data = {
++ .use_dma_tx = 0,
++ .use_dma_rx = 0, /* DBGU not capable of receive DMA */
++ .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
++};
++
++static struct platform_device at91rm9200_dbgu_device = {
++ .name = "atmel_usart",
++ .id = 0,
++ .dev = {
++ .platform_data = &dbgu_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = dbgu_resources,
++ .num_resources = ARRAY_SIZE(dbgu_resources),
++};
++
++static inline void configure_dbgu_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
++ at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
++}
++
++static struct resource uart0_resources[] = {
++ [0] = {
++ .start = AT91RM9200_BASE_US0,
++ .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_US0,
++ .end = AT91RM9200_ID_US0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart0_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91rm9200_uart0_device = {
++ .name = "atmel_usart",
++ .id = 1,
++ .dev = {
++ .platform_data = &uart0_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart0_resources,
++ .num_resources = ARRAY_SIZE(uart0_resources),
++};
++
++static inline void configure_usart0_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
++ at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
++ at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
++
++ /*
++ * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
++ * We need to drive the pin manually. Default is off (RTS is active low).
++ */
++ at91_set_gpio_output(AT91_PIN_PA21, 1);
++}
++
++static struct resource uart1_resources[] = {
++ [0] = {
++ .start = AT91RM9200_BASE_US1,
++ .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_US1,
++ .end = AT91RM9200_ID_US1,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart1_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91rm9200_uart1_device = {
++ .name = "atmel_usart",
++ .id = 2,
++ .dev = {
++ .platform_data = &uart1_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart1_resources,
++ .num_resources = ARRAY_SIZE(uart1_resources),
++};
++
++static inline void configure_usart1_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
++ at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
++ at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
++ at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
++ at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
++ at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
++ at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
++ at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
++}
++
++static struct resource uart2_resources[] = {
++ [0] = {
++ .start = AT91RM9200_BASE_US2,
++ .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_US2,
++ .end = AT91RM9200_ID_US2,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart2_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91rm9200_uart2_device = {
++ .name = "atmel_usart",
++ .id = 3,
++ .dev = {
++ .platform_data = &uart2_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart2_resources,
++ .num_resources = ARRAY_SIZE(uart2_resources),
++};
++
++static inline void configure_usart2_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
++ at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
++}
++
++static struct resource uart3_resources[] = {
++ [0] = {
++ .start = AT91RM9200_BASE_US3,
++ .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91RM9200_ID_US3,
++ .end = AT91RM9200_ID_US3,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart3_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91rm9200_uart3_device = {
++ .name = "atmel_usart",
++ .id = 4,
++ .dev = {
++ .platform_data = &uart3_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart3_resources,
++ .num_resources = ARRAY_SIZE(uart3_resources),
++};
++
++static inline void configure_usart3_pins(void)
++{
++ at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
++ at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
++}
++
++struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
++struct platform_device *atmel_default_console_device; /* the serial console device */
++
++void __init at91_init_serial(struct at91_uart_config *config)
++{
++ int i;
++
++ /* Fill in list of supported UARTs */
++ for (i = 0; i < config->nr_tty; i++) {
++ switch (config->tty_map[i]) {
++ case 0:
++ configure_usart0_pins();
++ at91_uarts[i] = &at91rm9200_uart0_device;
++ at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
++ break;
++ case 1:
++ configure_usart1_pins();
++ at91_uarts[i] = &at91rm9200_uart1_device;
++ at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
++ break;
++ case 2:
++ configure_usart2_pins();
++ at91_uarts[i] = &at91rm9200_uart2_device;
++ at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
++ break;
++ case 3:
++ configure_usart3_pins();
++ at91_uarts[i] = &at91rm9200_uart3_device;
++ at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
++ break;
++ case 4:
++ configure_dbgu_pins();
++ at91_uarts[i] = &at91rm9200_dbgu_device;
++ at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
++ break;
++ default:
++ continue;
++ }
++ at91_uarts[i]->id = i; /* update ID number to mapped ID */
++ }
++
++ /* Set serial console device */
++ if (config->console_tty < ATMEL_MAX_UART)
++ atmel_default_console_device = at91_uarts[config->console_tty];
++ if (!atmel_default_console_device)
++ printk(KERN_INFO "AT91: No default serial console defined.\n");
++}
++
++void __init at91_add_device_serial(void)
++{
++ int i;
++
++ for (i = 0; i < ATMEL_MAX_UART; i++) {
++ if (at91_uarts[i])
++ platform_device_register(at91_uarts[i]);
++ }
++}
++#else
++void __init at91_init_serial(struct at91_uart_config *config) {}
++void __init at91_add_device_serial(void) {}
++#endif
++
++
++/* -------------------------------------------------------------------- */
++
++/*
++ * These devices are always present and don't need any board-specific
++ * setup.
++ */
++static int __init at91_add_standard_devices(void)
++{
++ at91_add_device_rtc();
++ at91_add_device_watchdog();
++ return 0;
++}
++
++arch_initcall(at91_add_standard_devices);
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200_time.c linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200_time.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91rm9200_time.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/at91rm9200_time.c Thu Nov 16 11:41:09 2006
+@@ -30,6 +30,8 @@
+ #include <asm/io.h>
+ #include <asm/mach/time.h>
+
++#include <asm/arch/at91_st.h>
++
+ static unsigned long last_crtr;
+
+ /*
+@@ -99,6 +101,9 @@
+ /* Set Period Interval timer */
+ at91_sys_write(AT91_ST_PIMR, LATCH);
+
++ /* Clear any pending interrupts */
++ (void) at91_sys_read(AT91_ST_SR);
++
+ /* Enable Period Interval Timer interrupt */
+ at91_sys_write(AT91_ST_IER, AT91_ST_PITS);
+ }
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9260.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9260.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9260.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9260.c Mon Nov 20 10:52:16 2006
+@@ -0,0 +1,294 @@
++/*
++ * arch/arm/mach-at91rm9200/at91sam9260.c
++ *
++ * Copyright (C) 2006 SAN People
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/module.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/arch/at91sam9260.h>
++#include <asm/arch/at91_pmc.h>
++
++#include "generic.h"
++#include "clock.h"
++
++static struct map_desc at91sam9260_io_desc[] __initdata = {
++ {
++ .virtual = AT91_VA_BASE_SYS,
++ .pfn = __phys_to_pfn(AT91_BASE_SYS),
++ .length = SZ_16K,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
++ .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
++ .length = AT91SAM9260_SRAM0_SIZE,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
++ .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
++ .length = AT91SAM9260_SRAM1_SIZE,
++ .type = MT_DEVICE,
++ },
++};
++
++/* --------------------------------------------------------------------
++ * Clocks
++ * -------------------------------------------------------------------- */
++
++/*
++ * The peripheral clocks.
++ */
++static struct clk pioA_clk = {
++ .name = "pioA_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk pioB_clk = {
++ .name = "pioB_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk pioC_clk = {
++ .name = "pioC_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk adc_clk = {
++ .name = "adc_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_ADC,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart0_clk = {
++ .name = "usart0_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_US0,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart1_clk = {
++ .name = "usart1_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_US1,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart2_clk = {
++ .name = "usart2_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_US2,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk mmc_clk = {
++ .name = "mci_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_MCI,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk udc_clk = {
++ .name = "udc_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_UDP,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk twi_clk = {
++ .name = "twi_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_TWI,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk spi0_clk = {
++ .name = "spi0_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk spi1_clk = {
++ .name = "spi1_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk ohci_clk = {
++ .name = "ohci_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_UHP,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk ether_clk = {
++ .name = "ether_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk isi_clk = {
++ .name = "isi_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_ISI,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart3_clk = {
++ .name = "usart3_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_US3,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart4_clk = {
++ .name = "usart4_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_US4,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart5_clk = {
++ .name = "usart5_clk",
++ .pmc_mask = 1 << AT91SAM9260_ID_US5,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++
++static struct clk *periph_clocks[] __initdata = {
++ &pioA_clk,
++ &pioB_clk,
++ &pioC_clk,
++ &adc_clk,
++ &usart0_clk,
++ &usart1_clk,
++ &usart2_clk,
++ &mmc_clk,
++ &udc_clk,
++ &twi_clk,
++ &spi0_clk,
++ &spi1_clk,
++ // ssc
++ // tc0 .. tc2
++ &ohci_clk,
++ ðer_clk,
++ &isi_clk,
++ &usart3_clk,
++ &usart4_clk,
++ &usart5_clk,
++ // tc3 .. tc5
++ // irq0 .. irq2
++};
++
++/*
++ * The two programmable clocks.
++ * You must configure pin multiplexing to bring these signals out.
++ */
++static struct clk pck0 = {
++ .name = "pck0",
++ .pmc_mask = AT91_PMC_PCK0,
++ .type = CLK_TYPE_PROGRAMMABLE,
++ .id = 0,
++};
++static struct clk pck1 = {
++ .name = "pck1",
++ .pmc_mask = AT91_PMC_PCK1,
++ .type = CLK_TYPE_PROGRAMMABLE,
++ .id = 1,
++};
++
++static void __init at91sam9260_register_clocks(void)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
++ clk_register(periph_clocks[i]);
++
++ clk_register(&pck0);
++ clk_register(&pck1);
++}
++
++/* --------------------------------------------------------------------
++ * GPIO
++ * -------------------------------------------------------------------- */
++
++static struct at91_gpio_bank at91sam9260_gpio[] = {
++ {
++ .id = AT91SAM9260_ID_PIOA,
++ .offset = AT91_PIOA,
++ .clock = &pioA_clk,
++ }, {
++ .id = AT91SAM9260_ID_PIOB,
++ .offset = AT91_PIOB,
++ .clock = &pioB_clk,
++ }, {
++ .id = AT91SAM9260_ID_PIOC,
++ .offset = AT91_PIOC,
++ .clock = &pioC_clk,
++ }
++};
++
++static void at91sam9260_reset(void)
++{
++#warning "Implement CPU reset"
++}
++
++
++/* --------------------------------------------------------------------
++ * AT91SAM9260 processor initialization
++ * -------------------------------------------------------------------- */
++
++void __init at91sam9260_initialize(unsigned long main_clock)
++{
++ /* Map peripherals */
++ iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
++
++ at91_arch_reset = at91sam9260_reset;
++ at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
++ | (1 << AT91SAM9260_ID_IRQ2);
++
++ /* Init clock subsystem */
++ at91_clock_init(main_clock);
++
++ /* Register the processor-specific clocks */
++ at91sam9260_register_clocks();
++
++ /* Register GPIO subsystem */
++ at91_gpio_init(at91sam9260_gpio, 3);
++}
++
++/* --------------------------------------------------------------------
++ * Interrupt initialization
++ * -------------------------------------------------------------------- */
++
++/*
++ * The default interrupt priority levels (0 = lowest, 7 = highest).
++ */
++static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
++ 7, /* Advanced Interrupt Controller */
++ 7, /* System Peripherals */
++ 0, /* Parallel IO Controller A */
++ 0, /* Parallel IO Controller B */
++ 0, /* Parallel IO Controller C */
++ 0, /* Analog-to-Digital Converter */
++ 6, /* USART 0 */
++ 6, /* USART 1 */
++ 6, /* USART 2 */
++ 0, /* Multimedia Card Interface */
++ 4, /* USB Device Port */
++ 0, /* Two-Wire Interface */
++ 6, /* Serial Peripheral Interface 0 */
++ 6, /* Serial Peripheral Interface 1 */
++ 5, /* Serial Synchronous Controller */
++ 0,
++ 0,
++ 0, /* Timer Counter 0 */
++ 0, /* Timer Counter 1 */
++ 0, /* Timer Counter 2 */
++ 3, /* USB Host port */
++ 3, /* Ethernet */
++ 0, /* Image Sensor Interface */
++ 6, /* USART 3 */
++ 6, /* USART 4 */
++ 6, /* USART 5 */
++ 0, /* Timer Counter 3 */
++ 0, /* Timer Counter 4 */
++ 0, /* Timer Counter 5 */
++ 0, /* Advanced Interrupt Controller */
++ 0, /* Advanced Interrupt Controller */
++ 0, /* Advanced Interrupt Controller */
++};
++
++void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
++{
++ if (!priority)
++ priority = at91sam9260_default_irq_priority;
++
++ /* Initialize the AIC interrupt controller */
++ at91_aic_init(priority);
++
++ /* Enable GPIO interrupts */
++ at91_gpio_irq_setup();
++}
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9260_devices.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9260_devices.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9260_devices.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9260_devices.c Thu Nov 23 16:37:24 2006
+@@ -0,0 +1,892 @@
++/*
++ * arch/arm/mach-at91rm9200/at91sam9260_devices.c
++ *
++ * Copyright (C) 2006 Atmel
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++
++#include <linux/platform_device.h>
++
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91sam9260.h>
++#include <asm/arch/at91sam926x_mc.h>
++
++#include "generic.h"
++
++#define SZ_512 0x00000200
++#define SZ_256 0x00000100
++#define SZ_16 0x00000010
++
++/* --------------------------------------------------------------------
++ * USB Host
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
++static u64 ohci_dmamask = 0xffffffffUL;
++static struct at91_usbh_data usbh_data;
++
++static struct resource usbh_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_UHP_BASE,
++ .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_UHP,
++ .end = AT91SAM9260_ID_UHP,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91_usbh_device = {
++ .name = "at91_ohci",
++ .id = -1,
++ .dev = {
++ .dma_mask = &ohci_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = &usbh_data,
++ },
++ .resource = usbh_resources,
++ .num_resources = ARRAY_SIZE(usbh_resources),
++};
++
++void __init at91_add_device_usbh(struct at91_usbh_data *data)
++{
++ if (!data)
++ return;
++
++ usbh_data = *data;
++ platform_device_register(&at91_usbh_device);
++}
++#else
++void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * USB Device (Gadget)
++ * -------------------------------------------------------------------- */
++
++#ifdef CONFIG_USB_GADGET_AT91
++static struct at91_udc_data udc_data;
++
++static struct resource udc_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_UDP,
++ .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_UDP,
++ .end = AT91SAM9260_ID_UDP,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91_udc_device = {
++ .name = "at91_udc",
++ .id = -1,
++ .dev = {
++ .platform_data = &udc_data,
++ },
++ .resource = udc_resources,
++ .num_resources = ARRAY_SIZE(udc_resources),
++};
++
++void __init at91_add_device_udc(struct at91_udc_data *data)
++{
++ if (!data)
++ return;
++
++ if (data->vbus_pin) {
++ at91_set_gpio_input(data->vbus_pin, 0);
++ at91_set_deglitch(data->vbus_pin, 1);
++ }
++
++ /* Pullup pin is handled internally by USB device peripheral */
++
++ udc_data = *data;
++ platform_device_register(&at91_udc_device);
++}
++#else
++void __init at91_add_device_udc(struct at91_udc_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * Ethernet
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
++static u64 eth_dmamask = 0xffffffffUL;
++static struct eth_platform_data eth_data;
++
++static struct resource eth_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_EMAC,
++ .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_EMAC,
++ .end = AT91SAM9260_ID_EMAC,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9260_eth_device = {
++ .name = "macb",
++ .id = -1,
++ .dev = {
++ .dma_mask = ð_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = ð_data,
++ },
++ .resource = eth_resources,
++ .num_resources = ARRAY_SIZE(eth_resources),
++};
++
++void __init at91_add_device_eth(struct eth_platform_data *data)
++{
++ if (!data)
++ return;
++
++ if (data->phy_irq_pin) {
++ at91_set_gpio_input(data->phy_irq_pin, 0);
++ at91_set_deglitch(data->phy_irq_pin, 1);
++ }
++
++ /* Pins used for MII and RMII */
++ at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
++ at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
++ at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
++ at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
++ at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
++ at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
++ at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
++ at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
++ at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
++ at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
++
++ if (!data->is_rmii) {
++ at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
++ at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
++ at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
++ at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
++ at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
++ at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
++ at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
++ at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
++ }
++
++ eth_data = *data;
++ platform_device_register(&at91sam9260_eth_device);
++}
++#else
++void __init at91_add_device_eth(struct eth_platform_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * MMC / SD
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
++static u64 mmc_dmamask = 0xffffffffUL;
++static struct at91_mmc_data mmc_data;
++
++static struct resource mmc_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_MCI,
++ .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_MCI,
++ .end = AT91SAM9260_ID_MCI,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9260_mmc_device = {
++ .name = "at91_mci",
++ .id = -1,
++ .dev = {
++ .dma_mask = &mmc_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = &mmc_data,
++ },
++ .resource = mmc_resources,
++ .num_resources = ARRAY_SIZE(mmc_resources),
++};
++
++void __init at91_add_device_mmc(struct at91_mmc_data *data)
++{
++ if (!data)
++ return;
++
++ /* input/irq */
++ if (data->det_pin) {
++ at91_set_gpio_input(data->det_pin, 1);
++ at91_set_deglitch(data->det_pin, 1);
++ }
++ if (data->wp_pin)
++ at91_set_gpio_input(data->wp_pin, 1);
++ if (data->vcc_pin)
++ at91_set_gpio_output(data->vcc_pin, 0);
++
++ /* CLK */
++ at91_set_A_periph(AT91_PIN_PA8, 0);
++
++ if (data->slot_b) {
++ /* CMD */
++ at91_set_B_periph(AT91_PIN_PA1, 1);
++
++ /* DAT0, maybe DAT1..DAT3 */
++ at91_set_B_periph(AT91_PIN_PA0, 1);
++ if (data->wire4) {
++ at91_set_B_periph(AT91_PIN_PA5, 1);
++ at91_set_B_periph(AT91_PIN_PA4, 1);
++ at91_set_B_periph(AT91_PIN_PA3, 1);
++ }
++ } else {
++ /* CMD */
++ at91_set_A_periph(AT91_PIN_PA7, 1);
++
++ /* DAT0, maybe DAT1..DAT3 */
++ at91_set_A_periph(AT91_PIN_PA6, 1);
++ if (data->wire4) {
++ at91_set_A_periph(AT91_PIN_PA9, 1);
++ at91_set_A_periph(AT91_PIN_PA10, 1);
++ at91_set_A_periph(AT91_PIN_PA11, 1);
++ }
++ }
++
++ mmc_data = *data;
++ platform_device_register(&at91sam9260_mmc_device);
++}
++#else
++void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * NAND / SmartMedia
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
++static struct at91_nand_data nand_data;
++
++#define NAND_BASE AT91_CHIPSELECT_3
++
++static struct resource nand_resources[] = {
++ {
++ .start = NAND_BASE,
++ .end = NAND_BASE + SZ_8M - 1,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct platform_device at91sam9260_nand_device = {
++ .name = "at91_nand",
++ .id = -1,
++ .dev = {
++ .platform_data = &nand_data,
++ },
++ .resource = nand_resources,
++ .num_resources = ARRAY_SIZE(nand_resources),
++};
++
++void __init at91_add_device_nand(struct at91_nand_data *data)
++{
++ unsigned long csa, mode;
++
++ if (!data)
++ return;
++
++ csa = at91_sys_read(AT91_MATRIX_EBICSA);
++ at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
++
++ /* set the bus interface characteristics */
++ at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
++ | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
++
++ at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
++ | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
++
++ at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
++
++ if (data->bus_width_16)
++ mode = AT91_SMC_DBW_16;
++ else
++ mode = AT91_SMC_DBW_8;
++ at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
++
++ /* enable pin */
++ if (data->enable_pin)
++ at91_set_gpio_output(data->enable_pin, 1);
++
++ /* ready/busy pin */
++ if (data->rdy_pin)
++ at91_set_gpio_input(data->rdy_pin, 1);
++
++ /* card detect pin */
++ if (data->det_pin)
++ at91_set_gpio_input(data->det_pin, 1);
++
++ nand_data = *data;
++ platform_device_register(&at91sam9260_nand_device);
++}
++#else
++void __init at91_add_device_nand(struct at91_nand_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * TWI (i2c)
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
++
++static struct resource twi_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_TWI,
++ .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_TWI,
++ .end = AT91SAM9260_ID_TWI,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9260_twi_device = {
++ .name = "at91_i2c",
++ .id = -1,
++ .resource = twi_resources,
++ .num_resources = ARRAY_SIZE(twi_resources),
++};
++
++void __init at91_add_device_i2c(void)
++{
++ /* pins used for TWI interface */
++ at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
++ at91_set_multi_drive(AT91_PIN_PA23, 1);
++
++ at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
++ at91_set_multi_drive(AT91_PIN_PA24, 1);
++
++ platform_device_register(&at91sam9260_twi_device);
++}
++#else
++void __init at91_add_device_i2c(void) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * SPI
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
++static u64 spi_dmamask = 0xffffffffUL;
++
++static struct resource spi0_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_SPI0,
++ .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_SPI0,
++ .end = AT91SAM9260_ID_SPI0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9260_spi0_device = {
++ .name = "atmel_spi",
++ .id = 0,
++ .dev = {
++ .dma_mask = &spi_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = spi0_resources,
++ .num_resources = ARRAY_SIZE(spi0_resources),
++};
++
++static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
++
++static struct resource spi1_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_SPI1,
++ .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_SPI1,
++ .end = AT91SAM9260_ID_SPI1,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9260_spi1_device = {
++ .name = "atmel_spi",
++ .id = 1,
++ .dev = {
++ .dma_mask = &spi_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = spi1_resources,
++ .num_resources = ARRAY_SIZE(spi1_resources),
++};
++
++static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
++
++void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
++{
++ int i;
++ unsigned long cs_pin;
++ short enable_spi0 = 0;
++ short enable_spi1 = 0;
++
++ /* Choose SPI chip-selects */
++ for (i = 0; i < nr_devices; i++) {
++ if (devices[i].controller_data)
++ cs_pin = (unsigned long) devices[i].controller_data;
++ else if (devices[i].bus_num == 0)
++ cs_pin = spi0_standard_cs[devices[i].chip_select];
++ else
++ cs_pin = spi1_standard_cs[devices[i].chip_select];
++
++ if (devices[i].bus_num == 0)
++ enable_spi0 = 1;
++ else
++ enable_spi1 = 1;
++
++ /* enable chip-select pin */
++ at91_set_gpio_output(cs_pin, 1);
++
++ /* pass chip-select pin to driver */
++ devices[i].controller_data = (void *) cs_pin;
++ }
++
++ spi_register_board_info(devices, nr_devices);
++
++ /* Configure SPI bus(es) */
++ if (enable_spi0) {
++ at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
++ at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
++ at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
++
++ at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
++ platform_device_register(&at91sam9260_spi0_device);
++ }
++ if (enable_spi1) {
++ at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
++ at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
++ at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
++
++ at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
++ platform_device_register(&at91sam9260_spi1_device);
++ }
++}
++#else
++void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * LEDs
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_LEDS)
++u8 at91_leds_cpu;
++u8 at91_leds_timer;
++
++void __init at91_init_leds(u8 cpu_led, u8 timer_led)
++{
++ at91_leds_cpu = cpu_led;
++ at91_leds_timer = timer_led;
++}
++#else
++void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
++#endif
++
++
++#if defined(CONFIG_NEW_LEDS)
++
++static struct platform_device at91_leds = {
++ .name = "at91_leds",
++ .id = -1,
++};
++
++void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
++{
++ if (!nr)
++ return;
++
++ at91_leds.dev.platform_data = leds;
++
++ for ( ; nr; nr--, leds++) {
++ leds->index = nr; /* first record stores number of leds */
++ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
++ }
++
++ platform_device_register(&at91_leds);
++}
++#else
++void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * UART
++ * -------------------------------------------------------------------- */
++#if defined(CONFIG_SERIAL_ATMEL)
++static struct resource dbgu_resources[] = {
++ [0] = {
++ .start = AT91_VA_BASE_SYS + AT91_DBGU,
++ .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91_ID_SYS,
++ .end = AT91_ID_SYS,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data dbgu_data = {
++ .use_dma_tx = 0,
++ .use_dma_rx = 0, /* DBGU not capable of receive DMA */
++ .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
++};
++
++static struct platform_device at91sam9260_dbgu_device = {
++ .name = "atmel_usart",
++ .id = 0,
++ .dev = {
++ .platform_data = &dbgu_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = dbgu_resources,
++ .num_resources = ARRAY_SIZE(dbgu_resources),
++};
++
++static inline void configure_dbgu_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
++ at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
++}
++
++static struct resource uart0_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_US0,
++ .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_US0,
++ .end = AT91SAM9260_ID_US0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart0_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91sam9260_uart0_device = {
++ .name = "atmel_usart",
++ .id = 1,
++ .dev = {
++ .platform_data = &uart0_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart0_resources,
++ .num_resources = ARRAY_SIZE(uart0_resources),
++};
++
++static inline void configure_usart0_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
++ at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
++ at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
++ at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
++ at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
++ at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
++ at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
++ at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
++}
++
++static struct resource uart1_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_US1,
++ .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_US1,
++ .end = AT91SAM9260_ID_US1,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart1_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91sam9260_uart1_device = {
++ .name = "atmel_usart",
++ .id = 2,
++ .dev = {
++ .platform_data = &uart1_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart1_resources,
++ .num_resources = ARRAY_SIZE(uart1_resources),
++};
++
++static inline void configure_usart1_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
++ at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
++ at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
++ at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
++}
++
++static struct resource uart2_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_US2,
++ .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_US2,
++ .end = AT91SAM9260_ID_US2,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart2_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91sam9260_uart2_device = {
++ .name = "atmel_usart",
++ .id = 3,
++ .dev = {
++ .platform_data = &uart2_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart2_resources,
++ .num_resources = ARRAY_SIZE(uart2_resources),
++};
++
++static inline void configure_usart2_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
++ at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
++}
++
++static struct resource uart3_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_US3,
++ .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_US3,
++ .end = AT91SAM9260_ID_US3,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart3_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91sam9260_uart3_device = {
++ .name = "atmel_usart",
++ .id = 4,
++ .dev = {
++ .platform_data = &uart3_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart3_resources,
++ .num_resources = ARRAY_SIZE(uart3_resources),
++};
++
++static inline void configure_usart3_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
++ at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
++}
++
++static struct resource uart4_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_US4,
++ .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_US4,
++ .end = AT91SAM9260_ID_US4,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart4_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91sam9260_uart4_device = {
++ .name = "atmel_usart",
++ .id = 5,
++ .dev = {
++ .platform_data = &uart4_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart4_resources,
++ .num_resources = ARRAY_SIZE(uart4_resources),
++};
++
++static inline void configure_usart4_pins(void)
++{
++ at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
++ at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
++}
++
++static struct resource uart5_resources[] = {
++ [0] = {
++ .start = AT91SAM9260_BASE_US5,
++ .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9260_ID_US5,
++ .end = AT91SAM9260_ID_US5,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart5_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91sam9260_uart5_device = {
++ .name = "atmel_usart",
++ .id = 6,
++ .dev = {
++ .platform_data = &uart5_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart5_resources,
++ .num_resources = ARRAY_SIZE(uart5_resources),
++};
++
++static inline void configure_usart5_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
++ at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
++}
++
++struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
++struct platform_device *atmel_default_console_device; /* the serial console device */
++
++void __init at91_init_serial(struct at91_uart_config *config)
++{
++ int i;
++
++ /* Fill in list of supported UARTs */
++ for (i = 0; i < config->nr_tty; i++) {
++ switch (config->tty_map[i]) {
++ case 0:
++ configure_usart0_pins();
++ at91_uarts[i] = &at91sam9260_uart0_device;
++ at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
++ break;
++ case 1:
++ configure_usart1_pins();
++ at91_uarts[i] = &at91sam9260_uart1_device;
++ at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
++ break;
++ case 2:
++ configure_usart2_pins();
++ at91_uarts[i] = &at91sam9260_uart2_device;
++ at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
++ break;
++ case 3:
++ configure_usart3_pins();
++ at91_uarts[i] = &at91sam9260_uart3_device;
++ at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
++ break;
++ case 4:
++ configure_usart4_pins();
++ at91_uarts[i] = &at91sam9260_uart4_device;
++ at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
++ break;
++ case 5:
++ configure_usart5_pins();
++ at91_uarts[i] = &at91sam9260_uart5_device;
++ at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
++ break;
++ case 6:
++ configure_dbgu_pins();
++ at91_uarts[i] = &at91sam9260_dbgu_device;
++ at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
++ break;
++ default:
++ continue;
++ }
++ at91_uarts[i]->id = i; /* update ID number to mapped ID */
++ }
++
++ /* Set serial console device */
++ if (config->console_tty < ATMEL_MAX_UART)
++ atmel_default_console_device = at91_uarts[config->console_tty];
++ if (!atmel_default_console_device)
++ printk(KERN_INFO "AT91: No default serial console defined.\n");
++}
++
++void __init at91_add_device_serial(void)
++{
++ int i;
++
++ for (i = 0; i < ATMEL_MAX_UART; i++) {
++ if (at91_uarts[i])
++ platform_device_register(at91_uarts[i]);
++ }
++}
++#else
++void __init at91_init_serial(struct at91_uart_config *config) {}
++void __init at91_add_device_serial(void) {}
++#endif
++
++
++/* -------------------------------------------------------------------- */
++/*
++ * These devices are always present and don't need any board-specific
++ * setup.
++ */
++static int __init at91_add_standard_devices(void)
++{
++ return 0;
++}
++
++arch_initcall(at91_add_standard_devices);
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9261.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9261.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9261.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9261.c Thu Nov 23 15:41:39 2006
+@@ -0,0 +1,289 @@
++/*
++ * arch/arm/mach-at91rm9200/at91sam9261.c
++ *
++ * Copyright (C) 2005 SAN People
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/module.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/arch/at91sam9261.h>
++#include <asm/arch/at91_pmc.h>
++
++#include "generic.h"
++#include "clock.h"
++
++static struct map_desc at91sam9261_io_desc[] __initdata = {
++ {
++ .virtual = AT91_VA_BASE_SYS,
++ .pfn = __phys_to_pfn(AT91_BASE_SYS),
++ .length = SZ_16K,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
++ .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
++ .length = AT91SAM9261_SRAM_SIZE,
++ .type = MT_DEVICE,
++ },
++};
++
++/* --------------------------------------------------------------------
++ * Clocks
++ * -------------------------------------------------------------------- */
++
++/*
++ * The peripheral clocks.
++ */
++static struct clk pioA_clk = {
++ .name = "pioA_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk pioB_clk = {
++ .name = "pioB_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk pioC_clk = {
++ .name = "pioC_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart0_clk = {
++ .name = "usart0_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_US0,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart1_clk = {
++ .name = "usart1_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_US1,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk usart2_clk = {
++ .name = "usart2_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_US2,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk mmc_clk = {
++ .name = "mci_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_MCI,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk udc_clk = {
++ .name = "udc_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_UDP,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk twi_clk = {
++ .name = "twi_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_TWI,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk spi0_clk = {
++ .name = "spi0_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk spi1_clk = {
++ .name = "spi1_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk ohci_clk = {
++ .name = "ohci_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_UHP,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++static struct clk lcdc_clk = {
++ .name = "lcdc_clk",
++ .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
++ .type = CLK_TYPE_PERIPHERAL,
++};
++
++static struct clk *periph_clocks[] __initdata = {
++ &pioA_clk,
++ &pioB_clk,
++ &pioC_clk,
++ &usart0_clk,
++ &usart1_clk,
++ &usart2_clk,
++ &mmc_clk,
++ &udc_clk,
++ &twi_clk,
++ &spi0_clk,
++ &spi1_clk,
++ // ssc 0 .. ssc2
++ // tc0 .. tc2
++ &ohci_clk,
++ &lcdc_clk,
++ // irq0 .. irq2
++};
++
++/*
++ * The four programmable clocks.
++ * You must configure pin multiplexing to bring these signals out.
++ */
++static struct clk pck0 = {
++ .name = "pck0",
++ .pmc_mask = AT91_PMC_PCK0,
++ .type = CLK_TYPE_PROGRAMMABLE,
++ .id = 0,
++};
++static struct clk pck1 = {
++ .name = "pck1",
++ .pmc_mask = AT91_PMC_PCK1,
++ .type = CLK_TYPE_PROGRAMMABLE,
++ .id = 1,
++};
++static struct clk pck2 = {
++ .name = "pck2",
++ .pmc_mask = AT91_PMC_PCK2,
++ .type = CLK_TYPE_PROGRAMMABLE,
++ .id = 2,
++};
++static struct clk pck3 = {
++ .name = "pck3",
++ .pmc_mask = AT91_PMC_PCK3,
++ .type = CLK_TYPE_PROGRAMMABLE,
++ .id = 3,
++};
++
++/* HClocks */
++static struct clk hck0 = {
++ .name = "hck0",
++ .pmc_mask = AT91_PMC_HCK0,
++ .type = CLK_TYPE_SYSTEM,
++ .id = 0,
++};
++static struct clk hck1 = {
++ .name = "hck1",
++ .pmc_mask = AT91_PMC_HCK1,
++ .type = CLK_TYPE_SYSTEM,
++ .id = 1,
++};
++
++static void __init at91sam9261_register_clocks(void)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
++ clk_register(periph_clocks[i]);
++
++ clk_register(&pck0);
++ clk_register(&pck1);
++ clk_register(&pck2);
++ clk_register(&pck3);
++
++ clk_register(&hck0);
++ clk_register(&hck1);
++}
++
++/* --------------------------------------------------------------------
++ * GPIO
++ * -------------------------------------------------------------------- */
++
++static struct at91_gpio_bank at91sam9261_gpio[] = {
++ {
++ .id = AT91SAM9261_ID_PIOA,
++ .offset = AT91_PIOA,
++ .clock = &pioA_clk,
++ }, {
++ .id = AT91SAM9261_ID_PIOB,
++ .offset = AT91_PIOB,
++ .clock = &pioB_clk,
++ }, {
++ .id = AT91SAM9261_ID_PIOC,
++ .offset = AT91_PIOC,
++ .clock = &pioC_clk,
++ }
++};
++
++static void at91sam9261_reset(void)
++{
++#warning "Implement CPU reset"
++}
++
++
++/* --------------------------------------------------------------------
++ * AT91SAM9261 processor initialization
++ * -------------------------------------------------------------------- */
++
++void __init at91sam9261_initialize(unsigned long main_clock)
++{
++ /* Map peripherals */
++ iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
++
++ at91_arch_reset = at91sam9261_reset;
++ at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
++ | (1 << AT91SAM9261_ID_IRQ2);
++
++ /* Init clock subsystem */
++ at91_clock_init(main_clock);
++
++ /* Register the processor-specific clocks */
++ at91sam9261_register_clocks();
++
++ /* Register GPIO subsystem */
++ at91_gpio_init(at91sam9261_gpio, 3);
++}
++
++/* --------------------------------------------------------------------
++ * Interrupt initialization
++ * -------------------------------------------------------------------- */
++
++/*
++ * The default interrupt priority levels (0 = lowest, 7 = highest).
++ */
++static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
++ 7, /* Advanced Interrupt Controller */
++ 7, /* System Peripherals */
++ 0, /* Parallel IO Controller A */
++ 0, /* Parallel IO Controller B */
++ 0, /* Parallel IO Controller C */
++ 0,
++ 6, /* USART 0 */
++ 6, /* USART 1 */
++ 6, /* USART 2 */
++ 0, /* Multimedia Card Interface */
++ 4, /* USB Device Port */
++ 0, /* Two-Wire Interface */
++ 6, /* Serial Peripheral Interface 0 */
++ 6, /* Serial Peripheral Interface 1 */
++ 5, /* Serial Synchronous Controller 0 */
++ 5, /* Serial Synchronous Controller 1 */
++ 5, /* Serial Synchronous Controller 2 */
++ 0, /* Timer Counter 0 */
++ 0, /* Timer Counter 1 */
++ 0, /* Timer Counter 2 */
++ 3, /* USB Host port */
++ 3, /* LCD Controller */
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0, /* Advanced Interrupt Controller */
++ 0, /* Advanced Interrupt Controller */
++ 0, /* Advanced Interrupt Controller */
++};
++
++void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
++{
++ if (!priority)
++ priority = at91sam9261_default_irq_priority;
++
++ /* Initialize the AIC interrupt controller */
++ at91_aic_init(priority);
++
++ /* Enable GPIO interrupts */
++ at91_gpio_irq_setup();
++}
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9261_devices.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9261_devices.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam9261_devices.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam9261_devices.c Sat Nov 25 11:14:00 2006
+@@ -0,0 +1,767 @@
++/*
++ * arch/arm/mach-at91rm9200/at91sam9261_devices.c
++ *
++ * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
++ * Copyright (C) 2005 David Brownell
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++
++#include <linux/platform_device.h>
++
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91sam9261.h>
++#include <asm/arch/at91sam9261_matrix.h>
++#include <asm/arch/at91sam926x_mc.h>
++
++#include "generic.h"
++
++#define SZ_512 0x00000200
++#define SZ_256 0x00000100
++#define SZ_16 0x00000010
++
++/* --------------------------------------------------------------------
++ * USB Host
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
++static u64 ohci_dmamask = 0xffffffffUL;
++static struct at91_usbh_data usbh_data;
++
++static struct resource usbh_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_UHP_BASE,
++ .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_UHP,
++ .end = AT91SAM9261_ID_UHP,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9261_usbh_device = {
++ .name = "at91_ohci",
++ .id = -1,
++ .dev = {
++ .dma_mask = &ohci_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = &usbh_data,
++ },
++ .resource = usbh_resources,
++ .num_resources = ARRAY_SIZE(usbh_resources),
++};
++
++void __init at91_add_device_usbh(struct at91_usbh_data *data)
++{
++ if (!data)
++ return;
++
++ usbh_data = *data;
++ platform_device_register(&at91sam9261_usbh_device);
++}
++#else
++void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * USB Device (Gadget)
++ * -------------------------------------------------------------------- */
++
++#ifdef CONFIG_USB_GADGET_AT91
++static struct at91_udc_data udc_data;
++
++static struct resource udc_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_BASE_UDP,
++ .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_UDP,
++ .end = AT91SAM9261_ID_UDP,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9261_udc_device = {
++ .name = "at91_udc",
++ .id = -1,
++ .dev = {
++ .platform_data = &udc_data,
++ },
++ .resource = udc_resources,
++ .num_resources = ARRAY_SIZE(udc_resources),
++};
++
++void __init at91_add_device_udc(struct at91_udc_data *data)
++{
++ unsigned long x;
++
++ if (!data)
++ return;
++
++ if (data->vbus_pin) {
++ at91_set_gpio_input(data->vbus_pin, 0);
++ at91_set_deglitch(data->vbus_pin, 1);
++ }
++
++ /* Pullup pin is handled internally */
++ x = at91_sys_read(AT91_MATRIX_USBPUCR);
++ at91_sys_write(AT91_MATRIX_USBPUCR, x | AT91_MATRIX_USBPUCR_PUON);
++
++ udc_data = *data;
++ platform_device_register(&at91sam9261_udc_device);
++}
++#else
++void __init at91_add_device_udc(struct at91_udc_data *data) {}
++#endif
++
++/* --------------------------------------------------------------------
++ * MMC / SD
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
++static u64 mmc_dmamask = 0xffffffffUL;
++static struct at91_mmc_data mmc_data;
++
++static struct resource mmc_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_BASE_MCI,
++ .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_MCI,
++ .end = AT91SAM9261_ID_MCI,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9261_mmc_device = {
++ .name = "at91_mci",
++ .id = -1,
++ .dev = {
++ .dma_mask = &mmc_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = &mmc_data,
++ },
++ .resource = mmc_resources,
++ .num_resources = ARRAY_SIZE(mmc_resources),
++};
++
++void __init at91_add_device_mmc(struct at91_mmc_data *data)
++{
++ if (!data)
++ return;
++
++ /* input/irq */
++ if (data->det_pin) {
++ at91_set_gpio_input(data->det_pin, 1);
++ at91_set_deglitch(data->det_pin, 1);
++ }
++ if (data->wp_pin)
++ at91_set_gpio_input(data->wp_pin, 1);
++ if (data->vcc_pin)
++ at91_set_gpio_output(data->vcc_pin, 0);
++
++ /* CLK */
++ at91_set_B_periph(AT91_PIN_PA2, 0);
++
++ /* CMD */
++ at91_set_B_periph(AT91_PIN_PA1, 1);
++
++ /* DAT0, maybe DAT1..DAT3 */
++ at91_set_B_periph(AT91_PIN_PA0, 1);
++ if (data->wire4) {
++ at91_set_B_periph(AT91_PIN_PA4, 1);
++ at91_set_B_periph(AT91_PIN_PA5, 1);
++ at91_set_B_periph(AT91_PIN_PA6, 1);
++ }
++
++ mmc_data = *data;
++ platform_device_register(&at91sam9261_mmc_device);
++}
++#else
++void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * NAND / SmartMedia
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
++static struct at91_nand_data nand_data;
++
++#define NAND_BASE AT91_CHIPSELECT_3
++
++static struct resource nand_resources[] = {
++ {
++ .start = NAND_BASE,
++ .end = NAND_BASE + SZ_256M - 1,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct platform_device at91_nand_device = {
++ .name = "at91_nand",
++ .id = -1,
++ .dev = {
++ .platform_data = &nand_data,
++ },
++ .resource = nand_resources,
++ .num_resources = ARRAY_SIZE(nand_resources),
++};
++
++void __init at91_add_device_nand(struct at91_nand_data *data)
++{
++ unsigned long csa, mode;
++
++ if (!data)
++ return;
++
++ csa = at91_sys_read(AT91_MATRIX_EBICSA);
++ at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
++
++ /* set the bus interface characteristics */
++ at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
++ | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
++
++ at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
++ | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
++
++ at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
++
++ if (data->bus_width_16)
++ mode = AT91_SMC_DBW_16;
++ else
++ mode = AT91_SMC_DBW_8;
++ at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
++
++ /* enable pin */
++ if (data->enable_pin)
++ at91_set_gpio_output(data->enable_pin, 1);
++
++ /* ready/busy pin */
++ if (data->rdy_pin)
++ at91_set_gpio_input(data->rdy_pin, 1);
++
++ /* card detect pin */
++ if (data->det_pin)
++ at91_set_gpio_input(data->det_pin, 1);
++
++ at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
++ at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
++
++ nand_data = *data;
++ platform_device_register(&at91_nand_device);
++}
++
++#else
++void __init at91_add_device_nand(struct at91_nand_data *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * TWI (i2c)
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
++
++static struct resource twi_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_BASE_TWI,
++ .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_TWI,
++ .end = AT91SAM9261_ID_TWI,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9261_twi_device = {
++ .name = "at91_i2c",
++ .id = -1,
++ .resource = twi_resources,
++ .num_resources = ARRAY_SIZE(twi_resources),
++};
++
++void __init at91_add_device_i2c(void)
++{
++ /* pins used for TWI interface */
++ at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
++ at91_set_multi_drive(AT91_PIN_PA7, 1);
++
++ at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
++ at91_set_multi_drive(AT91_PIN_PA8, 1);
++
++ platform_device_register(&at91sam9261_twi_device);
++}
++#else
++void __init at91_add_device_i2c(void) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * SPI
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
++static u64 spi_dmamask = 0xffffffffUL;
++
++static struct resource spi0_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_BASE_SPI0,
++ .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_SPI0,
++ .end = AT91SAM9261_ID_SPI0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9261_spi0_device = {
++ .name = "atmel_spi",
++ .id = 0,
++ .dev = {
++ .dma_mask = &spi_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = spi0_resources,
++ .num_resources = ARRAY_SIZE(spi0_resources),
++};
++
++static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
++
++static struct resource spi1_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_BASE_SPI1,
++ .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_SPI1,
++ .end = AT91SAM9261_ID_SPI1,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device at91sam9261_spi1_device = {
++ .name = "atmel_spi",
++ .id = 1,
++ .dev = {
++ .dma_mask = &spi_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = spi1_resources,
++ .num_resources = ARRAY_SIZE(spi1_resources),
++};
++
++static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
++
++void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
++{
++ int i;
++ unsigned long cs_pin;
++ short enable_spi0 = 0;
++ short enable_spi1 = 0;
++
++ /* Choose SPI chip-selects */
++ for (i = 0; i < nr_devices; i++) {
++ if (devices[i].controller_data)
++ cs_pin = (unsigned long) devices[i].controller_data;
++ else if (devices[i].bus_num == 0)
++ cs_pin = spi0_standard_cs[devices[i].chip_select];
++ else
++ cs_pin = spi1_standard_cs[devices[i].chip_select];
++
++ if (devices[i].bus_num == 0)
++ enable_spi0 = 1;
++ else
++ enable_spi1 = 1;
++
++ /* enable chip-select pin */
++ at91_set_gpio_output(cs_pin, 1);
++
++ /* pass chip-select pin to driver */
++ devices[i].controller_data = (void *) cs_pin;
++ }
++
++ spi_register_board_info(devices, nr_devices);
++
++ /* Configure SPI bus(es) */
++ if (enable_spi0) {
++ at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
++ at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
++ at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
++
++ at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk");
++ platform_device_register(&at91sam9261_spi0_device);
++ }
++ if (enable_spi1) {
++ at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
++ at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
++ at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
++
++ at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk");
++ platform_device_register(&at91sam9261_spi1_device);
++ }
++}
++#else
++void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * LCD Controller
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE)
++static u64 lcdc_dmamask = 0xffffffffUL;
++static struct at91fb_info lcdc_data;
++
++static struct resource lcdc_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_LCDC_BASE,
++ .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_LCDC,
++ .end = AT91SAM9261_ID_LCDC,
++ .flags = IORESOURCE_IRQ,
++ },
++#if defined(CONFIG_FB_INTSRAM)
++ [2] = {
++ .start = AT91SAM9261_SRAM_BASE,
++ .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++ },
++#endif
++};
++
++static struct platform_device at91_lcdc_device = {
++ .name = "at91-fb",
++ .id = 0,
++ .dev = {
++ .dma_mask = &lcdc_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = &lcdc_data,
++ },
++ .resource = lcdc_resources,
++ .num_resources = ARRAY_SIZE(lcdc_resources),
++};
++
++void __init at91_add_device_lcdc(struct at91fb_info *data)
++{
++ if (!data) {
++ return;
++ }
++
++ at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
++ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
++ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
++ at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
++ at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
++ at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
++ at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
++ at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
++ at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
++ at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
++ at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
++ at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
++ at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
++ at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
++ at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
++ at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
++ at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
++ at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
++ at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
++ at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
++ at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
++ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
++
++ lcdc_data = *data;
++ platform_device_register(&at91_lcdc_device);
++}
++#else
++void __init at91_add_device_lcdc(struct at91fb_info *data) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * LEDs
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_LEDS)
++u8 at91_leds_cpu;
++u8 at91_leds_timer;
++
++void __init at91_init_leds(u8 cpu_led, u8 timer_led)
++{
++ at91_leds_cpu = cpu_led;
++ at91_leds_timer = timer_led;
++}
++#else
++void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
++#endif
++
++
++#if defined(CONFIG_NEW_LEDS)
++
++static struct platform_device at91_leds = {
++ .name = "at91_leds",
++ .id = -1,
++};
++
++void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
++{
++ if (!nr)
++ return;
++
++ at91_leds.dev.platform_data = leds;
++
++ for ( ; nr; nr--, leds++) {
++ leds->index = nr; /* first record stores number of leds */
++ at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
++ }
++
++ platform_device_register(&at91_leds);
++}
++#else
++void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
++#endif
++
++
++/* --------------------------------------------------------------------
++ * UART
++ * -------------------------------------------------------------------- */
++
++#if defined(CONFIG_SERIAL_ATMEL)
++static struct resource dbgu_resources[] = {
++ [0] = {
++ .start = AT91_VA_BASE_SYS + AT91_DBGU,
++ .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91_ID_SYS,
++ .end = AT91_ID_SYS,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data dbgu_data = {
++ .use_dma_tx = 0,
++ .use_dma_rx = 0, /* DBGU not capable of receive DMA */
++ .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
++};
++
++static struct platform_device at91sam9261_dbgu_device = {
++ .name = "atmel_usart",
++ .id = 0,
++ .dev = {
++ .platform_data = &dbgu_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = dbgu_resources,
++ .num_resources = ARRAY_SIZE(dbgu_resources),
++};
++
++static inline void configure_dbgu_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
++ at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
++}
++
++static struct resource uart0_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_BASE_US0,
++ .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_US0,
++ .end = AT91SAM9261_ID_US0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart0_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91sam9261_uart0_device = {
++ .name = "atmel_usart",
++ .id = 1,
++ .dev = {
++ .platform_data = &uart0_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart0_resources,
++ .num_resources = ARRAY_SIZE(uart0_resources),
++};
++
++static inline void configure_usart0_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
++ at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
++ at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
++ at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
++}
++
++static struct resource uart1_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_BASE_US1,
++ .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_US1,
++ .end = AT91SAM9261_ID_US1,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart1_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91sam9261_uart1_device = {
++ .name = "atmel_usart",
++ .id = 2,
++ .dev = {
++ .platform_data = &uart1_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart1_resources,
++ .num_resources = ARRAY_SIZE(uart1_resources),
++};
++
++static inline void configure_usart1_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
++ at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
++}
++
++static struct resource uart2_resources[] = {
++ [0] = {
++ .start = AT91SAM9261_BASE_US2,
++ .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = AT91SAM9261_ID_US2,
++ .end = AT91SAM9261_ID_US2,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct atmel_uart_data uart2_data = {
++ .use_dma_tx = 1,
++ .use_dma_rx = 1,
++};
++
++static struct platform_device at91sam9261_uart2_device = {
++ .name = "atmel_usart",
++ .id = 3,
++ .dev = {
++ .platform_data = &uart2_data,
++ .coherent_dma_mask = 0xffffffff,
++ },
++ .resource = uart2_resources,
++ .num_resources = ARRAY_SIZE(uart2_resources),
++};
++
++static inline void configure_usart2_pins(void)
++{
++ at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
++ at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
++}
++
++struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
++struct platform_device *atmel_default_console_device; /* the serial console device */
++
++void __init at91_init_serial(struct at91_uart_config *config)
++{
++ int i;
++
++ /* Fill in list of supported UARTs */
++ for (i = 0; i < config->nr_tty; i++) {
++ switch (config->tty_map[i]) {
++ case 0:
++ configure_usart0_pins();
++ at91_uarts[i] = &at91sam9261_uart0_device;
++ at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart");
++ break;
++ case 1:
++ configure_usart1_pins();
++ at91_uarts[i] = &at91sam9261_uart1_device;
++ at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart");
++ break;
++ case 2:
++ configure_usart2_pins();
++ at91_uarts[i] = &at91sam9261_uart2_device;
++ at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart");
++ break;
++ case 3:
++ configure_dbgu_pins();
++ at91_uarts[i] = &at91sam9261_dbgu_device;
++ at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart");
++ break;
++ default:
++ continue;
++ }
++ at91_uarts[i]->id = i; /* update ID number to mapped ID */
++ }
++
++ /* Set serial console device */
++ if (config->console_tty < ATMEL_MAX_UART)
++ atmel_default_console_device = at91_uarts[config->console_tty];
++ if (!atmel_default_console_device)
++ printk(KERN_INFO "AT91: No default serial console defined.\n");
++}
++
++void __init at91_add_device_serial(void)
++{
++ int i;
++
++ for (i = 0; i < ATMEL_MAX_UART; i++) {
++ if (at91_uarts[i])
++ platform_device_register(at91_uarts[i]);
++ }
++}
++#else
++void __init at91_init_serial(struct at91_uart_config *config) {}
++void __init at91_add_device_serial(void) {}
++#endif
++
++
++/* -------------------------------------------------------------------- */
++
++/*
++ * These devices are always present and don't need any board-specific
++ * setup.
++ */
++static int __init at91_add_standard_devices(void)
++{
++ return 0;
++}
++
++arch_initcall(at91_add_standard_devices);
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam926x_time.c linux-2.6.19/arch/arm/mach-at91rm9200/at91sam926x_time.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/at91sam926x_time.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/at91sam926x_time.c Mon Nov 20 10:52:16 2006
+@@ -0,0 +1,114 @@
++/*
++ * linux/arch/arm/mach-at91rm9200/at91sam926x_time.c
++ *
++ * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
++ * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/time.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/mach/time.h>
++
++#include <asm/arch/at91_pit.h>
++
++
++#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
++#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
++
++/*
++ * Returns number of microseconds since last timer interrupt. Note that interrupts
++ * will have been disabled by do_gettimeofday()
++ * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
++ * 'tick' is usecs per jiffy (linux/timex.h).
++ */
++static unsigned long at91sam926x_gettimeoffset(void)
++{
++ unsigned long elapsed;
++ unsigned long t = at91_sys_read(AT91_PIT_PIIR);
++
++ elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */
++
++ return (unsigned long)(elapsed * 1000000) / LATCH;
++}
++
++/*
++ * IRQ handler for the timer.
++ */
++static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
++{
++ volatile long nr_ticks;
++
++ if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */
++ write_seqlock(&xtime_lock);
++
++ /* Get number to ticks performed before interrupt and clear PIT interrupt */
++ nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
++ do {
++ timer_tick();
++ nr_ticks--;
++ } while (nr_ticks);
++
++ write_sequnlock(&xtime_lock);
++ return IRQ_HANDLED;
++ } else
++ return IRQ_NONE; /* not handled */
++}
++
++static struct irqaction at91sam926x_timer_irq = {
++ .name = "at91_tick",
++ .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER,
++ .handler = at91sam926x_timer_interrupt
++};
++
++void at91sam926x_timer_reset(void)
++{
++ /* Disable timer */
++ at91_sys_write(AT91_PIT_MR, 0);
++
++ /* Clear any pending interrupts */
++ (void) at91_sys_read(AT91_PIT_PIVR);
++
++ /* Set Period Interval timer and enable its interrupt */
++ at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
++}
++
++/*
++ * Set up timer interrupt.
++ */
++void __init at91sam926x_timer_init(void)
++{
++ /* Initialize and enable the timer */
++ at91sam926x_timer_reset();
++
++ /* Make IRQs happen for the system timer. */
++ setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
++}
++
++#ifdef CONFIG_PM
++static void at91sam926x_timer_suspend(void)
++{
++ /* Disable timer */
++ at91_sys_write(AT91_PIT_MR, 0);
++}
++#else
++#define at91sam926x_timer_suspend NULL
++#endif
++
++struct sys_timer at91sam926x_timer = {
++ .init = at91sam926x_timer_init,
++ .offset = at91sam926x_gettimeoffset,
++ .suspend = at91sam926x_timer_suspend,
++ .resume = at91sam926x_timer_reset,
++};
++
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-1arm.c linux-2.6.19/arch/arm/mach-at91rm9200/board-1arm.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-1arm.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-1arm.c Thu Nov 23 15:50:12 2006
+@@ -64,7 +64,7 @@
+ at91rm9200_init_interrupts(NULL);
+ }
+
+-static struct at91_eth_data __initdata onearm_eth_data = {
++static struct eth_platform_data __initdata onearm_eth_data = {
+ .phy_irq_pin = AT91_PIN_PC4,
+ .is_rmii = 1,
+ };
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-carmeva.c linux-2.6.19/arch/arm/mach-at91rm9200/board-carmeva.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-carmeva.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-carmeva.c Thu Nov 23 15:50:12 2006
+@@ -65,8 +65,7 @@
+ at91rm9200_init_interrupts(NULL);
+ }
+
+-
+-static struct at91_eth_data __initdata carmeva_eth_data = {
++static struct eth_platform_data __initdata carmeva_eth_data = {
+ .phy_irq_pin = AT91_PIN_PC4,
+ .is_rmii = 1,
+ };
+@@ -89,8 +88,33 @@
+ // };
+
+ static struct at91_mmc_data __initdata carmeva_mmc_data = {
+- .is_b = 0,
++ .slot_b = 0,
+ .wire4 = 1,
++ .det_pin = AT91_PIN_PB10,
++ .wp_pin = AT91_PIN_PC14,
++};
++
++static struct spi_board_info carmeva_spi_devices[] = {
++ { /* DataFlash chip */
++ .modalias = "mtd_dataflash",
++ .chip_select = 0,
++ .max_speed_hz = 10 * 1000 * 1000,
++ },
++ { /* User accessable spi - cs1 (250KHz) */
++ .modalias = "spi-cs1",
++ .chip_select = 1,
++ .max_speed_hz = 250 * 1000,
++ },
++ { /* User accessable spi - cs2 (1MHz) */
++ .modalias = "spi-cs2",
++ .chip_select = 2,
++ .max_speed_hz = 1 * 1000 * 1000,
++ },
++ { /* User accessable spi - cs3 (10MHz) */
++ .modalias = "spi-cs3",
++ .chip_select = 3,
++ .max_speed_hz = 10 * 1000 * 1000,
++ },
+ };
+
+ static void __init carmeva_board_init(void)
+@@ -105,10 +129,10 @@
+ at91_add_device_udc(&carmeva_udc_data);
+ /* I2C */
+ at91_add_device_i2c();
++ /* SPI */
++ at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices));
+ /* Compact Flash */
+ // at91_add_device_cf(&carmeva_cf_data);
+- /* SPI */
+-// at91_add_device_spi(NULL, 0);
+ /* MMC */
+ at91_add_device_mmc(&carmeva_mmc_data);
+ }
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-csb337.c linux-2.6.19/arch/arm/mach-at91rm9200/board-csb337.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-csb337.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-csb337.c Thu Nov 23 15:50:12 2006
+@@ -68,7 +68,7 @@
+ at91rm9200_init_interrupts(NULL);
+ }
+
+-static struct at91_eth_data __initdata csb337_eth_data = {
++static struct eth_platform_data __initdata csb337_eth_data = {
+ .phy_irq_pin = AT91_PIN_PC2,
+ .is_rmii = 0,
+ };
+@@ -99,7 +99,7 @@
+
+ static struct at91_mmc_data __initdata csb337_mmc_data = {
+ .det_pin = AT91_PIN_PD5,
+- .is_b = 0,
++ .slot_b = 0,
+ .wire4 = 1,
+ .wp_pin = AT91_PIN_PD6,
+ };
+@@ -112,6 +112,23 @@
+ },
+ };
+
++static struct at91_gpio_led csb337_leds[] = {
++ {
++ .name = "led0",
++ .gpio = AT91_PIN_PB0,
++ .trigger = "heartbeat",
++ },
++ {
++ .name = "led1",
++ .gpio = AT91_PIN_PB1,
++ .trigger = "timer",
++ },
++ {
++ .name = "led2",
++ .gpio = AT91_PIN_PB2,
++ }
++};
++
+ static void __init csb337_board_init(void)
+ {
+ /* Serial */
+@@ -131,6 +148,8 @@
+ at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
+ /* MMC */
+ at91_add_device_mmc(&csb337_mmc_data);
++ /* LEDS */
++ at91_gpio_leds(csb337_leds, ARRAY_SIZE(csb337_leds));
+ }
+
+ MACHINE_START(CSB337, "Cogent CSB337")
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-csb637.c linux-2.6.19/arch/arm/mach-at91rm9200/board-csb637.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-csb637.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-csb637.c Thu Nov 23 15:50:12 2006
+@@ -67,7 +67,7 @@
+ at91rm9200_init_interrupts(NULL);
+ }
+
+-static struct at91_eth_data __initdata csb637_eth_data = {
++static struct eth_platform_data __initdata csb637_eth_data = {
+ .phy_irq_pin = AT91_PIN_PC0,
+ .is_rmii = 0,
+ };
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-dk.c linux-2.6.19/arch/arm/mach-at91rm9200/board-dk.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-dk.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-dk.c Thu Nov 23 15:50:12 2006
+@@ -27,6 +27,7 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/spi/spi.h>
++#include <linux/mtd/physmap.h>
+
+ #include <asm/hardware.h>
+ #include <asm/setup.h>
+@@ -39,6 +40,7 @@
+
+ #include <asm/arch/board.h>
+ #include <asm/arch/gpio.h>
++#include <asm/arch/at91rm9200_mc.h>
+
+ #include "generic.h"
+
+@@ -71,7 +73,186 @@
+ at91rm9200_init_interrupts(NULL);
+ }
+
+-static struct at91_eth_data __initdata dk_eth_data = {
++#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
++#include <video/s1d13xxxfb.h>
++#include <asm/arch/ics1523.h>
++
++/* EPSON S1D13806 FB */
++#define AT91_FB_REG_BASE 0x30000000L
++#define AT91_FB_REG_SIZE 0x200
++#define AT91_FB_VMEM_BASE 0x30200000L
++#define AT91_FB_VMEM_SIZE 0x140000L
++
++static void __init dk_init_video(void)
++{
++ /* NWAIT Signal */
++ at91_set_A_periph(AT91_PIN_PC6, 0);
++
++ /* Initialization of the Static Memory Controller for Chip Select 2 */
++ at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
++ | AT91_SMC_WSEN | AT91_SMC_NWS_(4) /* wait states */
++ | AT91_SMC_TDF_(1) /* float time */
++ );
++
++ AT91F_ICS1523_clockinit();
++}
++
++/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz)
++ Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
++static const struct s1d13xxxfb_regval dk_s1dfb_initregs[] = {
++ {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */
++ {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */
++ {S1DREG_GPIO_CNF0, 0x00},
++ {S1DREG_GPIO_CNF1, 0x00},
++ {S1DREG_GPIO_CTL0, 0x08},
++ {S1DREG_GPIO_CTL1, 0x00},
++ {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/
++ {S1DREG_LCD_CLK_CNF, 0x00},
++ {S1DREG_CRT_CLK_CNF, 0x00},
++ {S1DREG_MPLUG_CLK_CNF, 0x00},
++ {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */
++ {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */
++ {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */
++ {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */
++ {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */
++ {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
++ {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */
++ {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */
++ {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */
++ {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */
++ {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */
++ {S1DREG_LCD_DISP_VHEIGHT0, 0xDF},
++ {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */
++ {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */
++ {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */
++ {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */
++ {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */
++ {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */
++ {S1DREG_LCD_DISP_START0, 0x00},
++ {S1DREG_LCD_DISP_START1, 0xC8},
++ {S1DREG_LCD_DISP_START2, 0x00},
++ {S1DREG_LCD_MEM_OFF0, 0x80},
++ {S1DREG_LCD_MEM_OFF1, 0x02},
++ {S1DREG_LCD_PIX_PAN, 0x00},
++ {S1DREG_LCD_DISP_FIFO_HTC, 0x3B},
++ {S1DREG_LCD_DISP_FIFO_LTC, 0x3C},
++ {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */
++ {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */
++ {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */
++ {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */
++ {S1DREG_CRT_DISP_VHEIGHT0, 0xDF},
++ {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */
++ {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */
++ {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */
++ {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */
++ {S1DREG_TV_OUT_CTL, 0x10},
++ {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */
++ {S1DREG_CRT_DISP_START0, 0x00},
++ {S1DREG_CRT_DISP_START1, 0x00},
++ {S1DREG_CRT_DISP_START2, 0x00},
++ {S1DREG_CRT_MEM_OFF0, 0x80},
++ {S1DREG_CRT_MEM_OFF1, 0x02},
++ {S1DREG_CRT_PIX_PAN, 0x00},
++ {S1DREG_CRT_DISP_FIFO_HTC, 0x3B},
++ {S1DREG_CRT_DISP_FIFO_LTC, 0x3C},
++ {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */
++ {S1DREG_LCD_CUR_START, 0x01},
++ {S1DREG_LCD_CUR_XPOS0, 0x00},
++ {S1DREG_LCD_CUR_XPOS1, 0x00},
++ {S1DREG_LCD_CUR_YPOS0, 0x00},
++ {S1DREG_LCD_CUR_YPOS1, 0x00},
++ {S1DREG_LCD_CUR_BCTL0, 0x00},
++ {S1DREG_LCD_CUR_GCTL0, 0x00},
++ {S1DREG_LCD_CUR_RCTL0, 0x00},
++ {S1DREG_LCD_CUR_BCTL1, 0x1F},
++ {S1DREG_LCD_CUR_GCTL1, 0x3F},
++ {S1DREG_LCD_CUR_RCTL1, 0x1F},
++ {S1DREG_LCD_CUR_FIFO_HTC, 0x00},
++ {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */
++ {S1DREG_CRT_CUR_START, 0x01},
++ {S1DREG_CRT_CUR_XPOS0, 0x00},
++ {S1DREG_CRT_CUR_XPOS1, 0x00},
++ {S1DREG_CRT_CUR_YPOS0, 0x00},
++ {S1DREG_CRT_CUR_YPOS1, 0x00},
++ {S1DREG_CRT_CUR_BCTL0, 0x00},
++ {S1DREG_CRT_CUR_GCTL0, 0x00},
++ {S1DREG_CRT_CUR_RCTL0, 0x00},
++ {S1DREG_CRT_CUR_BCTL1, 0x1F},
++ {S1DREG_CRT_CUR_GCTL1, 0x3F},
++ {S1DREG_CRT_CUR_RCTL1, 0x1F},
++ {S1DREG_CRT_CUR_FIFO_HTC, 0x00},
++ {S1DREG_BBLT_CTL0, 0x00},
++ {S1DREG_BBLT_CTL0, 0x00},
++ {S1DREG_BBLT_CC_EXP, 0x00},
++ {S1DREG_BBLT_OP, 0x00},
++ {S1DREG_BBLT_SRC_START0, 0x00},
++ {S1DREG_BBLT_SRC_START1, 0x00},
++ {S1DREG_BBLT_SRC_START2, 0x00},
++ {S1DREG_BBLT_DST_START0, 0x00},
++ {S1DREG_BBLT_DST_START1, 0x00},
++ {S1DREG_BBLT_DST_START2, 0x00},
++ {S1DREG_BBLT_MEM_OFF0, 0x00},
++ {S1DREG_BBLT_MEM_OFF1, 0x00},
++ {S1DREG_BBLT_WIDTH0, 0x00},
++ {S1DREG_BBLT_WIDTH1, 0x00},
++ {S1DREG_BBLT_HEIGHT0, 0x00},
++ {S1DREG_BBLT_HEIGHT1, 0x00},
++ {S1DREG_BBLT_BGC0, 0x00},
++ {S1DREG_BBLT_BGC1, 0x00},
++ {S1DREG_BBLT_FGC0, 0x00},
++ {S1DREG_BBLT_FGC1, 0x00},
++ {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */
++ {S1DREG_LKUP_ADDR, 0x00},
++ {S1DREG_PS_CNF, 0x00}, /* Power Save disable */
++ {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */
++ {S1DREG_CPU2MEM_WDOGT, 0x00},
++ {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */
++};
++
++static struct s1d13xxxfb_pdata dk_s1dfb_pdata = {
++ .initregs = dk_s1dfb_initregs,
++ .initregssize = ARRAY_SIZE(dk_s1dfb_initregs),
++ .platform_init_video = dk_init_video,
++};
++
++static u64 s1dfb_dmamask = 0xffffffffUL;
++
++static struct resource dk_s1dfb_resource[] = {
++ [0] = { /* video mem */
++ .name = "s1d13806 memory",
++ .start = AT91_FB_VMEM_BASE,
++ .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = { /* video registers */
++ .name = "s1d13806 registers",
++ .start = AT91_FB_REG_BASE,
++ .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device dk_s1dfb_device = {
++ .name = "s1d13806fb",
++ .id = -1,
++ .dev = {
++ .dma_mask = &s1dfb_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = &dk_s1dfb_pdata,
++ },
++ .resource = dk_s1dfb_resource,
++ .num_resources = ARRAY_SIZE(dk_s1dfb_resource),
++};
++
++static void __init dk_add_device_video(void)
++{
++ platform_device_register(&dk_s1dfb_device);
++}
++#else
++static void __init dk_add_device_video(void) {}
++#endif
++
++static struct eth_platform_data __initdata dk_eth_data = {
+ .phy_irq_pin = AT91_PIN_PC4,
+ .is_rmii = 1,
+ };
+@@ -93,7 +274,7 @@
+ };
+
+ static struct at91_mmc_data __initdata dk_mmc_data = {
+- .is_b = 0,
++ .slot_b = 0,
+ .wire4 = 1,
+ };
+
+@@ -145,6 +326,37 @@
+ .partition_info = nand_partitions,
+ };
+
++#define DK_FLASH_BASE AT91_CHIPSELECT_0
++#define DK_FLASH_SIZE 0x200000
++
++static struct physmap_flash_data dk_flash_data = {
++ .width = 2,
++};
++
++static struct resource dk_flash_resource = {
++ .start = DK_FLASH_BASE,
++ .end = DK_FLASH_BASE + DK_FLASH_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device dk_flash = {
++ .name = "physmap-flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &dk_flash_data,
++ },
++ .resource = &dk_flash_resource,
++ .num_resources = 1,
++};
++
++static struct at91_gpio_led dk_leds[] = {
++ {
++ .name = "led0",
++ .gpio = AT91_PIN_PB2,
++ .trigger = "timer",
++ }
++};
++
+ static void __init dk_board_init(void)
+ {
+ /* Serial */
+@@ -172,8 +384,12 @@
+ #endif
+ /* NAND */
+ at91_add_device_nand(&dk_nand_data);
++ /* NOR Flash */
++ platform_device_register(&dk_flash);
++ /* LEDs */
++ at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds));
+ /* VGA */
+-// dk_add_device_video();
++ dk_add_device_video();
+ }
+
+ MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-eb9200.c linux-2.6.19/arch/arm/mach-at91rm9200/board-eb9200.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-eb9200.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-eb9200.c Thu Nov 23 15:50:12 2006
+@@ -65,7 +65,7 @@
+ at91rm9200_init_interrupts(NULL);
+ }
+
+-static struct at91_eth_data __initdata eb9200_eth_data = {
++static struct eth_platform_data __initdata eb9200_eth_data = {
+ .phy_irq_pin = AT91_PIN_PC4,
+ .is_rmii = 1,
+ };
+@@ -87,7 +87,7 @@
+ };
+
+ static struct at91_mmc_data __initdata eb9200_mmc_data = {
+- .is_b = 0,
++ .slot_b = 0,
+ .wire4 = 1,
+ };
+
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-ek.c linux-2.6.19/arch/arm/mach-at91rm9200/board-ek.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-ek.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-ek.c Thu Nov 23 15:50:12 2006
+@@ -27,6 +27,7 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/spi/spi.h>
++#include <linux/mtd/physmap.h>
+
+ #include <asm/hardware.h>
+ #include <asm/setup.h>
+@@ -39,6 +40,7 @@
+
+ #include <asm/arch/board.h>
+ #include <asm/arch/gpio.h>
++#include <asm/arch/at91rm9200_mc.h>
+
+ #include "generic.h"
+
+@@ -71,7 +73,188 @@
+ at91rm9200_init_interrupts(NULL);
+ }
+
+-static struct at91_eth_data __initdata ek_eth_data = {
++#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
++#include <video/s1d13xxxfb.h>
++#include <asm/arch/ics1523.h>
++
++/* EPSON S1D13806 FB */
++#define AT91_FB_REG_BASE 0x40000000L
++#define AT91_FB_REG_SIZE 0x200
++#define AT91_FB_VMEM_BASE 0x40200000L
++#define AT91_FB_VMEM_SIZE 0x140000L
++
++static void __init ek_init_video(void)
++{
++ /* NWAIT Signal */
++ at91_set_A_periph(AT91_PIN_PC6, 0);
++
++ /* Initialization of the Static Memory Controller for Chip Select 3 */
++ at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16 /* 16 bit */
++ | AT91_SMC_WSEN | AT91_SMC_NWS_(5) /* wait states */
++ | AT91_SMC_TDF_(1) /* float time */
++ );
++
++ AT91F_ICS1523_clockinit();
++}
++
++/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz)
++ Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
++static const struct s1d13xxxfb_regval ek_s1dfb_initregs[] = {
++ {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */
++ {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */
++ {S1DREG_GPIO_CNF0, 0xFF}, // 0x00
++ {S1DREG_GPIO_CNF1, 0x1F}, // 0x08
++ {S1DREG_GPIO_CTL0, 0x00},
++ {S1DREG_GPIO_CTL1, 0x00},
++ {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/
++ {S1DREG_LCD_CLK_CNF, 0x00},
++ {S1DREG_CRT_CLK_CNF, 0x00},
++ {S1DREG_MPLUG_CLK_CNF, 0x00},
++ {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */
++ {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */
++ {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */
++ {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */
++ {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */
++ {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
++ {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */
++ {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */
++ {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */
++ {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */
++ {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */
++ {S1DREG_LCD_DISP_VHEIGHT0, 0xDF},
++ {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */
++ {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */
++ {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */
++ {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */
++ {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */
++ {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */
++ {S1DREG_LCD_DISP_START0, 0x00},
++ {S1DREG_LCD_DISP_START1, 0xC8},
++ {S1DREG_LCD_DISP_START2, 0x00},
++ {S1DREG_LCD_MEM_OFF0, 0x80},
++ {S1DREG_LCD_MEM_OFF1, 0x02},
++ {S1DREG_LCD_PIX_PAN, 0x00},
++ {S1DREG_LCD_DISP_FIFO_HTC, 0x3B},
++ {S1DREG_LCD_DISP_FIFO_LTC, 0x3C},
++ {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */
++ {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */
++ {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */
++ {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */
++ {S1DREG_CRT_DISP_VHEIGHT0, 0xDF},
++ {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */
++ {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */
++ {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */
++ {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */
++ {S1DREG_TV_OUT_CTL, 0x10},
++ {0x005E, 0x9F},
++ {0x005F, 0x00},
++ {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */
++ {S1DREG_CRT_DISP_START0, 0x00},
++ {S1DREG_CRT_DISP_START1, 0x00},
++ {S1DREG_CRT_DISP_START2, 0x00},
++ {S1DREG_CRT_MEM_OFF0, 0x80},
++ {S1DREG_CRT_MEM_OFF1, 0x02},
++ {S1DREG_CRT_PIX_PAN, 0x00},
++ {S1DREG_CRT_DISP_FIFO_HTC, 0x3B},
++ {S1DREG_CRT_DISP_FIFO_LTC, 0x3C},
++ {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */
++ {S1DREG_LCD_CUR_START, 0x01},
++ {S1DREG_LCD_CUR_XPOS0, 0x00},
++ {S1DREG_LCD_CUR_XPOS1, 0x00},
++ {S1DREG_LCD_CUR_YPOS0, 0x00},
++ {S1DREG_LCD_CUR_YPOS1, 0x00},
++ {S1DREG_LCD_CUR_BCTL0, 0x00},
++ {S1DREG_LCD_CUR_GCTL0, 0x00},
++ {S1DREG_LCD_CUR_RCTL0, 0x00},
++ {S1DREG_LCD_CUR_BCTL1, 0x1F},
++ {S1DREG_LCD_CUR_GCTL1, 0x3F},
++ {S1DREG_LCD_CUR_RCTL1, 0x1F},
++ {S1DREG_LCD_CUR_FIFO_HTC, 0x00},
++ {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */
++ {S1DREG_CRT_CUR_START, 0x01},
++ {S1DREG_CRT_CUR_XPOS0, 0x00},
++ {S1DREG_CRT_CUR_XPOS1, 0x00},
++ {S1DREG_CRT_CUR_YPOS0, 0x00},
++ {S1DREG_CRT_CUR_YPOS1, 0x00},
++ {S1DREG_CRT_CUR_BCTL0, 0x00},
++ {S1DREG_CRT_CUR_GCTL0, 0x00},
++ {S1DREG_CRT_CUR_RCTL0, 0x00},
++ {S1DREG_CRT_CUR_BCTL1, 0x1F},
++ {S1DREG_CRT_CUR_GCTL1, 0x3F},
++ {S1DREG_CRT_CUR_RCTL1, 0x1F},
++ {S1DREG_CRT_CUR_FIFO_HTC, 0x00},
++ {S1DREG_BBLT_CTL0, 0x00},
++ {S1DREG_BBLT_CTL0, 0x00},
++ {S1DREG_BBLT_CC_EXP, 0x00},
++ {S1DREG_BBLT_OP, 0x00},
++ {S1DREG_BBLT_SRC_START0, 0x00},
++ {S1DREG_BBLT_SRC_START1, 0x00},
++ {S1DREG_BBLT_SRC_START2, 0x00},
++ {S1DREG_BBLT_DST_START0, 0x00},
++ {S1DREG_BBLT_DST_START1, 0x00},
++ {S1DREG_BBLT_DST_START2, 0x00},
++ {S1DREG_BBLT_MEM_OFF0, 0x00},
++ {S1DREG_BBLT_MEM_OFF1, 0x00},
++ {S1DREG_BBLT_WIDTH0, 0x00},
++ {S1DREG_BBLT_WIDTH1, 0x00},
++ {S1DREG_BBLT_HEIGHT0, 0x00},
++ {S1DREG_BBLT_HEIGHT1, 0x00},
++ {S1DREG_BBLT_BGC0, 0x00},
++ {S1DREG_BBLT_BGC1, 0x00},
++ {S1DREG_BBLT_FGC0, 0x00},
++ {S1DREG_BBLT_FGC1, 0x00},
++ {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */
++ {S1DREG_LKUP_ADDR, 0x00},
++ {S1DREG_PS_CNF, 0x10}, /* Power Save disable */
++ {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */
++ {S1DREG_CPU2MEM_WDOGT, 0x00},
++ {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */
++};
++
++static struct s1d13xxxfb_pdata ek_s1dfb_pdata = {
++ .initregs = ek_s1dfb_initregs,
++ .initregssize = ARRAY_SIZE(ek_s1dfb_initregs),
++ .platform_init_video = ek_init_video,
++};
++
++static u64 s1dfb_dmamask = 0xffffffffUL;
++
++static struct resource ek_s1dfb_resource[] = {
++ [0] = { /* video mem */
++ .name = "s1d13806 memory",
++ .start = AT91_FB_VMEM_BASE,
++ .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = { /* video registers */
++ .name = "s1d13806 registers",
++ .start = AT91_FB_REG_BASE,
++ .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device ek_s1dfb_device = {
++ .name = "s1d13806fb",
++ .id = -1,
++ .dev = {
++ .dma_mask = &s1dfb_dmamask,
++ .coherent_dma_mask = 0xffffffff,
++ .platform_data = &ek_s1dfb_pdata,
++ },
++ .resource = ek_s1dfb_resource,
++ .num_resources = ARRAY_SIZE(ek_s1dfb_resource),
++};
++
++static void __init ek_add_device_video(void)
++{
++ platform_device_register(&ek_s1dfb_device);
++}
++#else
++static void __init ek_add_device_video(void) {}
++#endif
++
++static struct eth_platform_data __initdata ek_eth_data = {
+ .phy_irq_pin = AT91_PIN_PC4,
+ .is_rmii = 1,
+ };
+@@ -87,7 +270,7 @@
+
+ static struct at91_mmc_data __initdata ek_mmc_data = {
+ .det_pin = AT91_PIN_PB27,
+- .is_b = 0,
++ .slot_b = 0,
+ .wire4 = 1,
+ .wp_pin = AT91_PIN_PA17,
+ };
+@@ -107,6 +290,42 @@
+ #endif
+ };
+
++#define EK_FLASH_BASE AT91_CHIPSELECT_0
++#define EK_FLASH_SIZE 0x200000
++
++static struct physmap_flash_data ek_flash_data = {
++ .width = 2,
++};
++
++static struct resource ek_flash_resource = {
++ .start = EK_FLASH_BASE,
++ .end = EK_FLASH_BASE + EK_FLASH_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device ek_flash = {
++ .name = "physmap-flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &ek_flash_data,
++ },
++ .resource = &ek_flash_resource,
++ .num_resources = 1,
++};
++
++static struct at91_gpio_led ek_leds[] = {
++ {
++ .name = "led0",
++ .gpio = AT91_PIN_PB1,
++ .trigger = "heartbeat",
++ },
++ {
++ .name = "led1",
++ .gpio = AT91_PIN_PB2,
++ .trigger = "timer",
++ }
++};
++
+ static void __init ek_board_init(void)
+ {
+ /* Serial */
+@@ -130,8 +349,12 @@
+ at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
+ at91_add_device_mmc(&ek_mmc_data);
+ #endif
++ /* NOR Flash */
++ platform_device_register(&ek_flash);
++ /* LEDs */
++ at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+ /* VGA */
+-// ek_add_device_video();
++ ek_add_device_video();
+ }
+
+ MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-kafa.c linux-2.6.19/arch/arm/mach-at91rm9200/board-kafa.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-kafa.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-kafa.c Thu Nov 23 15:50:12 2006
+@@ -67,7 +67,7 @@
+ at91rm9200_init_interrupts(NULL);
+ }
+
+-static struct at91_eth_data __initdata kafa_eth_data = {
++static struct eth_platform_data __initdata kafa_eth_data = {
+ .phy_irq_pin = AT91_PIN_PC4,
+ .is_rmii = 0,
+ };
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-kb9202.c linux-2.6.19/arch/arm/mach-at91rm9200/board-kb9202.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-kb9202.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-kb9202.c Thu Nov 23 15:50:12 2006
+@@ -68,7 +68,7 @@
+ at91rm9200_init_interrupts(NULL);
+ }
+
+-static struct at91_eth_data __initdata kb9202_eth_data = {
++static struct eth_platform_data __initdata kb9202_eth_data = {
+ .phy_irq_pin = AT91_PIN_PB29,
+ .is_rmii = 0,
+ };
+@@ -84,7 +84,7 @@
+
+ static struct at91_mmc_data __initdata kb9202_mmc_data = {
+ .det_pin = AT91_PIN_PB2,
+- .is_b = 0,
++ .slot_b = 0,
+ .wire4 = 1,
+ };
+
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-sam9260ek.c linux-2.6.19/arch/arm/mach-at91rm9200/board-sam9260ek.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-sam9260ek.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-sam9260ek.c Sat Nov 25 10:47:45 2006
+@@ -0,0 +1,201 @@
++/*
++ * linux/arch/arm/mach-at91rm9200/board-ek.c
++ *
++ * Copyright (C) 2005 SAN People
++ * Copyright (C) 2006 Atmel
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spi/spi.h>
++
++#include <asm/hardware.h>
++#include <asm/setup.h>
++#include <asm/mach-types.h>
++#include <asm/irq.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91sam926x_mc.h>
++
++#include "generic.h"
++
++
++/*
++ * Serial port configuration.
++ * 0 .. 5 = USART0 .. USART5
++ * 6 = DBGU
++ */
++static struct at91_uart_config __initdata ek_uart_config = {
++ .console_tty = 0, /* ttyS0 */
++ .nr_tty = 3,
++ .tty_map = { 6, 0, 1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */
++};
++
++static void __init ek_map_io(void)
++{
++ /* Initialize processor: 18.432 MHz crystal */
++ at91sam9260_initialize(18432000);
++
++ /* Setup the serial ports and console */
++ at91_init_serial(&ek_uart_config);
++}
++
++static void __init ek_init_irq(void)
++{
++ at91sam9260_init_interrupts(NULL);
++}
++
++
++/*
++ * USB Host port
++ */
++static struct at91_usbh_data __initdata ek_usbh_data = {
++ .ports = 2,
++};
++
++/*
++ * USB Device port
++ */
++static struct at91_udc_data __initdata ek_udc_data = {
++ .vbus_pin = AT91_PIN_PC5,
++ .pullup_pin = 0, /* pull-up driven by UDC */
++};
++
++
++/*
++ * SPI devices.
++ */
++static struct spi_board_info ek_spi_devices[] = {
++#if !defined(CONFIG_MMC_AT91)
++ { /* DataFlash chip */
++ .modalias = "mtd_dataflash",
++ .chip_select = 1,
++ .max_speed_hz = 15 * 1000 * 1000,
++ .bus_num = 0,
++ },
++#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
++ { /* DataFlash card */
++ .modalias = "mtd_dataflash",
++ .chip_select = 0,
++ .max_speed_hz = 15 * 1000 * 1000,
++ .bus_num = 0,
++ },
++#endif
++#endif
++#if defined(CONFIG_SND_AT73C213)
++ { /* AT73C213 DAC */
++ .modalias = "snd_at73c213",
++ .chip_select = 0,
++ .max_speed_hz = 10 * 1000 * 1000,
++ .bus_num = 1,
++ },
++#endif
++};
++
++
++/*
++ * MACB Ethernet device
++ */
++static struct __initdata eth_platform_data ek_macb_data = {
++ .is_rmii = 1,
++};
++
++
++/*
++ * NAND flash
++ */
++static struct mtd_partition __initdata ek_nand_partition[] = {
++ {
++ .name = "Partition 1",
++ .offset = 0,
++ .size = 256 * 1024,
++ },
++ {
++ .name = "Partition 2",
++ .offset = 256 * 1024,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++
++static struct mtd_partition *nand_partitions(int size, int *num_partitions)
++{
++ *num_partitions = ARRAY_SIZE(ek_nand_partition);
++ return ek_nand_partition;
++}
++
++static struct at91_nand_data __initdata ek_nand_data = {
++ .ale = 21,
++ .cle = 22,
++// .det_pin = ... not connected
++ .rdy_pin = AT91_PIN_PC13,
++ .enable_pin = AT91_PIN_PC14,
++ .partition_info = nand_partitions,
++#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
++ .bus_width_16 = 1,
++#else
++ .bus_width_16 = 0,
++#endif
++};
++
++
++/*
++ * MCI (SD/MMC)
++ */
++static struct at91_mmc_data __initdata ek_mmc_data = {
++ .slot_b = 1,
++ .wire4 = 1,
++// .det_pin = ... not connected
++// .wp_pin = ... not connected
++// .vcc_pin = ... not connected
++};
++
++static void __init ek_board_init(void)
++{
++ /* Serial */
++ at91_add_device_serial();
++ /* USB Host */
++ at91_add_device_usbh(&ek_usbh_data);
++ /* USB Device */
++ at91_add_device_udc(&ek_udc_data);
++ /* SPI */
++ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
++ /* NAND */
++ at91_add_device_nand(&ek_nand_data);
++ /* Ethernet */
++ at91_add_device_eth(&ek_macb_data);
++ /* MMC */
++ at91_add_device_mmc(&ek_mmc_data);
++}
++
++MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
++ /* Maintainer: Atmel */
++ .phys_io = AT91_BASE_SYS,
++ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
++ .boot_params = AT91_SDRAM_BASE + 0x100,
++ .timer = &at91sam926x_timer,
++ .map_io = ek_map_io,
++ .init_irq = ek_init_irq,
++ .init_machine = ek_board_init,
++MACHINE_END
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/board-sam9261ek.c linux-2.6.19/arch/arm/mach-at91rm9200/board-sam9261ek.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/board-sam9261ek.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/board-sam9261ek.c Sat Nov 25 11:07:44 2006
+@@ -0,0 +1,259 @@
++/*
++ * linux/arch/arm/mach-at91rm9200/board-ek.c
++ *
++ * Copyright (C) 2005 SAN People
++ * Copyright (C) 2006 Atmel
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spi/spi.h>
++#include <linux/dm9000.h>
++
++#include <asm/hardware.h>
++#include <asm/setup.h>
++#include <asm/mach-types.h>
++#include <asm/irq.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91sam926x_mc.h>
++
++#include "generic.h"
++
++
++/*
++ * Serial port configuration.
++ * 0 .. 2 = USART0 .. USART2
++ * 3 = DBGU
++ */
++static struct at91_uart_config __initdata ek_uart_config = {
++ .console_tty = 0, /* ttyS0 */
++ .nr_tty = 1,
++ .tty_map = { 3, -1, -1, -1 } /* ttyS0, ..., ttyS3 */
++};
++
++static void __init ek_map_io(void)
++{
++ /* Initialize processor: 18.432 MHz crystal */
++ at91sam9261_initialize(18432000);
++
++ /* Setup the serial ports and console */
++ at91_init_serial(&ek_uart_config);
++}
++
++static void __init ek_init_irq(void)
++{
++ at91sam9261_init_interrupts(NULL);
++}
++
++
++/*
++ * DM9000 ethernet device
++ */
++#if defined(CONFIG_DM9000)
++static struct resource at91sam9261_dm9000_resource[] = {
++ [0] = {
++ .start = AT91_CHIPSELECT_2,
++ .end = AT91_CHIPSELECT_2 + 3,
++ .flags = IORESOURCE_MEM
++ },
++ [1] = {
++ .start = AT91_CHIPSELECT_2 + 0x44,
++ .end = AT91_CHIPSELECT_2 + 0xFF,
++ .flags = IORESOURCE_MEM
++ },
++ [2] = {
++ .start = AT91_PIN_PC11,
++ .end = AT91_PIN_PC11,
++ .flags = IORESOURCE_IRQ
++ }
++};
++
++static struct dm9000_plat_data dm9000_platdata = {
++ .flags = DM9000_PLATF_16BITONLY,
++};
++
++static struct platform_device at91sam9261_dm9000_device = {
++ .name = "dm9000",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(at91sam9261_dm9000_resource),
++ .resource = at91sam9261_dm9000_resource,
++ .dev = {
++ .platform_data = &dm9000_platdata,
++ }
++};
++
++static void __init ek_add_device_dm9000(void)
++{
++ /*
++ * Configure Chip-Select 2 on SMC for the DM9000.
++ * Note: These timings were calculated for MASTER_CLOCK = 100000000
++ * according to the DM9000 timings.
++ */
++ at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
++ at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
++ at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
++ at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
++
++ /* Configure Reset signal as output */
++ at91_set_gpio_output(AT91_PIN_PC10, 0);
++
++ /* Configure Interrupt pin as input, no pull-up */
++ at91_set_gpio_input(AT91_PIN_PC11, 0);
++
++ platform_device_register(&at91sam9261_dm9000_device);
++}
++#else
++static void __init ek_add_device_dm9000(void) {}
++#endif /* CONFIG_DM9000 */
++
++
++/*
++ * USB Host Port
++ */
++static struct at91_usbh_data __initdata ek_usbh_data = {
++ .ports = 2,
++};
++
++
++/*
++ * USB Device Port
++ */
++static struct at91_udc_data __initdata ek_udc_data = {
++ .vbus_pin = AT91_PIN_PB29,
++ .pullup_pin = 0, /* pull-up driven by UDC */
++};
++
++
++/*
++ * MCI (SD/MMC)
++ */
++static struct at91_mmc_data __initdata ek_mmc_data = {
++ .wire4 = 1,
++// .det_pin = ... not connected
++// .wp_pin = ... not connected
++// .vcc_pin = ... not connected
++};
++
++
++/*
++ * NAND flash
++ */
++static struct mtd_partition __initdata ek_nand_partition[] = {
++ {
++ .name = "Partition 1",
++ .offset = 0,
++ .size = 256 * 1024,
++ },
++ {
++ .name = "Partition 2",
++ .offset = 256 * 1024 ,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++
++static struct mtd_partition *nand_partitions(int size, int *num_partitions)
++{
++ *num_partitions = ARRAY_SIZE(ek_nand_partition);
++ return ek_nand_partition;
++}
++
++static struct at91_nand_data __initdata ek_nand_data = {
++ .ale = 22,
++ .cle = 21,
++// .det_pin = ... not connected
++ .rdy_pin = AT91_PIN_PC15,
++ .enable_pin = AT91_PIN_PC14,
++ .partition_info = nand_partitions,
++#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
++ .bus_width_16 = 1,
++#else
++ .bus_width_16 = 0,
++#endif
++};
++
++/*
++ * SPI devices
++ */
++static struct spi_board_info ek_spi_devices[] = {
++ { /* DataFlash chip */
++ .modalias = "mtd_dataflash",
++ .chip_select = 0,
++ .max_speed_hz = 15 * 1000 * 1000,
++ .bus_num = 0,
++ },
++#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
++ { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
++ .modalias = "mtd_dataflash",
++ .chip_select = 3,
++ .max_speed_hz = 15 * 1000 * 1000,
++ .bus_num = 0,
++ },
++#elif defined(CONFIG_SND_AT73C213)
++ { /* AT73C213 DAC */
++ .modalias = "snd_at73c213",
++ .chip_select = 3,
++ .max_speed_hz = 10 * 1000 * 1000,
++ .bus_num = 0,
++ },
++#endif
++};
++
++
++static void __init ek_board_init(void)
++{
++ /* Serial */
++ at91_add_device_serial();
++ /* USB Host */
++ at91_add_device_usbh(&ek_usbh_data);
++ /* USB Device */
++ at91_add_device_udc(&ek_udc_data);
++ /* I2C */
++ at91_add_device_i2c();
++ /* NAND */
++ at91_add_device_nand(&ek_nand_data);
++ /* DM9000 ethernet */
++ ek_add_device_dm9000();
++
++ /* spi0 and mmc/sd share the same PIO pins */
++#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
++ /* SPI */
++ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
++#else
++ /* MMC */
++ at91_add_device_mmc(&ek_mmc_data);
++#endif
++}
++
++MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
++ /* Maintainer: Atmel */
++ .phys_io = AT91_BASE_SYS,
++ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
++ .boot_params = AT91_SDRAM_BASE + 0x100,
++ .timer = &at91sam926x_timer,
++ .map_io = ek_map_io,
++ .init_irq = ek_init_irq,
++ .init_machine = ek_board_init,
++MACHINE_END
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/clock.c linux-2.6.19/arch/arm/mach-at91rm9200/clock.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/clock.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/clock.c Thu Nov 23 15:37:15 2006
+@@ -28,6 +28,8 @@
+ #include <asm/mach-types.h>
+
+ #include <asm/hardware.h>
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/cpu.h>
+
+ #include "clock.h"
+
+@@ -41,6 +43,7 @@
+ #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
+ #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
+ #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
++#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
+
+
+ static LIST_HEAD(clocks);
+@@ -114,13 +117,11 @@
+ static struct clk udpck = {
+ .name = "udpck",
+ .parent = &pllb,
+- .pmc_mask = AT91_PMC_UDP,
+ .mode = pmc_sys_mode,
+ };
+ static struct clk uhpck = {
+ .name = "uhpck",
+ .parent = &pllb,
+- .pmc_mask = AT91_PMC_UHP,
+ .mode = pmc_sys_mode,
+ };
+
+@@ -374,6 +375,7 @@
+ seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
+
+ seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
++#warning "Hard-coded PCK"
+ for (i = 0; i < 4; i++)
+ seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
+ seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
+@@ -434,6 +436,12 @@
+ clk->mode = pmc_periph_mode;
+ list_add_tail(&clk->node, &clocks);
+ }
++ else if (clk_is_sys(clk)) {
++ clk->parent = &mck;
++ clk->mode = pmc_sys_mode;
++
++ list_add_tail(&clk->node, &clocks);
++ }
+ #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
+ else if (clk_is_programmable(clk)) {
+ clk->mode = pmc_sys_mode;
+@@ -586,9 +594,21 @@
+ */
+ at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+ pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
+- at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
++ if (cpu_is_at91rm9200()) {
++ uhpck.pmc_mask = AT91RM9200_PMC_UHP;
++ udpck.pmc_mask = AT91RM9200_PMC_UDP;
++ at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP);
++ at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
++ } else if (cpu_is_at91sam9260()) {
++ uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
++ udpck.pmc_mask = AT91SAM926x_PMC_UDP;
++ at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP);
++ } else if (cpu_is_at91sam9261()) {
++ uhpck.pmc_mask = (AT91SAM926x_PMC_UHP | AT91_PMC_HCK0);
++ udpck.pmc_mask = AT91SAM926x_PMC_UDP;
++ at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91_PMC_HCK0 | AT91SAM926x_PMC_UDP);
++ }
+ at91_sys_write(AT91_CKGR_PLLBR, 0);
+- at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
+
+ udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+ uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/clock.h linux-2.6.19/arch/arm/mach-at91rm9200/clock.h
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/clock.h Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/clock.h Thu Nov 23 15:40:21 2006
+@@ -10,6 +10,7 @@
+ #define CLK_TYPE_PLL 0x2
+ #define CLK_TYPE_PROGRAMMABLE 0x4
+ #define CLK_TYPE_PERIPHERAL 0x8
++#define CLK_TYPE_SYSTEM 0x10
+
+
+ struct clk {
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/devices.c linux-2.6.19/arch/arm/mach-at91rm9200/devices.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/devices.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/devices.c Thu Jan 1 02:00:00 1970
+@@ -1,813 +0,0 @@
+-/*
+- * arch/arm/mach-at91rm9200/devices.c
+- *
+- * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
+- * Copyright (C) 2005 David Brownell
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- */
+-#include <asm/mach/arch.h>
+-#include <asm/mach/map.h>
+-
+-#include <linux/platform_device.h>
+-
+-#include <asm/hardware.h>
+-#include <asm/arch/board.h>
+-#include <asm/arch/gpio.h>
+-
+-#include "generic.h"
+-
+-#define SZ_512 0x00000200
+-#define SZ_256 0x00000100
+-#define SZ_16 0x00000010
+-
+-/* --------------------------------------------------------------------
+- * USB Host
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+-static u64 ohci_dmamask = 0xffffffffUL;
+-static struct at91_usbh_data usbh_data;
+-
+-static struct resource at91_usbh_resources[] = {
+- [0] = {
+- .start = AT91RM9200_UHP_BASE,
+- .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91RM9200_ID_UHP,
+- .end = AT91RM9200_ID_UHP,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device at91rm9200_usbh_device = {
+- .name = "at91_ohci",
+- .id = -1,
+- .dev = {
+- .dma_mask = &ohci_dmamask,
+- .coherent_dma_mask = 0xffffffff,
+- .platform_data = &usbh_data,
+- },
+- .resource = at91_usbh_resources,
+- .num_resources = ARRAY_SIZE(at91_usbh_resources),
+-};
+-
+-void __init at91_add_device_usbh(struct at91_usbh_data *data)
+-{
+- if (!data)
+- return;
+-
+- usbh_data = *data;
+- platform_device_register(&at91rm9200_usbh_device);
+-}
+-#else
+-void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * USB Device (Gadget)
+- * -------------------------------------------------------------------- */
+-
+-#ifdef CONFIG_USB_GADGET_AT91
+-static struct at91_udc_data udc_data;
+-
+-static struct resource at91_udc_resources[] = {
+- [0] = {
+- .start = AT91RM9200_BASE_UDP,
+- .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91RM9200_ID_UDP,
+- .end = AT91RM9200_ID_UDP,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device at91rm9200_udc_device = {
+- .name = "at91_udc",
+- .id = -1,
+- .dev = {
+- .platform_data = &udc_data,
+- },
+- .resource = at91_udc_resources,
+- .num_resources = ARRAY_SIZE(at91_udc_resources),
+-};
+-
+-void __init at91_add_device_udc(struct at91_udc_data *data)
+-{
+- if (!data)
+- return;
+-
+- if (data->vbus_pin) {
+- at91_set_gpio_input(data->vbus_pin, 0);
+- at91_set_deglitch(data->vbus_pin, 1);
+- }
+- if (data->pullup_pin)
+- at91_set_gpio_output(data->pullup_pin, 0);
+-
+- udc_data = *data;
+- platform_device_register(&at91rm9200_udc_device);
+-}
+-#else
+-void __init at91_add_device_udc(struct at91_udc_data *data) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * Ethernet
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
+-static u64 eth_dmamask = 0xffffffffUL;
+-static struct at91_eth_data eth_data;
+-
+-static struct resource at91_eth_resources[] = {
+- [0] = {
+- .start = AT91_VA_BASE_EMAC,
+- .end = AT91_VA_BASE_EMAC + SZ_16K - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91RM9200_ID_EMAC,
+- .end = AT91RM9200_ID_EMAC,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device at91rm9200_eth_device = {
+- .name = "at91_ether",
+- .id = -1,
+- .dev = {
+- .dma_mask = ð_dmamask,
+- .coherent_dma_mask = 0xffffffff,
+- .platform_data = ð_data,
+- },
+- .resource = at91_eth_resources,
+- .num_resources = ARRAY_SIZE(at91_eth_resources),
+-};
+-
+-void __init at91_add_device_eth(struct at91_eth_data *data)
+-{
+- if (!data)
+- return;
+-
+- if (data->phy_irq_pin) {
+- at91_set_gpio_input(data->phy_irq_pin, 0);
+- at91_set_deglitch(data->phy_irq_pin, 1);
+- }
+-
+- /* Pins used for MII and RMII */
+- at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
+- at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
+- at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
+- at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
+- at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
+- at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
+- at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
+- at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
+- at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
+- at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
+-
+- if (!data->is_rmii) {
+- at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
+- at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
+- at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
+- at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
+- at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
+- at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
+- at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
+- at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
+- }
+-
+- eth_data = *data;
+- platform_device_register(&at91rm9200_eth_device);
+-}
+-#else
+-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * Compact Flash / PCMCIA
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
+-static struct at91_cf_data cf_data;
+-
+-static struct resource at91_cf_resources[] = {
+- [0] = {
+- .start = AT91_CF_BASE,
+- /* ties up CS4, CS5 and CS6 */
+- .end = AT91_CF_BASE + (0x30000000 - 1),
+- .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
+- },
+-};
+-
+-static struct platform_device at91rm9200_cf_device = {
+- .name = "at91_cf",
+- .id = -1,
+- .dev = {
+- .platform_data = &cf_data,
+- },
+- .resource = at91_cf_resources,
+- .num_resources = ARRAY_SIZE(at91_cf_resources),
+-};
+-
+-void __init at91_add_device_cf(struct at91_cf_data *data)
+-{
+- if (!data)
+- return;
+-
+- /* input/irq */
+- if (data->irq_pin) {
+- at91_set_gpio_input(data->irq_pin, 1);
+- at91_set_deglitch(data->irq_pin, 1);
+- }
+- at91_set_gpio_input(data->det_pin, 1);
+- at91_set_deglitch(data->det_pin, 1);
+-
+- /* outputs, initially off */
+- if (data->vcc_pin)
+- at91_set_gpio_output(data->vcc_pin, 0);
+- at91_set_gpio_output(data->rst_pin, 0);
+-
+- /* force poweron defaults for these pins ... */
+- at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
+- at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
+- at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
+- at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
+-
+- cf_data = *data;
+- platform_device_register(&at91rm9200_cf_device);
+-}
+-#else
+-void __init at91_add_device_cf(struct at91_cf_data *data) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * MMC / SD
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_MMC_AT91RM9200) || defined(CONFIG_MMC_AT91RM9200_MODULE)
+-static u64 mmc_dmamask = 0xffffffffUL;
+-static struct at91_mmc_data mmc_data;
+-
+-static struct resource at91_mmc_resources[] = {
+- [0] = {
+- .start = AT91RM9200_BASE_MCI,
+- .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91RM9200_ID_MCI,
+- .end = AT91RM9200_ID_MCI,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device at91rm9200_mmc_device = {
+- .name = "at91_mci",
+- .id = -1,
+- .dev = {
+- .dma_mask = &mmc_dmamask,
+- .coherent_dma_mask = 0xffffffff,
+- .platform_data = &mmc_data,
+- },
+- .resource = at91_mmc_resources,
+- .num_resources = ARRAY_SIZE(at91_mmc_resources),
+-};
+-
+-void __init at91_add_device_mmc(struct at91_mmc_data *data)
+-{
+- if (!data)
+- return;
+-
+- /* input/irq */
+- if (data->det_pin) {
+- at91_set_gpio_input(data->det_pin, 1);
+- at91_set_deglitch(data->det_pin, 1);
+- }
+- if (data->wp_pin)
+- at91_set_gpio_input(data->wp_pin, 1);
+-
+- /* CLK */
+- at91_set_A_periph(AT91_PIN_PA27, 0);
+-
+- if (data->is_b) {
+- /* CMD */
+- at91_set_B_periph(AT91_PIN_PA8, 0);
+-
+- /* DAT0, maybe DAT1..DAT3 */
+- at91_set_B_periph(AT91_PIN_PA9, 0);
+- if (data->wire4) {
+- at91_set_B_periph(AT91_PIN_PA10, 0);
+- at91_set_B_periph(AT91_PIN_PA11, 0);
+- at91_set_B_periph(AT91_PIN_PA12, 0);
+- }
+- } else {
+- /* CMD */
+- at91_set_A_periph(AT91_PIN_PA28, 0);
+-
+- /* DAT0, maybe DAT1..DAT3 */
+- at91_set_A_periph(AT91_PIN_PA29, 0);
+- if (data->wire4) {
+- at91_set_B_periph(AT91_PIN_PB3, 0);
+- at91_set_B_periph(AT91_PIN_PB4, 0);
+- at91_set_B_periph(AT91_PIN_PB5, 0);
+- }
+- }
+-
+- mmc_data = *data;
+- platform_device_register(&at91rm9200_mmc_device);
+-}
+-#else
+-void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * NAND / SmartMedia
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+-static struct at91_nand_data nand_data;
+-
+-static struct resource at91_nand_resources[] = {
+- {
+- .start = AT91_SMARTMEDIA_BASE,
+- .end = AT91_SMARTMEDIA_BASE + SZ_8M - 1,
+- .flags = IORESOURCE_MEM,
+- }
+-};
+-
+-static struct platform_device at91_nand_device = {
+- .name = "at91_nand",
+- .id = -1,
+- .dev = {
+- .platform_data = &nand_data,
+- },
+- .resource = at91_nand_resources,
+- .num_resources = ARRAY_SIZE(at91_nand_resources),
+-};
+-
+-void __init at91_add_device_nand(struct at91_nand_data *data)
+-{
+- if (!data)
+- return;
+-
+- /* enable pin */
+- if (data->enable_pin)
+- at91_set_gpio_output(data->enable_pin, 1);
+-
+- /* ready/busy pin */
+- if (data->rdy_pin)
+- at91_set_gpio_input(data->rdy_pin, 1);
+-
+- /* card detect pin */
+- if (data->det_pin)
+- at91_set_gpio_input(data->det_pin, 1);
+-
+- at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
+- at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
+-
+- nand_data = *data;
+- platform_device_register(&at91_nand_device);
+-}
+-#else
+-void __init at91_add_device_nand(struct at91_nand_data *data) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * TWI (i2c)
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+-static struct platform_device at91rm9200_twi_device = {
+- .name = "at91_i2c",
+- .id = -1,
+- .num_resources = 0,
+-};
+-
+-void __init at91_add_device_i2c(void)
+-{
+- /* pins used for TWI interface */
+- at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
+- at91_set_multi_drive(AT91_PIN_PA25, 1);
+-
+- at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
+- at91_set_multi_drive(AT91_PIN_PA26, 1);
+-
+- platform_device_register(&at91rm9200_twi_device);
+-}
+-#else
+-void __init at91_add_device_i2c(void) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * SPI
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
+-static u64 spi_dmamask = 0xffffffffUL;
+-
+-static struct resource at91_spi_resources[] = {
+- [0] = {
+- .start = AT91RM9200_BASE_SPI,
+- .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91RM9200_ID_SPI,
+- .end = AT91RM9200_ID_SPI,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device at91rm9200_spi_device = {
+- .name = "at91_spi",
+- .id = 0,
+- .dev = {
+- .dma_mask = &spi_dmamask,
+- .coherent_dma_mask = 0xffffffff,
+- },
+- .resource = at91_spi_resources,
+- .num_resources = ARRAY_SIZE(at91_spi_resources),
+-};
+-
+-static const unsigned at91_spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
+-
+-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+-{
+- int i;
+- unsigned long cs_pin;
+-
+- at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
+- at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
+- at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
+-
+- /* Enable SPI chip-selects */
+- for (i = 0; i < nr_devices; i++) {
+- if (devices[i].controller_data)
+- cs_pin = (unsigned long) devices[i].controller_data;
+- else
+- cs_pin = at91_spi_standard_cs[devices[i].chip_select];
+-
+-#ifdef CONFIG_SPI_AT91_MANUAL_CS
+- at91_set_gpio_output(cs_pin, 1);
+-#else
+- at91_set_A_periph(cs_pin, 0);
+-#endif
+-
+- /* pass chip-select pin to driver */
+- devices[i].controller_data = (void *) cs_pin;
+- }
+-
+- spi_register_board_info(devices, nr_devices);
+- at91_clock_associate("spi0_clk", &at91rm9200_spi_device.dev, "spi");
+- platform_device_register(&at91rm9200_spi_device);
+-}
+-#else
+-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * RTC
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_RTC_DRV_AT91) || defined(CONFIG_RTC_DRV_AT91_MODULE)
+-static struct platform_device at91rm9200_rtc_device = {
+- .name = "at91_rtc",
+- .id = -1,
+- .num_resources = 0,
+-};
+-
+-static void __init at91_add_device_rtc(void)
+-{
+- platform_device_register(&at91rm9200_rtc_device);
+-}
+-#else
+-static void __init at91_add_device_rtc(void) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * Watchdog
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_AT91_WATCHDOG) || defined(CONFIG_AT91_WATCHDOG_MODULE)
+-static struct platform_device at91rm9200_wdt_device = {
+- .name = "at91_wdt",
+- .id = -1,
+- .num_resources = 0,
+-};
+-
+-static void __init at91_add_device_watchdog(void)
+-{
+- platform_device_register(&at91rm9200_wdt_device);
+-}
+-#else
+-static void __init at91_add_device_watchdog(void) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * LEDs
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_LEDS)
+-u8 at91_leds_cpu;
+-u8 at91_leds_timer;
+-
+-void __init at91_init_leds(u8 cpu_led, u8 timer_led)
+-{
+- at91_leds_cpu = cpu_led;
+- at91_leds_timer = timer_led;
+-}
+-#else
+-void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
+-#endif
+-
+-
+-/* --------------------------------------------------------------------
+- * UART
+- * -------------------------------------------------------------------- */
+-
+-#if defined(CONFIG_SERIAL_ATMEL)
+-static struct resource dbgu_resources[] = {
+- [0] = {
+- .start = AT91_VA_BASE_SYS + AT91_DBGU,
+- .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91_ID_SYS,
+- .end = AT91_ID_SYS,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct atmel_uart_data dbgu_data = {
+- .use_dma_tx = 0,
+- .use_dma_rx = 0, /* DBGU not capable of receive DMA */
+- .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+-};
+-
+-static struct platform_device at91rm9200_dbgu_device = {
+- .name = "atmel_usart",
+- .id = 0,
+- .dev = {
+- .platform_data = &dbgu_data,
+- .coherent_dma_mask = 0xffffffff,
+- },
+- .resource = dbgu_resources,
+- .num_resources = ARRAY_SIZE(dbgu_resources),
+-};
+-
+-static inline void configure_dbgu_pins(void)
+-{
+- at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
+- at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
+-}
+-
+-static struct resource uart0_resources[] = {
+- [0] = {
+- .start = AT91RM9200_BASE_US0,
+- .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91RM9200_ID_US0,
+- .end = AT91RM9200_ID_US0,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct atmel_uart_data uart0_data = {
+- .use_dma_tx = 1,
+- .use_dma_rx = 1,
+-};
+-
+-static struct platform_device at91rm9200_uart0_device = {
+- .name = "atmel_usart",
+- .id = 1,
+- .dev = {
+- .platform_data = &uart0_data,
+- .coherent_dma_mask = 0xffffffff,
+- },
+- .resource = uart0_resources,
+- .num_resources = ARRAY_SIZE(uart0_resources),
+-};
+-
+-static inline void configure_usart0_pins(void)
+-{
+- at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
+- at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
+- at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
+-
+- /*
+- * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
+- * We need to drive the pin manually. Default is off (RTS is active low).
+- */
+- at91_set_gpio_output(AT91_PIN_PA21, 1);
+-}
+-
+-static struct resource uart1_resources[] = {
+- [0] = {
+- .start = AT91RM9200_BASE_US1,
+- .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91RM9200_ID_US1,
+- .end = AT91RM9200_ID_US1,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct atmel_uart_data uart1_data = {
+- .use_dma_tx = 1,
+- .use_dma_rx = 1,
+-};
+-
+-static struct platform_device at91rm9200_uart1_device = {
+- .name = "atmel_usart",
+- .id = 2,
+- .dev = {
+- .platform_data = &uart1_data,
+- .coherent_dma_mask = 0xffffffff,
+- },
+- .resource = uart1_resources,
+- .num_resources = ARRAY_SIZE(uart1_resources),
+-};
+-
+-static inline void configure_usart1_pins(void)
+-{
+- at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
+- at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
+- at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
+- at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
+- at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
+- at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
+- at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
+- at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
+-}
+-
+-static struct resource uart2_resources[] = {
+- [0] = {
+- .start = AT91RM9200_BASE_US2,
+- .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91RM9200_ID_US2,
+- .end = AT91RM9200_ID_US2,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct atmel_uart_data uart2_data = {
+- .use_dma_tx = 1,
+- .use_dma_rx = 1,
+-};
+-
+-static struct platform_device at91rm9200_uart2_device = {
+- .name = "atmel_usart",
+- .id = 3,
+- .dev = {
+- .platform_data = &uart2_data,
+- .coherent_dma_mask = 0xffffffff,
+- },
+- .resource = uart2_resources,
+- .num_resources = ARRAY_SIZE(uart2_resources),
+-};
+-
+-static inline void configure_usart2_pins(void)
+-{
+- at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
+- at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
+-}
+-
+-static struct resource uart3_resources[] = {
+- [0] = {
+- .start = AT91RM9200_BASE_US3,
+- .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = {
+- .start = AT91RM9200_ID_US3,
+- .end = AT91RM9200_ID_US3,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct atmel_uart_data uart3_data = {
+- .use_dma_tx = 1,
+- .use_dma_rx = 1,
+-};
+-
+-static struct platform_device at91rm9200_uart3_device = {
+- .name = "atmel_usart",
+- .id = 4,
+- .dev = {
+- .platform_data = &uart3_data,
+- .coherent_dma_mask = 0xffffffff,
+- },
+- .resource = uart3_resources,
+- .num_resources = ARRAY_SIZE(uart3_resources),
+-};
+-
+-static inline void configure_usart3_pins(void)
+-{
+- at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
+- at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
+-}
+-
+-struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
+-struct platform_device *atmel_default_console_device; /* the serial console device */
+-
+-void __init at91_init_serial(struct at91_uart_config *config)
+-{
+- int i;
+-
+- /* Fill in list of supported UARTs */
+- for (i = 0; i < config->nr_tty; i++) {
+- switch (config->tty_map[i]) {
+- case 0:
+- configure_usart0_pins();
+- at91_uarts[i] = &at91rm9200_uart0_device;
+- at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
+- break;
+- case 1:
+- configure_usart1_pins();
+- at91_uarts[i] = &at91rm9200_uart1_device;
+- at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
+- break;
+- case 2:
+- configure_usart2_pins();
+- at91_uarts[i] = &at91rm9200_uart2_device;
+- at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
+- break;
+- case 3:
+- configure_usart3_pins();
+- at91_uarts[i] = &at91rm9200_uart3_device;
+- at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
+- break;
+- case 4:
+- configure_dbgu_pins();
+- at91_uarts[i] = &at91rm9200_dbgu_device;
+- at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
+- break;
+- default:
+- continue;
+- }
+- at91_uarts[i]->id = i; /* update ID number to mapped ID */
+- }
+-
+- /* Set serial console device */
+- if (config->console_tty < ATMEL_MAX_UART)
+- atmel_default_console_device = at91_uarts[config->console_tty];
+- if (!atmel_default_console_device)
+- printk(KERN_INFO "AT91: No default serial console defined.\n");
+-}
+-
+-void __init at91_add_device_serial(void)
+-{
+- int i;
+-
+- for (i = 0; i < ATMEL_MAX_UART; i++) {
+- if (at91_uarts[i])
+- platform_device_register(at91_uarts[i]);
+- }
+-}
+-#else
+-void __init at91_init_serial(struct at91_uart_config *config) {}
+-void __init at91_add_device_serial(void) {}
+-#endif
+-
+-
+-/* -------------------------------------------------------------------- */
+-
+-/*
+- * These devices are always present and don't need any board-specific
+- * setup.
+- */
+-static int __init at91_add_standard_devices(void)
+-{
+- at91_add_device_rtc();
+- at91_add_device_watchdog();
+- return 0;
+-}
+-
+-arch_initcall(at91_add_standard_devices);
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/generic.h linux-2.6.19/arch/arm/mach-at91rm9200/generic.h
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/generic.h Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/generic.h Wed Nov 15 09:01:27 2006
+@@ -10,14 +10,19 @@
+
+ /* Processors */
+ extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
++extern void __init at91sam9260_initialize(unsigned long main_clock);
++extern void __init at91sam9261_initialize(unsigned long main_clock);
+
+ /* Interrupts */
+ extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
++extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
++extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
+ extern void __init at91_aic_init(unsigned int priority[]);
+
+ /* Timer */
+ struct sys_timer;
+ extern struct sys_timer at91rm9200_timer;
++extern struct sys_timer at91sam926x_timer;
+
+ /* Clocks */
+ extern int __init at91_clock_init(unsigned long main_clock);
+@@ -39,3 +44,6 @@
+ };
+ extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
+ extern void __init at91_gpio_irq_setup(void);
++
++extern void (*at91_arch_reset)(void);
++extern int at91_extern_irq;
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/gpio.c linux-2.6.19/arch/arm/mach-at91rm9200/gpio.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/gpio.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/gpio.c Wed Nov 1 12:37:25 2006
+@@ -19,6 +19,8 @@
+
+ #include <asm/io.h>
+ #include <asm/hardware.h>
++#include <asm/arch/at91_pio.h>
++#include <asm/arch/at91_pmc.h>
+ #include <asm/arch/gpio.h>
+
+ #include "generic.h"
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/ics1523.c linux-2.6.19/arch/arm/mach-at91rm9200/ics1523.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/ics1523.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/ics1523.c Tue Oct 24 14:59:00 2006
+@@ -0,0 +1,227 @@
++/*
++ * arch/arm/mach-at91rm9200/ics1523.c
++ *
++ * Copyright (C) 2003 ATMEL Rousset
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <linux/delay.h>
++
++#include <asm/arch/ics1523.h>
++#include <asm/arch/at91_twi.h>
++#include <asm/arch/gpio.h>
++
++/* TWI Errors */
++#define AT91_TWI_ERROR (AT91_TWI_NACK | AT91_TWI_UNRE | AT91_TWI_OVRE)
++
++
++//-----------------------------------------------------------------------------
++//
++// TWI Register access
++//
++//-----------------------------------------------------------------------------
++
++static inline unsigned long at91_twi_read(unsigned int reg)
++{
++ void __iomem *twi_base = (void __iomem *)AT91_VA_BASE_TWI;
++
++ return __raw_readl(twi_base + reg);
++}
++
++static inline void at91_twi_write(unsigned int reg, unsigned long value)
++{
++ void __iomem *twi_base = (void __iomem *)AT91_VA_BASE_TWI;
++
++ __raw_writel(value, twi_base + reg);
++}
++
++//-----------------------------------------------------------------------------
++//
++// Initialization of TWI CLOCK
++//
++//-----------------------------------------------------------------------------
++
++static void AT91F_SetTwiClock(unsigned int mck_khz)
++{
++ int sclock;
++
++ /* Here, CKDIV = 1 and CHDIV = CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
++ sclock = (10*mck_khz /ICS_TRANSFER_RATE);
++ if (sclock % 10 >= 5)
++ sclock = (sclock /10) - 5;
++ else
++ sclock = (sclock /10)- 6;
++ sclock = (sclock + (4 - sclock %4)) >> 2; // div 4
++
++ at91_twi_write(AT91_TWI_CWGR, 0x00010000 | sclock | (sclock << 8));
++}
++
++//-----------------------------------------------------------------------------
++//
++// Read a byte with TWI Interface from the Clock Generator ICS1523
++//
++//-----------------------------------------------------------------------------
++
++static int AT91F_ICS1523_ReadByte(unsigned char reg_address, unsigned char *data_in)
++{
++ int Status, nb_trial;
++
++ at91_twi_write(AT91_TWI_MMR, AT91_TWI_MREAD | AT91_TWI_IADRSZ_1 | ((ICS_ADD << 16) & AT91_TWI_DADR));
++ at91_twi_write(AT91_TWI_IADR, reg_address);
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
++
++ // Program temporizing period (300us)
++ udelay(300);
++
++ // Wait TXcomplete ...
++ nb_trial = 0;
++ Status = at91_twi_read(AT91_TWI_SR);
++ while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
++ nb_trial++;
++ Status = at91_twi_read(AT91_TWI_SR);
++ }
++
++ if (Status & AT91_TWI_TXCOMP) {
++ *data_in = (unsigned char) at91_twi_read(AT91_TWI_RHR);
++ return ((int) ICS1523_ACCESS_OK);
++ }
++ return ((int) ICS1523_ACCESS_ERROR);
++}
++
++//-----------------------------------------------------------------------------
++//
++// Write a byte with TWI Interface to the Clock Generator ICS1523
++//
++//-----------------------------------------------------------------------------
++
++static int AT91F_ICS1523_WriteByte(unsigned char reg_address, unsigned char data_out)
++{
++ int Status, nb_trial;
++
++ at91_twi_write(AT91_TWI_MMR, AT91_TWI_IADRSZ_1 | ((ICS_ADD << 16) & AT91_TWI_DADR));
++ at91_twi_write(AT91_TWI_IADR, reg_address);
++ at91_twi_write(AT91_TWI_THR, data_out);
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
++
++ // Program temporizing period (300us)
++ udelay(300);
++
++ nb_trial = 0;
++ Status = at91_twi_read(AT91_TWI_SR);
++ while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
++ nb_trial++;
++ if (Status & AT91_TWI_ERROR) {
++ // Si Under run OR NACK Start again
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
++
++ // Program temporizing period (300us)
++ udelay(300);
++ }
++ Status = at91_twi_read(AT91_TWI_SR);
++ };
++
++ if (Status & AT91_TWI_TXCOMP)
++ return ((int) ICS1523_ACCESS_OK);
++ else
++ return ((int) ICS1523_ACCESS_ERROR);
++}
++
++//-----------------------------------------------------------------------------
++//
++// Initialization of the Clock Generator ICS1523
++//
++//-----------------------------------------------------------------------------
++
++int AT91F_ICS1523_clockinit(void)
++{
++ int ack, nb_trial, error_status;
++ unsigned int status = 0xffffffff;
++ struct clk *twi_clk;
++
++ error_status = (int) ICS1523_ACCESS_OK;
++
++ /* pins used for TWI interface */
++ at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
++ at91_set_multi_drive(AT91_PIN_PA25, 1);
++ at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
++ at91_set_multi_drive(AT91_PIN_PA26, 1);
++
++ // Enable the TWI clock.
++ twi_clk = clk_get(NULL, "twi_clk");
++ if (IS_ERR(twi_clk))
++ return ICS1523_ACCESS_ERROR;
++ clk_enable(twi_clk);
++
++ // Disable interrupts
++ at91_twi_write(AT91_TWI_IDR, -1);
++
++ // Reset peripheral
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST);
++
++ // Set Master mode
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN);
++
++ // Set TWI Clock Waveform Generator Register
++ AT91F_SetTwiClock(60000); // MCK in KHz = 60000 KHz
++
++ // ICS1523 Initialisation
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) 0);
++ error_status |= ack;
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_OE, (unsigned char) (ICS_OEF | ICS_OET2 | ICS_OETCK));
++ error_status |= ack;
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_OD, (unsigned char) (ICS_INSEL | 0x7F));
++ error_status |= ack;
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0);
++ error_status |= ack;
++
++ nb_trial = 0;
++ do {
++ nb_trial++;
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) (ICS_ENDLS | ICS_ENPLS | ICS_PDEN /*| ICS_FUNCSEL*/));
++ error_status |= ack;
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_LCR, (unsigned char) (ICS_PSD | ICS_PFD));
++ error_status |= ack;
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_FD0, (unsigned char) 0x39) ; /* 0x7A */
++ error_status |= ack;
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_FD1, (unsigned char) 0x00);
++ error_status |= ack;
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_PLLR));
++ error_status |= ack;
++
++ // Program 1ms temporizing period
++ mdelay(1);
++
++ AT91F_ICS1523_ReadByte ((unsigned char) ICS_SR, (char *)&status);
++ } while (!((unsigned int) status & (unsigned int) ICS_PLLLOCK) && (nb_trial < 10));
++
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_DPAC, (unsigned char) 0x03) ; /* 0x01 */
++ error_status |= ack;
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_DPAR));
++ error_status |= ack;
++
++ /* Program 1ms temporizing period */
++ mdelay(1);
++
++ ack = AT91F_ICS1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0x00);
++ error_status |= ack;
++
++ /* Program 1ms temporizing period */
++ mdelay(1);
++
++ return (error_status);
++}
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/irq.c linux-2.6.19/arch/arm/mach-at91rm9200/irq.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/irq.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/irq.c Wed Nov 1 12:40:39 2006
+@@ -47,6 +47,10 @@
+ at91_sys_write(AT91_AIC_IECR, 1 << irq);
+ }
+
++unsigned int at91_extern_irq;
++
++#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
++
+ static int at91_aic_set_type(unsigned irq, unsigned type)
+ {
+ unsigned int smr, srctype;
+@@ -59,14 +63,16 @@
+ srctype = AT91_AIC_SRCTYPE_RISING;
+ break;
+ case IRQT_LOW:
+- if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */
++ if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
++ srctype = AT91_AIC_SRCTYPE_LOW;
++ else
+ return -EINVAL;
+- srctype = AT91_AIC_SRCTYPE_LOW;
+ break;
+ case IRQT_FALLING:
+- if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */
++ if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
++ srctype = AT91_AIC_SRCTYPE_FALLING;
++ else
+ return -EINVAL;
+- srctype = AT91_AIC_SRCTYPE_FALLING;
+ break;
+ default:
+ return -EINVAL;
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/pm.c linux-2.6.19/arch/arm/mach-at91rm9200/pm.c
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/pm.c Mon Dec 4 16:39:29 2006
++++ linux-2.6.19/arch/arm/mach-at91rm9200/pm.c Thu Nov 16 11:51:41 2006
+@@ -26,7 +26,10 @@
+ #include <asm/mach/irq.h>
+ #include <asm/mach-types.h>
+
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/at91rm9200_mc.h>
+ #include <asm/arch/gpio.h>
++#include <asm/arch/cpu.h>
+
+ #include "generic.h"
+
+@@ -60,6 +63,7 @@
+ * Verify that all the clocks are correct before entering
+ * slow-clock mode.
+ */
++#warning "SAM9260 only has 3 programmable clocks."
+ static int at91_pm_verify_clocks(void)
+ {
+ unsigned long scsr;
+@@ -68,9 +72,15 @@
+ scsr = at91_sys_read(AT91_PMC_SCSR);
+
+ /* USB must not be using PLLB */
+- if ((scsr & (AT91_PMC_UHP | AT91_PMC_UDP)) != 0) {
+- pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
+- return 0;
++ if (cpu_is_at91rm9200()) {
++ if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
++ pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
++ return 0;
++ }
++ } else if (cpu_is_at91sam9261()) {
++#warning "Check SAM9261 USB clocks"
++ } else if (cpu_is_at91sam9260()) {
++#warning "Check SAM9260 USB clocks"
+ }
+
+ #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
+@@ -112,7 +122,6 @@
+ static void (*slow_clock)(void);
+
+
+-
+ static int at91_pm_enter(suspend_state_t state)
+ {
+ at91_gpio_suspend();
+@@ -123,13 +132,7 @@
+ (at91_sys_read(AT91_PMC_PCSR)
+ | (1 << AT91_ID_FIQ)
+ | (1 << AT91_ID_SYS)
+- | (1 << AT91RM9200_ID_IRQ0)
+- | (1 << AT91RM9200_ID_IRQ1)
+- | (1 << AT91RM9200_ID_IRQ2)
+- | (1 << AT91RM9200_ID_IRQ3)
+- | (1 << AT91RM9200_ID_IRQ4)
+- | (1 << AT91RM9200_ID_IRQ5)
+- | (1 << AT91RM9200_ID_IRQ6))
++ | (at91_extern_irq))
+ & at91_sys_read(AT91_AIC_IMR),
+ state);
+
+@@ -203,16 +206,23 @@
+ .enter = at91_pm_enter,
+ };
+
++#ifdef CONFIG_AT91_SLOW_CLOCK
++extern void at91rm9200_slow_clock(void);
++extern u32 at91rm9200_slow_clock_sz;
++#endif
++
+ static int __init at91_pm_init(void)
+ {
+- printk("AT91: Power Management\n");
+-
+-#ifdef CONFIG_AT91_PM_SLOW_CLOCK
+- /* REVISIT allocations of SRAM should be dynamically managed.
++#ifdef CONFIG_AT91_SLOW_CLOCK
++ /*
++ * REVISIT allocations of SRAM should be dynamically managed.
+ * FIQ handlers and other components will want SRAM/TCM too...
+ */
+- slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K));
++ slow_clock = (void *) (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE + (3 * SZ_4K));
+ memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz);
++ printk("AT91: Power Management (with slow clock mode)\n");
++#else
++ printk("AT91: Power Management\n");
+ #endif
+
+ /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */
+diff -urN -x CVS linux-2.6.19-final/arch/arm/mach-at91rm9200/pm_slowclock.S linux-2.6.19/arch/arm/mach-at91rm9200/pm_slowclock.S
+--- linux-2.6.19-final/arch/arm/mach-at91rm9200/pm_slowclock.S Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/arch/arm/mach-at91rm9200/pm_slowclock.S Thu Nov 16 11:47:10 2006
+@@ -0,0 +1,170 @@
++/*
++ * arch/arm/mach-at91rm9200/pm_slow_clock.S
++ *
++ * Copyright (C) 2006 Savin Zlobec
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/linkage.h>
++#include <asm/hardware.h>
++
++#define MCKRDY_TIMEOUT 1000
++#define MOSCRDY_TIMEOUT 1000
++#define PLLALOCK_TIMEOUT 1000
++
++ .macro wait_mckrdy
++ mov r2, #MCKRDY_TIMEOUT
++1: sub r2, r2, #1
++ cmp r2, #0
++ beq 2f
++ ldr r3, [r1, #AT91_PMC_SR]
++ tst r3, #AT91_PMC_MCKRDY
++ beq 1b
++2:
++ .endm
++
++ .macro wait_moscrdy
++ mov r2, #MOSCRDY_TIMEOUT
++1: sub r2, r2, #1
++ cmp r2, #0
++ beq 2f
++ ldr r3, [r1, #AT91_PMC_SR]
++ tst r3, #AT91_PMC_MOSCS
++ beq 1b
++2:
++ .endm
++
++ .macro wait_pllalock
++ mov r2, #PLLALOCK_TIMEOUT
++1: sub r2, r2, #1
++ cmp r2, #0
++ beq 2f
++ ldr r3, [r1, #AT91_PMC_SR]
++ tst r3, #AT91_PMC_LOCKA
++ beq 1b
++2:
++ .endm
++
++ .macro wait_plladis
++ mov r2, #PLLALOCK_TIMEOUT
++1: sub r2, r2, #1
++ cmp r2, #0
++ beq 2f
++ ldr r3, [r1, #AT91_PMC_SR]
++ tst r3, #AT91_PMC_LOCKA
++ bne 1b
++2:
++ .endm
++
++ .text
++
++ENTRY(at91rm9200_slow_clock)
++
++ ldr r1, .at91_va_base_sys
++
++ /* Put SDRAM in self refresh mode */
++
++ b 1f
++ .align 5
++1: mcr p15, 0, r0, c7, c10, 4
++ mov r2, #1
++ str r2, [r1, #AT91_SDRAMC_SRR]
++
++ /* Save Master clock setting */
++
++ ldr r2, [r1, #AT91_PMC_MCKR]
++ str r2, .saved_mckr
++
++ /*
++ * Set the Master clock source to slow clock
++ *
++ * First set the CSS field, wait for MCKRDY
++ * and than set the PRES and MDIV fields.
++ *
++ * See eratta #2[78] for details.
++ */
++
++ bic r2, r2, #3
++ str r2, [r1, #AT91_PMC_MCKR]
++
++ wait_mckrdy
++
++ mov r2, #0
++ str r2, [r1, #AT91_PMC_MCKR]
++
++ /* Save PLLA setting and disable it */
++
++ ldr r2, [r1, #AT91_CKGR_PLLAR]
++ str r2, .saved_pllar
++
++ mov r2, #0
++ str r2, [r1, #AT91_CKGR_PLLAR]
++
++ wait_plladis
++
++ /* Turn off the main oscillator */
++
++ ldr r2, [r1, #AT91_CKGR_MOR]
++ bic r2, r2, #AT91_PMC_MOSCEN
++ str r2, [r1, #AT91_CKGR_MOR]
++
++ /* Wait for interrupt */
++
++ mcr p15, 0, r0, c7, c0, 4
++
++ /* Turn on the main oscillator */
++
++ ldr r2, [r1, #AT91_CKGR_MOR]
++ orr r2, r2, #AT91_PMC_MOSCEN
++ str r2, [r1, #AT91_CKGR_MOR]
++
++ wait_moscrdy
++
++ /* Restore PLLA setting */
++
++ ldr r2, .saved_pllar
++ str r2, [r1, #AT91_CKGR_PLLAR]
++
++ wait_pllalock
++
++ /*
++ * Restore master clock setting
++ *
++ * First set PRES if it was not 0,
++ * than set CSS and MDIV fields.
++ * After every change wait for
++ * MCKRDY.
++ *
++ * See eratta #2[78] for details.
++ */
++
++ ldr r2, .saved_mckr
++ tst r2, #0x1C
++ beq 2f
++ and r2, r2, #0x1C
++ str r2, [r1, #AT91_PMC_MCKR]
++
++ wait_mckrdy
++
++2: ldr r2, .saved_mckr
++ str r2, [r1, #AT91_PMC_MCKR]
++
++ wait_mckrdy
++
++ mov pc, lr
++
++.saved_mckr:
++ .word 0
++
++.saved_pllar:
++ .word 0
++
++.at91_va_base_sys:
++ .word AT91_VA_BASE_SYS
++
++ENTRY(at91rm9200_slow_clock_sz)
++ .word .-at91rm9200_slow_clock
+diff -urN -x CVS linux-2.6.19-final/drivers/char/Kconfig linux-2.6.19/drivers/char/Kconfig
+--- linux-2.6.19-final/drivers/char/Kconfig Mon Dec 4 16:39:54 2006
++++ linux-2.6.19/drivers/char/Kconfig Thu Nov 16 16:34:39 2006
+@@ -1048,5 +1048,21 @@
+ sysfs directory, /sys/devices/platform/telco_clock, with a number of
+ files for controlling the behavior of this hardware.
+
++config AT91_SPI
++ bool "SPI driver (legacy) for AT91RM9200 processors"
++ depends on ARCH_AT91RM9200
++ default y
++ help
++ The SPI driver gives access to this serial bus on the AT91RM9200
++ processor.
++
++config AT91_SPIDEV
++ bool "SPI device interface (legacy) for AT91RM9200 processors"
++ depends on ARCH_AT91RM9200 && AT91_SPI
++ default n
++ help
++ The SPI driver gives user mode access to this serial
++ bus on the AT91RM9200 processor.
++
+ endmenu
+
+diff -urN -x CVS linux-2.6.19-final/drivers/char/Makefile linux-2.6.19/drivers/char/Makefile
+--- linux-2.6.19-final/drivers/char/Makefile Mon Dec 4 16:39:54 2006
++++ linux-2.6.19/drivers/char/Makefile Thu Oct 12 17:07:38 2006
+@@ -90,6 +90,8 @@
+ obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o
+ obj-$(CONFIG_TANBAC_TB0219) += tb0219.o
+ obj-$(CONFIG_TELCLOCK) += tlclk.o
++obj-$(CONFIG_AT91_SPI) += at91_spi.o
++obj-$(CONFIG_AT91_SPIDEV) += at91_spidev.o
+
+ obj-$(CONFIG_WATCHDOG) += watchdog/
+ obj-$(CONFIG_MWAVE) += mwave/
+diff -urN -x CVS linux-2.6.19-final/drivers/char/at91_spi.c linux-2.6.19/drivers/char/at91_spi.c
+--- linux-2.6.19-final/drivers/char/at91_spi.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/char/at91_spi.c Tue Oct 24 14:31:50 2006
+@@ -0,0 +1,336 @@
++/*
++ * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 (Thunder)
++ *
++ * Copyright (C) SAN People (Pty) Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/dma-mapping.h>
++#include <linux/module.h>
++#include <linux/sched.h>
++#include <linux/completion.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <asm/io.h>
++#include <asm/semaphore.h>
++
++#include <asm/arch/at91_spi.h>
++#include <asm/arch/at91_pdc.h>
++#include <asm/arch/board.h>
++#include <asm/arch/spi.h>
++
++#undef DEBUG_SPI
++
++static struct spi_local spi_dev[NR_SPI_DEVICES]; /* state of the SPI devices */
++static int spi_enabled = 0;
++static struct semaphore spi_lock; /* protect access to SPI bus */
++static int current_device = -1; /* currently selected SPI device */
++static struct clk *spi_clk; /* SPI clock */
++static void __iomem *spi_base; /* SPI peripheral base-address */
++
++DECLARE_COMPLETION(transfer_complete);
++
++
++#define at91_spi_read(reg) __raw_readl(spi_base + (reg))
++#define at91_spi_write(reg, val) __raw_writel((val), spi_base + (reg))
++
++
++/* ......................................................................... */
++
++/*
++ * Access and enable the SPI bus.
++ * This MUST be called before any transfers are performed.
++ */
++void spi_access_bus(short device)
++{
++ /* Ensure that requested device is valid */
++ if ((device < 0) || (device >= NR_SPI_DEVICES))
++ panic("at91_spi: spi_access_bus called with invalid device");
++
++ if (spi_enabled == 0) {
++ clk_enable(spi_clk); /* Enable Peripheral clock */
++ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */
++#ifdef DEBUG_SPI
++ printk("SPI on\n");
++#endif
++ }
++ spi_enabled++;
++
++ /* Lock the SPI bus */
++ down(&spi_lock);
++ current_device = device;
++
++ /* Configure SPI bus for device */
++ at91_spi_write(AT91_SPI_MR, AT91_SPI_MSTR | AT91_SPI_MODFDIS | (spi_dev[device].pcs << 16));
++}
++
++/*
++ * Relinquish control of the SPI bus.
++ */
++void spi_release_bus(short device)
++{
++ if (device != current_device)
++ panic("at91_spi: spi_release called with invalid device");
++
++ /* Release the SPI bus */
++ current_device = -1;
++ up(&spi_lock);
++
++ spi_enabled--;
++ if (spi_enabled == 0) {
++ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */
++ clk_disable(spi_clk); /* Disable Peripheral clock */
++#ifdef DEBUG_SPI
++ printk("SPI off\n");
++#endif
++ }
++}
++
++/*
++ * Perform a data transfer over the SPI bus
++ */
++int spi_transfer(struct spi_transfer_list* list)
++{
++ struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
++ int tx_size;
++
++ if (!list)
++ panic("at91_spi: spi_transfer called with NULL transfer list");
++ if (current_device == -1)
++ panic("at91_spi: spi_transfer called without acquiring bus");
++
++#ifdef DEBUG_SPI
++ printk("SPI transfer start [%i]\n", list->nr_transfers);
++#endif
++
++ /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
++ tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
++
++ /* Store transfer list */
++ device->xfers = list;
++ list->curr = 0;
++
++ /* Assume there must be at least one transfer */
++ device->tx = dma_map_single(NULL, list->tx[0], list->txlen[0], DMA_TO_DEVICE);
++ device->rx = dma_map_single(NULL, list->rx[0], list->rxlen[0], DMA_FROM_DEVICE);
++
++ /* Program PDC registers */
++ at91_spi_write(AT91_PDC_TPR, device->tx);
++ at91_spi_write(AT91_PDC_RPR, device->rx);
++ at91_spi_write(AT91_PDC_TCR, list->txlen[0] / tx_size);
++ at91_spi_write(AT91_PDC_RCR, list->rxlen[0] / tx_size);
++
++ /* Is there a second transfer? */
++ if (list->nr_transfers > 1) {
++ device->txnext = dma_map_single(NULL, list->tx[1], list->txlen[1], DMA_TO_DEVICE);
++ device->rxnext = dma_map_single(NULL, list->rx[1], list->rxlen[1], DMA_FROM_DEVICE);
++
++ /* Program Next PDC registers */
++ at91_spi_write(AT91_PDC_TNPR, device->txnext);
++ at91_spi_write(AT91_PDC_RNPR, device->rxnext);
++ at91_spi_write(AT91_PDC_TNCR, list->txlen[1] / tx_size);
++ at91_spi_write(AT91_PDC_RNCR, list->rxlen[1] / tx_size);
++ }
++ else {
++ device->txnext = 0;
++ device->rxnext = 0;
++ at91_spi_write(AT91_PDC_TNCR, 0);
++ at91_spi_write(AT91_PDC_RNCR, 0);
++ }
++
++ // TODO: If we are doing consecutive transfers (at high speed, or
++ // small buffers), then it might be worth modifying the 'Delay between
++ // Consecutive Transfers' in the CSR registers.
++ // This is an issue if we cannot chain the next buffer fast enough
++ // in the interrupt handler.
++
++ /* Enable transmitter and receiver */
++ at91_spi_write(AT91_PDC_PTCR, AT91_PDC_RXTEN | AT91_PDC_TXTEN);
++
++ at91_spi_write(AT91_SPI_IER, AT91_SPI_ENDRX); /* enable buffer complete interrupt */
++ wait_for_completion(&transfer_complete);
++
++#ifdef DEBUG_SPI
++ printk("SPI transfer end\n");
++#endif
++
++ return 0;
++}
++
++/* ......................................................................... */
++
++/*
++ * Handle interrupts from the SPI controller.
++ */
++static irqreturn_t at91spi_interrupt(int irq, void *dev_id)
++{
++ unsigned int status;
++ struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
++ struct spi_transfer_list *list = device->xfers;
++
++#ifdef DEBUG_SPI
++ printk("SPI interrupt %i\n", current_device);
++#endif
++
++ if (!list)
++ panic("at91_spi: spi_interrupt with a NULL transfer list");
++
++ status = at91_spi_read(AT91_SPI_SR) & at91_spi_read(AT91_SPI_IMR); /* read status */
++
++ dma_unmap_single(NULL, device->tx, list->txlen[list->curr], DMA_TO_DEVICE);
++ dma_unmap_single(NULL, device->rx, list->rxlen[list->curr], DMA_FROM_DEVICE);
++
++ device->tx = device->txnext; /* move next transfer to current transfer */
++ device->rx = device->rxnext;
++
++ list->curr = list->curr + 1;
++ if (list->curr == list->nr_transfers) { /* all transfers complete */
++ at91_spi_write(AT91_SPI_IDR, AT91_SPI_ENDRX); /* disable interrupt */
++
++ /* Disable transmitter and receiver */
++ at91_spi_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
++
++ device->xfers = NULL;
++ complete(&transfer_complete);
++ }
++ else if (list->curr+1 == list->nr_transfers) { /* no more next transfers */
++ device->txnext = 0;
++ device->rxnext = 0;
++ at91_spi_write(AT91_PDC_TNCR, 0);
++ at91_spi_write(AT91_PDC_RNCR, 0);
++ }
++ else {
++ int i = (list->curr)+1;
++
++ /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
++ int tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
++
++ device->txnext = dma_map_single(NULL, list->tx[i], list->txlen[i], DMA_TO_DEVICE);
++ device->rxnext = dma_map_single(NULL, list->rx[i], list->rxlen[i], DMA_FROM_DEVICE);
++ at91_spi_write(AT91_PDC_TNPR, device->txnext);
++ at91_spi_write(AT91_PDC_RNPR, device->rxnext);
++ at91_spi_write(AT91_PDC_TNCR, list->txlen[i] / tx_size);
++ at91_spi_write(AT91_PDC_RNCR, list->rxlen[i] / tx_size);
++ }
++ return IRQ_HANDLED;
++}
++
++/* ......................................................................... */
++
++/*
++ * Initialize the SPI controller
++ */
++static int __init at91spi_probe(struct platform_device *pdev)
++{
++ int i;
++ unsigned long scbr;
++ struct resource *res;
++
++ init_MUTEX(&spi_lock);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENXIO;
++
++ if (!request_mem_region(res->start, res->end - res->start + 1, "at91_spi"))
++ return -EBUSY;
++
++ spi_base = ioremap(res->start, res->end - res->start + 1);
++ if (!spi_base) {
++ release_mem_region(res->start, res->end - res->start + 1);
++ return -ENOMEM;
++ }
++
++ spi_clk = clk_get(NULL, "spi_clk");
++ if (IS_ERR(spi_clk)) {
++ printk(KERN_ERR "at91_spi: no clock defined\n");
++ iounmap(spi_base);
++ release_mem_region(res->start, res->end - res->start + 1);
++ return -ENODEV;
++ }
++
++ at91_spi_write(AT91_SPI_CR, AT91_SPI_SWRST); /* software reset of SPI controller */
++
++ /*
++ * Calculate the correct SPI baud-rate divisor.
++ */
++ scbr = clk_get_rate(spi_clk) / (2 * DEFAULT_SPI_CLK);
++ scbr = scbr + 1; /* round up */
++
++ printk(KERN_INFO "at91_spi: Baud rate set to %ld\n", clk_get_rate(spi_clk) / (2 * scbr));
++
++ /* Set Chip Select registers to good defaults */
++ for (i = 0; i < 4; i++) {
++ at91_spi_write(AT91_SPI_CSR(i), AT91_SPI_CPOL | AT91_SPI_BITS_8 | (16 << 16) | (scbr << 8));
++ }
++
++ at91_spi_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
++
++ memset(&spi_dev, 0, sizeof(spi_dev));
++ spi_dev[0].pcs = 0xE;
++ spi_dev[1].pcs = 0xD;
++ spi_dev[2].pcs = 0xB;
++ spi_dev[3].pcs = 0x7;
++
++ if (request_irq(AT91RM9200_ID_SPI, at91spi_interrupt, 0, "spi", NULL)) {
++ clk_put(spi_clk);
++ iounmap(spi_base);
++ release_mem_region(res->start, res->end - res->start + 1);
++ return -EBUSY;
++ }
++
++ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */
++
++ return 0;
++}
++
++static int __devexit at91spi_remove(struct platform_device *pdev)
++{
++ struct resource *res;
++
++ at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */
++ clk_put(spi_clk);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ iounmap(spi_base);
++ release_mem_region(res->start, res->end - res->start + 1);
++
++ free_irq(AT91RM9200_ID_SPI, 0);
++ return 0;
++}
++
++static struct platform_driver at91spi_driver = {
++ .probe = at91spi_probe,
++ .remove = __devexit_p(at91spi_remove),
++ .driver = {
++ .name = "at91_spi",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init at91spi_init(void)
++{
++ return platform_driver_register(&at91spi_driver);
++}
++
++static void __exit at91spi_exit(void)
++{
++ platform_driver_unregister(&at91spi_driver);
++}
++
++EXPORT_SYMBOL(spi_access_bus);
++EXPORT_SYMBOL(spi_release_bus);
++EXPORT_SYMBOL(spi_transfer);
++
++module_init(at91spi_init);
++module_exit(at91spi_exit);
++
++MODULE_LICENSE("GPL")
++MODULE_AUTHOR("Andrew Victor")
++MODULE_DESCRIPTION("SPI driver for Atmel AT91RM9200")
+diff -urN -x CVS linux-2.6.19-final/drivers/char/at91_spidev.c linux-2.6.19/drivers/char/at91_spidev.c
+--- linux-2.6.19-final/drivers/char/at91_spidev.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/char/at91_spidev.c Tue Oct 24 14:58:33 2006
+@@ -0,0 +1,236 @@
++/*
++ * User-space interface to the SPI bus on Atmel AT91RM9200
++ *
++ * Copyright (C) 2003 SAN People (Pty) Ltd
++ *
++ * Based on SPI driver by Rick Bronson
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/highmem.h>
++#include <linux/pagemap.h>
++#include <asm/arch/spi.h>
++
++#ifdef CONFIG_DEVFS_FS
++#include <linux/devfs_fs_kernel.h>
++#endif
++
++
++#undef DEBUG_SPIDEV
++
++/* ......................................................................... */
++
++/*
++ * Read or Write to SPI bus.
++ */
++static ssize_t spidev_rd_wr(struct file *file, char *buf, size_t count, loff_t *offset)
++{
++ unsigned int spi_device = (unsigned int) file->private_data;
++
++ struct mm_struct * mm;
++ struct page ** maplist;
++ struct spi_transfer_list* list;
++ int pgcount;
++
++ unsigned int ofs, pagelen;
++ int res, i, err;
++
++ if (!count) {
++ return 0;
++ }
++
++ list = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
++ if (!list) {
++ return -ENOMEM;
++ }
++
++ mm = current->mm;
++
++ pgcount = ((unsigned long)buf+count+PAGE_SIZE-1)/PAGE_SIZE - (unsigned long)buf/PAGE_SIZE;
++
++ if (pgcount >= MAX_SPI_TRANSFERS) {
++ kfree(list);
++ return -EFBIG;
++ }
++
++ maplist = kmalloc (pgcount * sizeof (struct page *), GFP_KERNEL);
++
++ if (!maplist) {
++ kfree(list);
++ return -ENOMEM;
++ }
++ flush_cache_all();
++ down_read(&mm->mmap_sem);
++ err= get_user_pages(current, mm, (unsigned long)buf, pgcount, 1, 0, maplist, NULL);
++ up_read(&mm->mmap_sem);
++
++ if (err < 0) {
++ kfree(list);
++ kfree(maplist);
++ return err;
++ }
++ pgcount = err;
++
++#ifdef DEBUG_SPIDEV
++ printk("spidev_rd_rw: %i %i\n", count, pgcount);
++#endif
++
++ /* Set default return value = transfer length */
++ res = count;
++
++ /*
++ * At this point, the virtual area buf[0] .. buf[count-1] will have
++ * corresponding pages mapped in the physical memory and locked until
++ * we unmap the kiobuf. The pages cannot be swapped out or moved
++ * around.
++ */
++ ofs = (unsigned long) buf & (PAGE_SIZE -1);
++ pagelen = PAGE_SIZE - ofs;
++ if (count < pagelen)
++ pagelen = count;
++
++ for (i = 0; i < pgcount; i++) {
++ flush_dcache_page(maplist[i]);
++
++ list->tx[i] = list->rx[i] = page_address(maplist[i]) + ofs;
++ list->txlen[i] = list->rxlen[i] = pagelen;
++
++#ifdef DEBUG_SPIDEV
++ printk(" %i: %x (%i)\n", i, list->tx[i], list->txlen[i]);
++#endif
++
++ ofs = 0; /* all subsequent transfers start at beginning of a page */
++ count = count - pagelen;
++ pagelen = (count < PAGE_SIZE) ? count : PAGE_SIZE;
++ }
++ list->nr_transfers = pgcount;
++
++ /* Perform transfer on SPI bus */
++ spi_access_bus(spi_device);
++ spi_transfer(list);
++ spi_release_bus(spi_device);
++
++ while (pgcount--) {
++ page_cache_release (maplist[pgcount]);
++ }
++ flush_cache_all();
++
++ kfree(maplist);
++ kfree(list);
++
++ return res;
++}
++
++static int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
++{
++ int spi_device = MINOR(inode->i_rdev);
++
++ if (spi_device >= NR_SPI_DEVICES)
++ return -ENODEV;
++
++ // TODO: This interface can be used to configure the SPI bus.
++ // Configurable options could include: Speed, Clock Polarity, Clock Phase
++
++ switch(cmd) {
++ default:
++ return -ENOIOCTLCMD;
++ }
++}
++
++/*
++ * Open the SPI device
++ */
++static int spidev_open(struct inode *inode, struct file *file)
++{
++ unsigned int spi_device = MINOR(inode->i_rdev);
++
++ if (spi_device >= NR_SPI_DEVICES)
++ return -ENODEV;
++
++ /*
++ * 'private_data' is actually a pointer, but we overload it with the
++ * value we want to store.
++ */
++ file->private_data = (void *)spi_device;
++
++ return 0;
++}
++
++/*
++ * Close the SPI device
++ */
++static int spidev_close(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++/* ......................................................................... */
++
++static struct file_operations spidev_fops = {
++ .owner = THIS_MODULE,
++ .llseek = no_llseek,
++ .read = spidev_rd_wr,
++ .write = (int (*) (struct file *file, const char *buf, size_t count, loff_t *offset))spidev_rd_wr,
++ .ioctl = spidev_ioctl,
++ .open = spidev_open,
++ .release = spidev_close,
++};
++
++/*
++ * Install the SPI /dev interface driver
++ */
++static int __init at91_spidev_init(void)
++{
++#ifdef CONFIG_DEVFS_FS
++ int i;
++#endif
++
++ if (register_chrdev(SPI_MAJOR, "spi", &spidev_fops)) {
++ printk(KERN_ERR "at91_spidev: Unable to get major %d for SPI bus\n", SPI_MAJOR);
++ return -EIO;
++ }
++
++#ifdef CONFIG_DEVFS_FS
++ devfs_mk_dir("spi");
++ for (i = 0; i < NR_SPI_DEVICES; i++) {
++ devfs_mk_cdev(MKDEV(SPI_MAJOR, i), S_IFCHR | S_IRUSR | S_IWUSR, "spi/%d",i);
++ }
++#endif
++ printk(KERN_INFO "AT91 SPI driver loaded\n");
++
++ return 0;
++}
++
++/*
++ * Remove the SPI /dev interface driver
++ */
++static void __exit at91_spidev_exit(void)
++{
++#ifdef CONFIG_DEVFS_FS
++ int i;
++ for (i = 0; i < NR_SPI_DEVICES; i++) {
++ devfs_remove("spi/%d", i);
++ }
++
++ devfs_remove("spi");
++#endif
++
++ if (unregister_chrdev(SPI_MAJOR, "spi")) {
++ printk(KERN_ERR "at91_spidev: Unable to release major %d for SPI bus\n", SPI_MAJOR);
++ return;
++ }
++}
++
++module_init(at91_spidev_init);
++module_exit(at91_spidev_exit);
++
++MODULE_LICENSE("GPL")
++MODULE_AUTHOR("Andrew Victor")
++MODULE_DESCRIPTION("SPI /dev interface for Atmel AT91RM9200")
+diff -urN -x CVS linux-2.6.19-final/drivers/char/watchdog/at91rm9200_wdt.c linux-2.6.19/drivers/char/watchdog/at91rm9200_wdt.c
+--- linux-2.6.19-final/drivers/char/watchdog/at91rm9200_wdt.c Mon Dec 4 16:39:59 2006
++++ linux-2.6.19/drivers/char/watchdog/at91rm9200_wdt.c Wed Nov 8 12:40:58 2006
+@@ -21,6 +21,7 @@
+ #include <linux/watchdog.h>
+ #include <asm/bitops.h>
+ #include <asm/uaccess.h>
++#include <asm/arch/at91_st.h>
+
+
+ #define WDT_DEFAULT_TIME 5 /* seconds */
+diff -urN -x CVS linux-2.6.19-final/drivers/i2c/busses/Kconfig linux-2.6.19/drivers/i2c/busses/Kconfig
+--- linux-2.6.19-final/drivers/i2c/busses/Kconfig Mon Dec 4 16:40:01 2006
++++ linux-2.6.19/drivers/i2c/busses/Kconfig Thu Oct 12 17:07:38 2006
+@@ -74,6 +74,13 @@
+ This driver can also be built as a module. If so, the module
+ will be called i2c-amd8111.
+
++config I2C_AT91
++ tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
++ depends on I2C && ARCH_AT91 && EXPERIMENTAL
++ help
++ This supports the use of the I2C interface on Atmel AT91
++ processors.
++
+ config I2C_AU1550
+ tristate "Au1550/Au1200 SMBus interface"
+ depends on I2C && (SOC_AU1550 || SOC_AU1200)
+@@ -520,6 +527,14 @@
+ This driver can also be built as a module. If so, the module
+ will be called i2c-voodoo3.
+
++config I2C_PCA
++ tristate "PCA9564"
++ depends on I2C
++ select I2C_ALGOPCA
++ help
++ This driver support the Philips PCA 9564 Parallel bus to I2C
++ bus controller.
++
+ config I2C_PCA_ISA
+ tristate "PCA9564 on an ISA bus"
+ depends on I2C
+diff -urN -x CVS linux-2.6.19-final/drivers/i2c/busses/Makefile linux-2.6.19/drivers/i2c/busses/Makefile
+--- linux-2.6.19-final/drivers/i2c/busses/Makefile Mon Dec 4 16:40:01 2006
++++ linux-2.6.19/drivers/i2c/busses/Makefile Thu Oct 12 17:07:38 2006
+@@ -8,6 +8,7 @@
+ obj-$(CONFIG_I2C_AMD756) += i2c-amd756.o
+ obj-$(CONFIG_I2C_AMD756_S4882) += i2c-amd756-s4882.o
+ obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
++obj-$(CONFIG_I2C_AT91) += i2c-at91.o
+ obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
+ obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
+ obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o
+@@ -27,6 +28,7 @@
+ obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
+ obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
+ obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o
++obj-$(CONFIG_I2C_PCA) += i2c-pca.o
+ obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
+ obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
+ obj-$(CONFIG_I2C_PROSAVAGE) += i2c-prosavage.o
+diff -urN -x CVS linux-2.6.19-final/drivers/i2c/busses/i2c-at91.c linux-2.6.19/drivers/i2c/busses/i2c-at91.c
+--- linux-2.6.19-final/drivers/i2c/busses/i2c-at91.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/i2c/busses/i2c-at91.c Fri Nov 10 09:18:41 2006
+@@ -0,0 +1,325 @@
++/*
++ i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
++
++ Copyright (C) 2004 Rick Bronson
++ Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
++
++ Borrowed heavily from original work by:
++ Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 2 of the License, or
++ (at your option) any later version.
++*/
++
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/pci.h>
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++
++#include <asm/io.h>
++
++#include <asm/arch/at91_twi.h>
++#include <asm/arch/board.h>
++#include <asm/arch/cpu.h>
++
++#define TWI_CLOCK 100000 /* Hz. max 400 Kbits/sec */
++
++
++static struct clk *twi_clk;
++static void __iomem *twi_base;
++
++#define at91_twi_read(reg) __raw_readl(twi_base + (reg))
++#define at91_twi_write(reg, val) __raw_writel((val), twi_base + (reg))
++
++
++/*
++ * Initialize the TWI hardware registers.
++ */
++static void __devinit at91_twi_hwinit(void)
++{
++ unsigned long cdiv, ckdiv;
++
++ at91_twi_write(AT91_TWI_IDR, 0xffffffff); /* Disable all interrupts */
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST); /* Reset peripheral */
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN); /* Set Master mode */
++
++ /* Calcuate clock dividers */
++ cdiv = (clk_get_rate(twi_clk) / (2 * TWI_CLOCK)) - 3;
++ cdiv = cdiv + 1; /* round up */
++ ckdiv = 0;
++ while (cdiv > 255) {
++ ckdiv++;
++ cdiv = cdiv >> 1;
++ }
++
++ if (cpu_is_at91rm9200()) { /* AT91RM9200 Errata #22 */
++ if (ckdiv > 5) {
++ printk(KERN_ERR "AT91 I2C: Invalid TWI_CLOCK value!\n");
++ ckdiv = 5;
++ }
++ }
++
++ at91_twi_write(AT91_TWI_CWGR, (ckdiv << 16) | (cdiv << 8) | cdiv);
++}
++
++/*
++ * Poll the i2c status register until the specified bit is set.
++ * Returns 0 if timed out (100 msec).
++ */
++static short at91_poll_status(unsigned long bit)
++{
++ int loop_cntr = 10000;
++
++ do {
++ udelay(10);
++ } while (!(at91_twi_read(AT91_TWI_SR) & bit) && (--loop_cntr > 0));
++
++ return (loop_cntr > 0);
++}
++
++static int xfer_read(struct i2c_adapter *adap, unsigned char *buf, int length)
++{
++ /* Send Start */
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_START);
++
++ /* Read data */
++ while (length--) {
++ if (!length) /* need to send Stop before reading last byte */
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_STOP);
++ if (!at91_poll_status(AT91_TWI_RXRDY)) {
++ dev_dbg(&adap->dev, "RXRDY timeout\n");
++ return -ETIMEDOUT;
++ }
++ *buf++ = (at91_twi_read(AT91_TWI_RHR) & 0xff);
++ }
++
++ return 0;
++}
++
++static int xfer_write(struct i2c_adapter *adap, unsigned char *buf, int length)
++{
++ /* Load first byte into transmitter */
++ at91_twi_write(AT91_TWI_THR, *buf++);
++
++ /* Send Start */
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_START);
++
++ do {
++ if (!at91_poll_status(AT91_TWI_TXRDY)) {
++ dev_dbg(&adap->dev, "TXRDY timeout\n");
++ return -ETIMEDOUT;
++ }
++
++ length--; /* byte was transmitted */
++
++ if (length > 0) /* more data to send? */
++ at91_twi_write(AT91_TWI_THR, *buf++);
++ } while (length);
++
++ /* Send Stop */
++ at91_twi_write(AT91_TWI_CR, AT91_TWI_STOP);
++
++ return 0;
++}
++
++/*
++ * Generic i2c master transfer entrypoint.
++ *
++ * Note: We do not use Atmel's feature of storing the "internal device address".
++ * Instead the "internal device address" has to be written using a seperate
++ * i2c message.
++ * http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2004-September/024411.html
++ */
++static int at91_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
++{
++ int i, ret;
++
++ dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
++
++ for (i = 0; i < num; i++) {
++ dev_dbg(&adap->dev, " #%d: %sing %d byte%s %s 0x%02x\n", i,
++ pmsg->flags & I2C_M_RD ? "read" : "writ",
++ pmsg->len, pmsg->len > 1 ? "s" : "",
++ pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
++
++ at91_twi_write(AT91_TWI_MMR, (pmsg->addr << 16)
++ | ((pmsg->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
++
++ if (pmsg->len && pmsg->buf) { /* sanity check */
++ if (pmsg->flags & I2C_M_RD)
++ ret = xfer_read(adap, pmsg->buf, pmsg->len);
++ else
++ ret = xfer_write(adap, pmsg->buf, pmsg->len);
++
++ if (ret)
++ return ret;
++
++ /* Wait until transfer is finished */
++ if (!at91_poll_status(AT91_TWI_TXCOMP)) {
++ dev_dbg(&adap->dev, "TXCOMP timeout\n");
++ return -ETIMEDOUT;
++ }
++ }
++ dev_dbg(&adap->dev, "transfer complete\n");
++ pmsg++; /* next message */
++ }
++ return i;
++}
++
++/*
++ * Return list of supported functionality.
++ */
++static u32 at91_func(struct i2c_adapter *adapter)
++{
++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++static struct i2c_algorithm at91_algorithm = {
++ .master_xfer = at91_xfer,
++ .functionality = at91_func,
++};
++
++/*
++ * Main initialization routine.
++ */
++static int __devinit at91_i2c_probe(struct platform_device *pdev)
++{
++ struct i2c_adapter *adapter;
++ struct resource *res;
++ int rc;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENXIO;
++
++ if (!request_mem_region(res->start, res->end - res->start + 1, "at91_i2c"))
++ return -EBUSY;
++
++ twi_base = ioremap(res->start, res->end - res->start + 1);
++ if (!twi_base) {
++ rc = -ENOMEM;
++ goto fail0;
++ }
++
++ twi_clk = clk_get(NULL, "twi_clk");
++ if (IS_ERR(twi_clk)) {
++ dev_err(&pdev->dev, "no clock defined\n");
++ rc = -ENODEV;
++ goto fail1;
++ }
++
++ adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
++ if (adapter == NULL) {
++ dev_err(&pdev->dev, "can't allocate inteface!\n");
++ rc = -ENOMEM;
++ goto fail2;
++ }
++ sprintf(adapter->name, "AT91");
++ adapter->algo = &at91_algorithm;
++ adapter->class = I2C_CLASS_HWMON;
++ adapter->dev.parent = &pdev->dev;
++
++ platform_set_drvdata(pdev, adapter);
++
++ clk_enable(twi_clk); /* enable peripheral clock */
++ at91_twi_hwinit(); /* initialize TWI controller */
++
++ rc = i2c_add_adapter(adapter);
++ if (rc) {
++ dev_err(&pdev->dev, "Adapter %s registration failed\n",
++ adapter->name);
++ goto fail3;
++ }
++
++ dev_info(&pdev->dev, "AT91 i2c bus driver.\n");
++ return 0;
++
++fail3:
++ platform_set_drvdata(pdev, NULL);
++ kfree(adapter);
++ clk_disable(twi_clk);
++fail2:
++ clk_put(twi_clk);
++fail1:
++ iounmap(twi_base);
++fail0:
++ release_mem_region(res->start, res->end - res->start + 1);
++
++ return rc;
++}
++
++static int __devexit at91_i2c_remove(struct platform_device *pdev)
++{
++ struct i2c_adapter *adapter = platform_get_drvdata(pdev);
++ struct resource *res;
++ int rc;
++
++ rc = i2c_del_adapter(adapter);
++ platform_set_drvdata(pdev, NULL);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ iounmap(twi_base);
++ release_mem_region(res->start, res->end - res->start + 1);
++
++ clk_disable(twi_clk); /* disable peripheral clock */
++ clk_put(twi_clk);
++
++ return rc;
++}
++
++#ifdef CONFIG_PM
++
++/* NOTE: could save a few mA by keeping clock off outside of at91_xfer... */
++
++static int at91_i2c_suspend(struct platform_device *pdev, pm_message_t mesg)
++{
++ clk_disable(twi_clk);
++ return 0;
++}
++
++static int at91_i2c_resume(struct platform_device *pdev)
++{
++ return clk_enable(twi_clk);
++}
++
++#else
++#define at91_i2c_suspend NULL
++#define at91_i2c_resume NULL
++#endif
++
++static struct platform_driver at91_i2c_driver = {
++ .probe = at91_i2c_probe,
++ .remove = __devexit_p(at91_i2c_remove),
++ .suspend = at91_i2c_suspend,
++ .resume = at91_i2c_resume,
++ .driver = {
++ .name = "at91_i2c",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init at91_i2c_init(void)
++{
++ return platform_driver_register(&at91_i2c_driver);
++}
++
++static void __exit at91_i2c_exit(void)
++{
++ platform_driver_unregister(&at91_i2c_driver);
++}
++
++module_init(at91_i2c_init);
++module_exit(at91_i2c_exit);
++
++MODULE_AUTHOR("Rick Bronson");
++MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
++MODULE_LICENSE("GPL");
+diff -urN -x CVS linux-2.6.19-final/drivers/i2c/busses/i2c-pca.c linux-2.6.19/drivers/i2c/busses/i2c-pca.c
+--- linux-2.6.19-final/drivers/i2c/busses/i2c-pca.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/i2c/busses/i2c-pca.c Mon Oct 16 16:10:42 2006
+@@ -0,0 +1,202 @@
++/*
++ * Platform driver for PCA9564 I2C bus controller.
++ *
++ * (C) 2006 Andrew Victor
++ *
++ * Based on i2c-pca-isa.c driver for PCA9564 on ISA boards
++ * Copyright (C) 2004 Arcom Control Systems
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/wait.h>
++#include <linux/platform_device.h>
++
++#include <linux/i2c.h>
++#include <linux/i2c-algo-pca.h>
++
++#include <asm/io.h>
++
++#include "../algos/i2c-algo-pca.h"
++
++#define PCA_OWN_ADDRESS 0x55 /* our address for slave mode */
++#define PCA_CLOCK I2C_PCA_CON_59kHz
++
++//#define DEBUG_IO
++
++#define PCA_IO_SIZE 4
++
++static void __iomem *base_addr;
++static int irq;
++static wait_queue_head_t pca_wait;
++
++static int pca_getown(struct i2c_algo_pca_data *adap)
++{
++ return PCA_OWN_ADDRESS;
++}
++
++static int pca_getclock(struct i2c_algo_pca_data *adap)
++{
++ return PCA_CLOCK;
++}
++
++static void pca_writebyte(struct i2c_algo_pca_data *adap, int reg, int val)
++{
++#ifdef DEBUG_IO
++ static char *names[] = { "T/O", "DAT", "ADR", "CON" };
++ printk("*** write %s at %#lx <= %#04x\n", names[reg], (unsigned long) base_addr+reg, val);
++#endif
++ outb(val, base_addr+reg);
++}
++
++static int pca_readbyte(struct i2c_algo_pca_data *adap, int reg)
++{
++ int res = inb(base_addr+reg);
++#ifdef DEBUG_IO
++ {
++ static char *names[] = { "STA", "DAT", "ADR", "CON" };
++ printk("*** read %s => %#04x\n", names[reg], res);
++ }
++#endif
++ return res;
++}
++
++static int pca_waitforinterrupt(struct i2c_algo_pca_data *adap)
++{
++ int ret = 0;
++
++ if (irq > -1) {
++ ret = wait_event_interruptible(pca_wait,
++ pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI);
++ } else {
++ while ((pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
++ udelay(100);
++ }
++ return ret;
++}
++
++static irqreturn_t pca_handler(int this_irq, void *dev_id)
++{
++ wake_up_interruptible(&pca_wait);
++ return IRQ_HANDLED;
++}
++
++static struct i2c_algo_pca_data pca_i2c_data = {
++ .get_own = pca_getown,
++ .get_clock = pca_getclock,
++ .write_byte = pca_writebyte,
++ .read_byte = pca_readbyte,
++ .wait_for_interrupt = pca_waitforinterrupt,
++};
++
++static struct i2c_adapter pca_i2c_ops = {
++ .owner = THIS_MODULE,
++ .id = I2C_HW_A_PLAT,
++ .algo_data = &pca_i2c_data,
++ .name = "PCA9564",
++};
++
++static int __devinit pca_i2c_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++
++ init_waitqueue_head(&pca_wait);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENODEV;
++
++ if (!request_mem_region(res->start, PCA_IO_SIZE, "PCA9564"))
++ return -ENXIO;
++
++ base_addr = ioremap(res->start, PCA_IO_SIZE);
++ if (base_addr == NULL)
++ goto out_region;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq > -1) {
++ if (request_irq(irq, pca_handler, 0, "pca9564", NULL) < 0) {
++ printk(KERN_ERR "i2c-pca: Request irq%d failed\n", irq);
++ goto out_remap;
++ }
++ }
++
++ if (i2c_pca_add_bus(&pca_i2c_ops) < 0) {
++ printk(KERN_ERR "i2c-pca: Failed to add i2c bus\n");
++ goto out_irq;
++ }
++
++ return 0;
++
++ out_irq:
++ if (irq > -1)
++ free_irq(irq, &pca_i2c_ops);
++
++ out_remap:
++ iounmap(base_addr);
++
++ out_region:
++ release_mem_region(res->start, PCA_IO_SIZE);
++ return -ENODEV;
++}
++
++static int __devexit pca_i2c_remove(struct platform_device *pdev)
++{
++ struct resource *res;
++
++ i2c_pca_del_bus(&pca_i2c_ops);
++
++ if (irq > 0)
++ free_irq(irq, NULL);
++
++ iounmap(base_addr);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ release_mem_region(res->start, PCA_IO_SIZE);
++
++ return 0;
++}
++
++static struct platform_driver pca_i2c_driver = {
++ .probe = pca_i2c_probe,
++ .remove = __devexit_p(pca_i2c_remove),
++ .driver = {
++ .name = "pca9564",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init pca_i2c_init(void)
++{
++ return platform_driver_register(&pca_i2c_driver);
++}
++
++static void __exit pca_i2c_exit(void)
++{
++ platform_driver_unregister(&pca_i2c_driver);
++}
++
++module_init(pca_i2c_init);
++module_exit(pca_i2c_exit);
++
++MODULE_AUTHOR("Andrew Victor");
++MODULE_DESCRIPTION("PCA9564 platform driver");
++MODULE_LICENSE("GPL");
+diff -urN -x CVS linux-2.6.19-final/drivers/leds/Kconfig linux-2.6.19/drivers/leds/Kconfig
+--- linux-2.6.19-final/drivers/leds/Kconfig Mon Dec 4 16:33:34 2006
++++ linux-2.6.19/drivers/leds/Kconfig Thu Nov 16 17:15:16 2006
+@@ -76,6 +76,13 @@
+ This option enables support for the Soekris net4801 and net4826 error
+ LED.
+
++config LEDS_AT91
++ tristate "LED support using AT91 GPIOs"
++ depends LEDS_CLASS && ARCH_AT91 && !LEDS
++ help
++ This option enables support for LEDs connected to GPIO lines
++ on AT91-based boards.
++
+ comment "LED Triggers"
+
+ config LEDS_TRIGGERS
+diff -urN -x CVS linux-2.6.19-final/drivers/leds/Makefile linux-2.6.19/drivers/leds/Makefile
+--- linux-2.6.19-final/drivers/leds/Makefile Mon Dec 4 16:33:34 2006
++++ linux-2.6.19/drivers/leds/Makefile Thu Nov 16 12:52:06 2006
+@@ -13,6 +13,7 @@
+ obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o
+ obj-$(CONFIG_LEDS_AMS_DELTA) += leds-ams-delta.o
+ obj-$(CONFIG_LEDS_NET48XX) += leds-net48xx.o
++obj-$(CONFIG_LEDS_AT91) += leds-at91.o
+
+ # LED Triggers
+ obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
+diff -urN -x CVS linux-2.6.19-final/drivers/leds/leds-at91.c linux-2.6.19/drivers/leds/leds-at91.c
+--- linux-2.6.19-final/drivers/leds/leds-at91.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/leds/leds-at91.c Mon Nov 20 11:02:21 2006
+@@ -0,0 +1,140 @@
++/*
++ * AT91 GPIO based LED driver
++ *
++ * Copyright (C) 2006 David Brownell
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/leds.h>
++
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++
++static LIST_HEAD(at91_led_list); /* list of AT91 LEDs */
++
++struct at91_led {
++ struct led_classdev cdev;
++ struct list_head list;
++ struct at91_gpio_led *led_data;
++};
++
++/*
++ * Change the state of the LED.
++ */
++static void at91_led_set(struct led_classdev *cdev, enum led_brightness value)
++{
++ struct at91_led *led = container_of(cdev, struct at91_led, cdev);
++ short active = (value == LED_OFF);
++
++ if (led->led_data->flags & 1) /* active high/low? */
++ active = !active;
++ at91_set_gpio_value(led->led_data->gpio, value == LED_OFF);
++}
++
++static int __devexit at91_led_remove(struct platform_device *pdev)
++{
++ struct at91_led *led;
++
++ list_for_each_entry (led, &at91_led_list, list)
++ led_classdev_unregister(&led->cdev);
++
++#warning "Free allocated memory"
++ // TODO: Free memory. kfree(led);
++
++ return 0;
++}
++
++static int __init at91_led_probe(struct platform_device *pdev)
++{
++ int status = 0;
++ struct at91_gpio_led *pdata = pdev->dev.platform_data;
++ unsigned nr_leds;
++ struct at91_led *led;
++
++ if (!pdata)
++ return -ENODEV;
++
++ nr_leds = pdata->index; /* first index stores number of LEDs */
++
++ while (nr_leds--) {
++ led = kzalloc(sizeof(struct at91_led), GFP_KERNEL);
++ if (!led) {
++ dev_err(&pdev->dev, "No memory for device\n");
++ status = -ENOMEM;
++ goto cleanup;
++ }
++ led->led_data = pdata;
++ led->cdev.name = pdata->name;
++ led->cdev.brightness_set = at91_led_set,
++ led->cdev.default_trigger = pdata->trigger;
++
++ status = led_classdev_register(&pdev->dev, &led->cdev);
++ if (status < 0) {
++ dev_err(&pdev->dev, "led_classdev_register failed - %d\n", status);
++cleanup:
++ at91_led_remove(pdev);
++ break;
++ }
++ list_add(&led->list, &at91_led_list);
++ pdata++;
++ }
++ return status;
++}
++
++#ifdef CONFIG_PM
++static int at91_led_suspend(struct platform_device *dev, pm_message_t state)
++{
++ struct at91_led *led;
++
++ list_for_each_entry (led, &at91_led_list, list)
++ led_classdev_suspend(&led->cdev);
++
++ return 0;
++}
++
++static int at91_led_resume(struct platform_device *dev)
++{
++ struct at91_led *led;
++
++ list_for_each_entry (led, &at91_led_list, list)
++ led_classdev_resume(&led->cdev);
++
++ return 0;
++}
++#else
++#define at91_led_suspend NULL
++#define at91_led_resume NULL
++#endif
++
++static struct platform_driver at91_led_driver = {
++ .probe = at91_led_probe,
++ .remove = __devexit_p(at91_led_remove),
++ .suspend = at91_led_suspend,
++ .resume = at91_led_resume,
++ .driver = {
++ .name = "at91_leds",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init at91_led_init(void)
++{
++ return platform_driver_register(&at91_led_driver);
++}
++module_init(at91_led_init);
++
++static void __exit at91_led_exit(void)
++{
++ platform_driver_unregister(&at91_led_driver);
++}
++module_exit(at91_led_exit);
++
++MODULE_DESCRIPTION("AT91 GPIO LED driver");
++MODULE_AUTHOR("David Brownell");
++MODULE_LICENSE("GPL");
+diff -urN -x CVS linux-2.6.19-final/drivers/mmc/Kconfig linux-2.6.19/drivers/mmc/Kconfig
+--- linux-2.6.19-final/drivers/mmc/Kconfig Mon Dec 4 16:40:13 2006
++++ linux-2.6.19/drivers/mmc/Kconfig Thu Nov 9 14:16:55 2006
+@@ -91,11 +91,11 @@
+
+ If unsure, say N.
+
+-config MMC_AT91RM9200
+- tristate "AT91RM9200 SD/MMC Card Interface support"
+- depends on ARCH_AT91RM9200 && MMC
++config MMC_AT91
++ tristate "AT91 SD/MMC Card Interface support"
++ depends on ARCH_AT91 && MMC
+ help
+- This selects the AT91RM9200 MCI controller.
++ This selects the AT91 MCI controller.
+
+ If unsure, say N.
+
+diff -urN -x CVS linux-2.6.19-final/drivers/mmc/Makefile linux-2.6.19/drivers/mmc/Makefile
+--- linux-2.6.19-final/drivers/mmc/Makefile Mon Dec 4 16:40:13 2006
++++ linux-2.6.19/drivers/mmc/Makefile Thu Nov 9 14:17:47 2006
+@@ -22,7 +22,7 @@
+ obj-$(CONFIG_MMC_WBSD) += wbsd.o
+ obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
+ obj-$(CONFIG_MMC_OMAP) += omap.o
+-obj-$(CONFIG_MMC_AT91RM9200) += at91_mci.o
++obj-$(CONFIG_MMC_AT91) += at91_mci.o
+ obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
+
+ mmc_core-y := mmc.o mmc_sysfs.o
+diff -urN -x CVS linux-2.6.19-final/drivers/mmc/at91_mci.c linux-2.6.19/drivers/mmc/at91_mci.c
+--- linux-2.6.19-final/drivers/mmc/at91_mci.c Mon Dec 4 16:40:13 2006
++++ linux-2.6.19/drivers/mmc/at91_mci.c Sat Nov 25 11:00:45 2006
+@@ -1,5 +1,5 @@
+ /*
+- * linux/drivers/mmc/at91_mci.c - ATMEL AT91RM9200 MCI Driver
++ * linux/drivers/mmc/at91_mci.c - ATMEL AT91 MCI Driver
+ *
+ * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
+ *
+@@ -11,7 +11,7 @@
+ */
+
+ /*
+- This is the AT91RM9200 MCI driver that has been tested with both MMC cards
++ This is the AT91 MCI driver that has been tested with both MMC cards
+ and SD-cards. Boards that support write protect are now supported.
+ The CCAT91SBC001 board does not support SD cards.
+
+@@ -38,8 +38,8 @@
+ controller to manage the transfers.
+
+ A read is done from the controller directly to the scatterlist passed in from the request.
+- Due to a bug in the controller, when a read is completed, all the words are byte
+- swapped in the scatterlist buffers.
++ Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
++ swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug.
+
+ The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
+
+@@ -72,42 +72,27 @@
+ #include <asm/irq.h>
+ #include <asm/mach/mmc.h>
+ #include <asm/arch/board.h>
++#include <asm/arch/cpu.h>
+ #include <asm/arch/gpio.h>
+-#include <asm/arch/at91rm9200_mci.h>
+-#include <asm/arch/at91rm9200_pdc.h>
++#include <asm/arch/at91_mci.h>
++#include <asm/arch/at91_pdc.h>
+
+ #define DRIVER_NAME "at91_mci"
+
+ #undef SUPPORT_4WIRE
+
+-static struct clk *mci_clk;
++#define FL_SENT_COMMAND (1 << 0)
++#define FL_SENT_STOP (1 << 1)
+
+-#define FL_SENT_COMMAND (1 << 0)
+-#define FL_SENT_STOP (1 << 1)
++#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
++ | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
++ | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
+
++#define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg))
++#define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
+
+
+ /*
+- * Read from a MCI register.
+- */
+-static inline unsigned long at91_mci_read(unsigned int reg)
+-{
+- void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
+-
+- return __raw_readl(mci_base + reg);
+-}
+-
+-/*
+- * Write to a MCI register.
+- */
+-static inline void at91_mci_write(unsigned int reg, unsigned long value)
+-{
+- void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
+-
+- __raw_writel(value, mci_base + reg);
+-}
+-
+-/*
+ * Low level type for this driver
+ */
+ struct at91mci_host
+@@ -116,9 +101,14 @@
+ struct mmc_command *cmd;
+ struct mmc_request *request;
+
++ void __iomem *baseaddr;
++ int irq;
++
+ struct at91_mmc_data *board;
+ int present;
+
++ struct clk *mci_clk;
++
+ /*
+ * Flag indicating when the command has been sent. This is used to
+ * work out whether or not to send the stop
+@@ -158,7 +148,6 @@
+ for (i = 0; i < len; i++) {
+ struct scatterlist *sg;
+ int amount;
+- int index;
+ unsigned int *sgbuffer;
+
+ sg = &data->sg[i];
+@@ -166,10 +155,15 @@
+ sgbuffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
+ amount = min(size, sg->length);
+ size -= amount;
+- amount /= 4;
+-
+- for (index = 0; index < amount; index++)
+- *dmabuf++ = swab32(sgbuffer[index]);
++
++ if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
++ int index;
++
++ for (index = 0; index < (amount / 4); index++)
++ *dmabuf++ = swab32(sgbuffer[index]);
++ }
++ else
++ memcpy(dmabuf, sgbuffer, amount);
+
+ kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
+
+@@ -217,13 +211,13 @@
+
+ /* Check to see if this needs filling */
+ if (i == 0) {
+- if (at91_mci_read(AT91_PDC_RCR) != 0) {
++ if (at91_mci_read(host, AT91_PDC_RCR) != 0) {
+ pr_debug("Transfer active in current\n");
+ continue;
+ }
+ }
+ else {
+- if (at91_mci_read(AT91_PDC_RNCR) != 0) {
++ if (at91_mci_read(host, AT91_PDC_RNCR) != 0) {
+ pr_debug("Transfer active in next\n");
+ continue;
+ }
+@@ -240,12 +234,12 @@
+ pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
+
+ if (i == 0) {
+- at91_mci_write(AT91_PDC_RPR, sg->dma_address);
+- at91_mci_write(AT91_PDC_RCR, sg->length / 4);
++ at91_mci_write(host, AT91_PDC_RPR, sg->dma_address);
++ at91_mci_write(host, AT91_PDC_RCR, sg->length / 4);
+ }
+ else {
+- at91_mci_write(AT91_PDC_RNPR, sg->dma_address);
+- at91_mci_write(AT91_PDC_RNCR, sg->length / 4);
++ at91_mci_write(host, AT91_PDC_RNPR, sg->dma_address);
++ at91_mci_write(host, AT91_PDC_RNCR, sg->length / 4);
+ }
+ }
+
+@@ -276,8 +270,6 @@
+
+ while (host->in_use_index < host->transfer_index) {
+ unsigned int *buffer;
+- int index;
+- int len;
+
+ struct scatterlist *sg;
+
+@@ -295,11 +287,14 @@
+
+ data->bytes_xfered += sg->length;
+
+- len = sg->length / 4;
+-
+- for (index = 0; index < len; index++) {
+- buffer[index] = swab32(buffer[index]);
++ if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
++ int index;
++
++ for (index = 0; index < (sg->length / 4); index++) {
++ buffer[index] = swab32(buffer[index]);
++ }
+ }
++
+ kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
+ flush_dcache_page(sg->page);
+ }
+@@ -308,57 +303,34 @@
+ if (host->transfer_index < data->sg_len)
+ at91mci_pre_dma_read(host);
+ else {
+- at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
+- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
++ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
++ at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
+ }
+
+ pr_debug("post dma read done\n");
+ }
+
+-/*
+- * Handle transmitted data
+- */
+-static void at91_mci_handle_transmitted(struct at91mci_host *host)
+-{
+- struct mmc_command *cmd;
+- struct mmc_data *data;
+-
+- pr_debug("Handling the transmit\n");
+-
+- /* Disable the transfer */
+- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
+-
+- /* Now wait for cmd ready */
+- at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
+- at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
+-
+- cmd = host->cmd;
+- if (!cmd) return;
+-
+- data = cmd->data;
+- if (!data) return;
+-
+- data->bytes_xfered = host->total_length;
+-}
+
+ /*
+ * Enable the controller
+ */
+-static void at91_mci_enable(void)
++static void at91_mci_enable(struct at91mci_host *host)
+ {
+- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
+- at91_mci_write(AT91_MCI_IDR, 0xFFFFFFFF);
+- at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
+- at91_mci_write(AT91_MCI_MR, 0x834A);
+- at91_mci_write(AT91_MCI_SDCR, 0x0);
++ at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
++ at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
++ at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
++ at91_mci_write(host, AT91_MCI_MR, AT91_MCI_PDCMODE | 0x34a);
++
++ /* use Slot A or B (only one at same time) */
++ at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b);
+ }
+
+ /*
+ * Disable the controller
+ */
+-static void at91_mci_disable(void)
++static void at91_mci_disable(struct at91mci_host *host)
+ {
+- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
++ at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
+ }
+
+ /*
+@@ -378,13 +350,13 @@
+
+ /* Not sure if this is needed */
+ #if 0
+- if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
++ if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
+ pr_debug("Clearing timeout\n");
+- at91_mci_write(AT91_MCI_ARGR, 0);
+- at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
+- while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
++ at91_mci_write(host, AT91_MCI_ARGR, 0);
++ at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
++ while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
+ /* spin */
+- pr_debug("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
++ pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
+ }
+ }
+ #endif
+@@ -431,32 +403,32 @@
+ /*
+ * Set the arguments and send the command
+ */
+- pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n",
+- cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
++ pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
++ cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
+
+ if (!data) {
+- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
+- at91_mci_write(AT91_PDC_RPR, 0);
+- at91_mci_write(AT91_PDC_RCR, 0);
+- at91_mci_write(AT91_PDC_RNPR, 0);
+- at91_mci_write(AT91_PDC_RNCR, 0);
+- at91_mci_write(AT91_PDC_TPR, 0);
+- at91_mci_write(AT91_PDC_TCR, 0);
+- at91_mci_write(AT91_PDC_TNPR, 0);
+- at91_mci_write(AT91_PDC_TNCR, 0);
++ at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
++ at91_mci_write(host, AT91_PDC_RPR, 0);
++ at91_mci_write(host, AT91_PDC_RCR, 0);
++ at91_mci_write(host, AT91_PDC_RNPR, 0);
++ at91_mci_write(host, AT91_PDC_RNCR, 0);
++ at91_mci_write(host, AT91_PDC_TPR, 0);
++ at91_mci_write(host, AT91_PDC_TCR, 0);
++ at91_mci_write(host, AT91_PDC_TNPR, 0);
++ at91_mci_write(host, AT91_PDC_TNCR, 0);
+
+- at91_mci_write(AT91_MCI_ARGR, cmd->arg);
+- at91_mci_write(AT91_MCI_CMDR, cmdr);
++ at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
++ at91_mci_write(host, AT91_MCI_CMDR, cmdr);
+ return AT91_MCI_CMDRDY;
+ }
+
+- mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; /* zero block length and PDC mode */
+- at91_mci_write(AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
++ mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; /* zero block length and PDC mode */
++ at91_mci_write(host, AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
+
+ /*
+ * Disable the PDC controller
+ */
+- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
++ at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
+
+ if (cmdr & AT91_MCI_TRCMD_START) {
+ data->bytes_xfered = 0;
+@@ -478,15 +450,15 @@
+ */
+ host->total_length = block_length * blocks;
+ host->buffer = dma_alloc_coherent(NULL,
+- host->total_length,
+- &host->physical_address, GFP_KERNEL);
++ host->total_length,
++ &host->physical_address, GFP_KERNEL);
+
+ at91mci_sg_to_dma(host, data);
+
+ pr_debug("Transmitting %d bytes\n", host->total_length);
+
+- at91_mci_write(AT91_PDC_TPR, host->physical_address);
+- at91_mci_write(AT91_PDC_TCR, host->total_length / 4);
++ at91_mci_write(host, AT91_PDC_TPR, host->physical_address);
++ at91_mci_write(host, AT91_PDC_TCR, host->total_length / 4);
+ ier = AT91_MCI_TXBUFE;
+ }
+ }
+@@ -496,14 +468,14 @@
+ * the data sheet says
+ */
+
+- at91_mci_write(AT91_MCI_ARGR, cmd->arg);
+- at91_mci_write(AT91_MCI_CMDR, cmdr);
++ at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
++ at91_mci_write(host, AT91_MCI_CMDR, cmdr);
+
+ if (cmdr & AT91_MCI_TRCMD_START) {
+ if (cmdr & AT91_MCI_TRDIR)
+- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
++ at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTEN);
+ else
+- at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
++ at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_TXTEN);
+ }
+ return ier;
+ }
+@@ -520,7 +492,7 @@
+ pr_debug("setting ier to %08X\n", ier);
+
+ /* Stop on errors or the required value */
+- at91_mci_write(AT91_MCI_IER, 0xffff0000 | ier);
++ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
+ }
+
+ /*
+@@ -548,26 +520,24 @@
+ struct mmc_command *cmd = host->cmd;
+ unsigned int status;
+
+- at91_mci_write(AT91_MCI_IDR, 0xffffffff);
++ at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
+
+- cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
+- cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
+- cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
+- cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
++ cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
++ cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
++ cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
++ cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
+
+ if (host->buffer) {
+ dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
+ host->buffer = NULL;
+ }
+
+- status = at91_mci_read(AT91_MCI_SR);
++ status = at91_mci_read(host, AT91_MCI_SR);
+
+ pr_debug("Status = %08X [%08X %08X %08X %08X]\n",
+ status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+
+- if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE |
+- AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE |
+- AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) {
++ if (status & AT91_MCI_ERRORS) {
+ if ((status & AT91_MCI_RCRCE) &&
+ ((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) {
+ cmd->error = MMC_ERR_NONE;
+@@ -605,24 +575,50 @@
+ }
+
+ /*
++ * Handle transmitted data
++ */
++static void at91_mci_handle_transmitted(struct at91mci_host *host)
++{
++ struct mmc_command *cmd;
++ struct mmc_data *data;
++
++ pr_debug("Handling the transmit\n");
++
++ /* Disable the transfer */
++ at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
++
++ /* Now wait for cmd ready */
++ at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
++ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
++
++ cmd = host->cmd;
++ if (!cmd) return;
++
++ data = cmd->data;
++ if (!data) return;
++
++ data->bytes_xfered = host->total_length;
++}
++
++/*
+ * Set the IOS
+ */
+ static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ {
+ int clkdiv;
+ struct at91mci_host *host = mmc_priv(mmc);
+- unsigned long at91_master_clock = clk_get_rate(mci_clk);
++ unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
+
+ host->bus_mode = ios->bus_mode;
+
+ if (ios->clock == 0) {
+ /* Disable the MCI controller */
+- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
++ at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
+ clkdiv = 0;
+ }
+ else {
+ /* Enable the MCI controller */
+- at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
++ at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
+
+ if ((at91_master_clock % (ios->clock * 2)) == 0)
+ clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
+@@ -634,25 +630,25 @@
+ }
+ if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
+ pr_debug("MMC: Setting controller bus width to 4\n");
+- at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
++ at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
+ }
+ else {
+ pr_debug("MMC: Setting controller bus width to 1\n");
+- at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
++ at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
+ }
+
+ /* Set the clock divider */
+- at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
++ at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
+
+ /* maybe switch power to the card */
+ if (host->board->vcc_pin) {
+ switch (ios->power_mode) {
+ case MMC_POWER_OFF:
+- at91_set_gpio_output(host->board->vcc_pin, 0);
++ at91_set_gpio_value(host->board->vcc_pin, 0);
+ break;
+ case MMC_POWER_UP:
+ case MMC_POWER_ON:
+- at91_set_gpio_output(host->board->vcc_pin, 1);
++ at91_set_gpio_value(host->board->vcc_pin, 1);
+ break;
+ }
+ }
+@@ -665,39 +661,40 @@
+ {
+ struct at91mci_host *host = devid;
+ int completed = 0;
++ unsigned int int_status, int_mask;
+
+- unsigned int int_status;
++ int_status = at91_mci_read(host, AT91_MCI_SR);
++ int_mask = at91_mci_read(host, AT91_MCI_IMR);
+
+- int_status = at91_mci_read(AT91_MCI_SR);
+- pr_debug("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR),
+- int_status & at91_mci_read(AT91_MCI_IMR));
+-
+- if ((int_status & at91_mci_read(AT91_MCI_IMR)) & 0xffff0000)
+- completed = 1;
++ pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
++ int_status & int_mask);
+
+- int_status &= at91_mci_read(AT91_MCI_IMR);
++ int_status = int_status & int_mask;
+
+- if (int_status & AT91_MCI_UNRE)
+- pr_debug("MMC: Underrun error\n");
+- if (int_status & AT91_MCI_OVRE)
+- pr_debug("MMC: Overrun error\n");
+- if (int_status & AT91_MCI_DTOE)
+- pr_debug("MMC: Data timeout\n");
+- if (int_status & AT91_MCI_DCRCE)
+- pr_debug("MMC: CRC error in data\n");
+- if (int_status & AT91_MCI_RTOE)
+- pr_debug("MMC: Response timeout\n");
+- if (int_status & AT91_MCI_RENDE)
+- pr_debug("MMC: Response end bit error\n");
+- if (int_status & AT91_MCI_RCRCE)
+- pr_debug("MMC: Response CRC error\n");
+- if (int_status & AT91_MCI_RDIRE)
+- pr_debug("MMC: Response direction error\n");
+- if (int_status & AT91_MCI_RINDE)
+- pr_debug("MMC: Response index error\n");
++ if (int_status & AT91_MCI_ERRORS) {
++ completed = 1;
++
++ if (int_status & AT91_MCI_UNRE)
++ pr_debug("MMC: Underrun error\n");
++ if (int_status & AT91_MCI_OVRE)
++ pr_debug("MMC: Overrun error\n");
++ if (int_status & AT91_MCI_DTOE)
++ pr_debug("MMC: Data timeout\n");
++ if (int_status & AT91_MCI_DCRCE)
++ pr_debug("MMC: CRC error in data\n");
++ if (int_status & AT91_MCI_RTOE)
++ pr_debug("MMC: Response timeout\n");
++ if (int_status & AT91_MCI_RENDE)
++ pr_debug("MMC: Response end bit error\n");
++ if (int_status & AT91_MCI_RCRCE)
++ pr_debug("MMC: Response CRC error\n");
++ if (int_status & AT91_MCI_RDIRE)
++ pr_debug("MMC: Response direction error\n");
++ if (int_status & AT91_MCI_RINDE)
++ pr_debug("MMC: Response index error\n");
++ } else {
++ /* Only continue processing if no errors */
+
+- /* Only continue processing if no errors */
+- if (!completed) {
+ if (int_status & AT91_MCI_TXBUFE) {
+ pr_debug("TX buffer empty\n");
+ at91_mci_handle_transmitted(host);
+@@ -705,12 +702,11 @@
+
+ if (int_status & AT91_MCI_RXBUFF) {
+ pr_debug("RX buffer full\n");
+- at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
++ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);
+ }
+
+- if (int_status & AT91_MCI_ENDTX) {
++ if (int_status & AT91_MCI_ENDTX)
+ pr_debug("Transmit has ended\n");
+- }
+
+ if (int_status & AT91_MCI_ENDRX) {
+ pr_debug("Receive has ended\n");
+@@ -719,37 +715,33 @@
+
+ if (int_status & AT91_MCI_NOTBUSY) {
+ pr_debug("Card is ready\n");
+- at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
++ at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);
+ }
+
+- if (int_status & AT91_MCI_DTIP) {
++ if (int_status & AT91_MCI_DTIP)
+ pr_debug("Data transfer in progress\n");
+- }
+
+- if (int_status & AT91_MCI_BLKE) {
++ if (int_status & AT91_MCI_BLKE)
+ pr_debug("Block transfer has ended\n");
+- }
+
+- if (int_status & AT91_MCI_TXRDY) {
++ if (int_status & AT91_MCI_TXRDY)
+ pr_debug("Ready to transmit\n");
+- }
+
+- if (int_status & AT91_MCI_RXRDY) {
++ if (int_status & AT91_MCI_RXRDY)
+ pr_debug("Ready to receive\n");
+- }
+
+ if (int_status & AT91_MCI_CMDRDY) {
+ pr_debug("Command ready\n");
+ completed = 1;
+ }
+ }
+- at91_mci_write(AT91_MCI_IDR, int_status);
+
+ if (completed) {
+ pr_debug("Completed command\n");
+- at91_mci_write(AT91_MCI_IDR, 0xffffffff);
++ at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
+ at91mci_completed_command(host);
+- }
++ } else
++ at91_mci_write(host, AT91_MCI_IDR, int_status);
+
+ return IRQ_HANDLED;
+ }
+@@ -769,7 +761,7 @@
+ present ? "insert" : "remove");
+ if (!present) {
+ pr_debug("****** Resetting SD-card bus width ******\n");
+- at91_mci_write(AT91_MCI_SDCR, 0);
++ at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
+ }
+ mmc_detect_change(host->mmc, msecs_to_jiffies(100));
+ }
+@@ -806,15 +798,22 @@
+ {
+ struct mmc_host *mmc;
+ struct at91mci_host *host;
++ struct resource *res;
+ int ret;
+
+ pr_debug("Probe MCI devices\n");
+- at91_mci_disable();
+- at91_mci_enable();
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENXIO;
++
++ if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME))
++ return -EBUSY;
+
+ mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
+ if (!mmc) {
+ pr_debug("Failed to allocate mmc host\n");
++ release_mem_region(res->start, res->end - res->start + 1);
+ return -ENOMEM;
+ }
+
+@@ -822,7 +821,7 @@
+ mmc->f_min = 375000;
+ mmc->f_max = 25000000;
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+- mmc->caps = MMC_CAP_BYTEBLOCK;
++ mmc->caps = MMC_CAP_BYTEBLOCK | MMC_CAP_MULTIWRITE;
+
+ host = mmc_priv(mmc);
+ host->mmc = mmc;
+@@ -833,29 +832,50 @@
+ #ifdef SUPPORT_4WIRE
+ mmc->caps |= MMC_CAP_4_BIT_DATA;
+ #else
+- printk("MMC: 4 wire bus mode not supported by this driver - using 1 wire\n");
++ printk("AT91 MMC: 4 wire bus mode not supported by this driver - using 1 wire\n");
+ #endif
+ }
+
+ /*
+ * Get Clock
+ */
+- mci_clk = clk_get(&pdev->dev, "mci_clk");
+- if (IS_ERR(mci_clk)) {
++ host->mci_clk = clk_get(&pdev->dev, "mci_clk");
++ if (IS_ERR(host->mci_clk)) {
+ printk(KERN_ERR "AT91 MMC: no clock defined.\n");
+ mmc_free_host(mmc);
++ release_mem_region(res->start, res->end - res->start + 1);
+ return -ENODEV;
+ }
+- clk_enable(mci_clk); /* Enable the peripheral clock */
++
++ /*
++ * Map I/O region
++ */
++ host->baseaddr = ioremap(res->start, res->end - res->start + 1);
++ if (!host->baseaddr) {
++ clk_put(host->mci_clk);
++ release_mem_region(res->start, res->end - res->start + 1);
++ mmc_free_host(mmc);
++ return -ENOMEM;
++ }
++
++ /*
++ * Reset hardware
++ */
++ clk_enable(host->mci_clk); /* Enable the peripheral clock */
++ at91_mci_disable(host);
++ at91_mci_enable(host);
+
+ /*
+ * Allocate the MCI interrupt
+ */
+- ret = request_irq(AT91RM9200_ID_MCI, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host);
++ host->irq = platform_get_irq(pdev, 0);
++ ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host);
+ if (ret) {
+- printk(KERN_ERR "Failed to request MCI interrupt\n");
+- clk_disable(mci_clk);
+- clk_put(mci_clk);
++ printk(KERN_ERR "AT91 MMC: Failed to request MCI interrupt\n");
++ clk_disable(host->mci_clk);
++ clk_put(host->mci_clk);
++ iounmap(host->baseaddr);
++ release_mem_region(res->start, res->end - res->start + 1);
+ mmc_free_host(mmc);
+ return ret;
+ }
+@@ -879,10 +899,10 @@
+ ret = request_irq(host->board->det_pin, at91_mmc_det_irq,
+ 0, DRIVER_NAME, host);
+ if (ret)
+- printk(KERN_ERR "couldn't allocate MMC detect irq\n");
++ printk(KERN_ERR "AT91 MMC: Couldn't allocate MMC detect irq\n");
+ }
+
+- pr_debug(KERN_INFO "Added MCI driver\n");
++ pr_debug("Added MCI driver\n");
+
+ return 0;
+ }
+@@ -894,6 +914,7 @@
+ {
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
+ struct at91mci_host *host;
++ struct resource *res;
+
+ if (!mmc)
+ return -1;
+@@ -905,16 +926,19 @@
+ cancel_delayed_work(&host->mmc->detect);
+ }
+
++ at91_mci_disable(host);
+ mmc_remove_host(mmc);
+- at91_mci_disable();
+- free_irq(AT91RM9200_ID_MCI, host);
+- mmc_free_host(mmc);
++ free_irq(host->irq, host);
+
+- clk_disable(mci_clk); /* Disable the peripheral clock */
+- clk_put(mci_clk);
++ iounmap(host->baseaddr);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ release_mem_region(res->start, res->end - res->start + 1);
+
+- platform_set_drvdata(pdev, NULL);
++ clk_disable(host->mci_clk); /* Disable the peripheral clock */
++ clk_put(host->mci_clk);
+
++ mmc_free_host(mmc);
++ platform_set_drvdata(pdev, NULL);
+ pr_debug("MCI Removed\n");
+
+ return 0;
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/devices/Kconfig linux-2.6.19/drivers/mtd/devices/Kconfig
+--- linux-2.6.19-final/drivers/mtd/devices/Kconfig Mon Dec 4 16:40:13 2006
++++ linux-2.6.19/drivers/mtd/devices/Kconfig Wed Nov 22 09:22:03 2006
+@@ -267,5 +267,11 @@
+ LinuxBIOS or if you need to recover a DiskOnChip Millennium on which
+ you have managed to wipe the first block.
+
+-endmenu
++config MTD_AT91_DATAFLASH
++ tristate "AT91RM9200 DataFlash AT45DBxxx (legacy driver)"
++ depends on MTD && ARCH_AT91RM9200 && AT91_SPI
++ help
++ This enables access to the DataFlash (AT45DBxxx) on the AT91RM9200.
++ If you have such a board, say 'Y'.
+
++endmenu
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/devices/Makefile linux-2.6.19/drivers/mtd/devices/Makefile
+--- linux-2.6.19-final/drivers/mtd/devices/Makefile Mon Dec 4 16:33:42 2006
++++ linux-2.6.19/drivers/mtd/devices/Makefile Thu Oct 12 17:07:39 2006
+@@ -17,3 +17,4 @@
+ obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
+ obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
+ obj-$(CONFIG_MTD_M25P80) += m25p80.o
++obj-$(CONFIG_MTD_AT91_DATAFLASH)+= at91_dataflash.o
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/devices/at91_dataflash.c linux-2.6.19/drivers/mtd/devices/at91_dataflash.c
+--- linux-2.6.19-final/drivers/mtd/devices/at91_dataflash.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/mtd/devices/at91_dataflash.c Mon Dec 4 16:12:44 2006
+@@ -0,0 +1,640 @@
++/*
++ * Atmel DataFlash driver for Atmel AT91RM9200 (Thunder)
++ *
++ * Copyright (C) SAN People (Pty) Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++*/
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/pci.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/arch/spi.h>
++
++#undef DEBUG_DATAFLASH
++
++#define DATAFLASH_MAX_DEVICES 4 /* max number of dataflash devices */
++#undef DATAFLASH_ALWAYS_ADD_DEVICE /* always add whole device when using partitions? */
++
++#define OP_READ_CONTINUOUS 0xE8
++#define OP_READ_PAGE 0xD2
++#define OP_READ_BUFFER1 0xD4
++#define OP_READ_BUFFER2 0xD6
++#define OP_READ_STATUS 0xD7
++
++#define OP_ERASE_PAGE 0x81
++#define OP_ERASE_BLOCK 0x50
++
++#define OP_TRANSFER_BUF1 0x53
++#define OP_TRANSFER_BUF2 0x55
++#define OP_COMPARE_BUF1 0x60
++#define OP_COMPARE_BUF2 0x61
++
++#define OP_PROGRAM_VIA_BUF1 0x82
++#define OP_PROGRAM_VIA_BUF2 0x85
++
++struct dataflash_local
++{
++ int spi; /* SPI chip-select number */
++
++ unsigned int page_size; /* number of bytes per page */
++ unsigned short page_offset; /* page offset in flash address */
++};
++
++
++/* Detected DataFlash devices */
++static struct mtd_info* mtd_devices[DATAFLASH_MAX_DEVICES];
++static int nr_devices = 0;
++
++/* ......................................................................... */
++
++#ifdef CONFIG_MTD_PARTITIONS
++
++static struct mtd_partition static_partitions_2M[] =
++{
++ {
++ .name = "bootloader",
++ .offset = 0,
++ .size = 1 * 32 * 8 * 528, /* 1st sector = 32 blocks * 8 pages * 528 bytes */
++ .mask_flags = MTD_WRITEABLE, /* read-only */
++ },
++ {
++ .name = "kernel",
++ .offset = MTDPART_OFS_NXTBLK,
++ .size = 6 * 32 * 8 * 528, /* 6 sectors */
++ },
++ {
++ .name = "filesystem",
++ .offset = MTDPART_OFS_NXTBLK,
++ .size = MTDPART_SIZ_FULL, /* rest = 9 sectors */
++ }
++};
++
++static struct mtd_partition static_partitions_4M[] =
++{
++ {
++ .name = "bootloader",
++ .offset = 0,
++ .size = 1 * 64 * 8 * 528, /* 1st sector = 64 blocks * 8 pages * 528 bytes */
++ .mask_flags = MTD_WRITEABLE, /* read-only */
++ },
++ {
++ .name = "kernel",
++ .offset = MTDPART_OFS_NXTBLK,
++ .size = 4 * 64 * 8 * 528, /* 4 sectors */
++ },
++ {
++ .name = "filesystem",
++ .offset = MTDPART_OFS_NXTBLK,
++ .size = MTDPART_SIZ_FULL, /* rest = 11 sectors */
++ }
++};
++
++#if defined(CONFIG_MACH_KAFA)
++static struct mtd_partition static_partitions_8M[] =
++{
++ {
++ name: "romboot",
++ offset: 0,
++ size: 16 * 1056, /* 160 Kb */
++ mask_flags: MTD_WRITEABLE, /* read-only */
++ },
++ {
++ name: "uboot",
++ offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
++ size: 128 * 1056, /* 1 MB */
++ },
++ {
++ name: "kernel",
++ offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
++ size: 1024 * 1056, /* 1 MB */
++ },
++ {
++ name: "filesystem",
++ offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
++ size: MTDPART_SIZ_FULL,
++ }
++};
++
++#else
++
++static struct mtd_partition static_partitions_8M[] =
++{
++ {
++ .name = "bootloader",
++ .offset = 0,
++ .size = 1 * 32 * 8 * 1056, /* 1st sector = 32 blocks * 8 pages * 1056 bytes */
++ .mask_flags = MTD_WRITEABLE, /* read-only */
++ },
++ {
++ .name = "kernel",
++ .offset = MTDPART_OFS_NXTBLK,
++ .size = 5 * 32 * 8 * 1056, /* 5 sectors */
++ },
++ {
++ .name = "filesystem",
++ .offset = MTDPART_OFS_NXTBLK,
++ .size = MTDPART_SIZ_FULL, /* rest = 26 sectors */
++ }
++};
++#endif
++
++static const char *part_probes[] = { "cmdlinepart", NULL, };
++
++#endif
++
++/* ......................................................................... */
++
++/* Allocate a single SPI transfer descriptor. We're assuming that if multiple
++ SPI transfers occur at the same time, spi_access_bus() will serialize them.
++ If this is not valid, then either (i) each dataflash 'priv' structure
++ needs it's own transfer descriptor, (ii) we lock this one, or (iii) use
++ another mechanism. */
++static struct spi_transfer_list* spi_transfer_desc;
++
++/*
++ * Perform a SPI transfer to access the DataFlash device.
++ */
++static int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len,
++ char* txnext, int txnext_len, char* rxnext, int rxnext_len)
++{
++ struct spi_transfer_list* list = spi_transfer_desc;
++
++ list->tx[0] = tx; list->txlen[0] = tx_len;
++ list->rx[0] = rx; list->rxlen[0] = rx_len;
++
++ list->tx[1] = txnext; list->txlen[1] = txnext_len;
++ list->rx[1] = rxnext; list->rxlen[1] = rxnext_len;
++
++ list->nr_transfers = nr;
++
++ return spi_transfer(list);
++}
++
++/* ......................................................................... */
++
++/*
++ * Poll the DataFlash device until it is READY.
++ */
++static void at91_dataflash_waitready(void)
++{
++ char* command = kmalloc(2, GFP_KERNEL);
++
++ if (!command)
++ return;
++
++ do {
++ command[0] = OP_READ_STATUS;
++ command[1] = 0;
++
++ do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
++ } while ((command[1] & 0x80) == 0);
++
++ kfree(command);
++}
++
++/*
++ * Return the status of the DataFlash device.
++ */
++static unsigned short at91_dataflash_status(void)
++{
++ unsigned short status;
++ char* command = kmalloc(2, GFP_KERNEL);
++
++ if (!command)
++ return 0;
++
++ command[0] = OP_READ_STATUS;
++ command[1] = 0;
++
++ do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
++ status = command[1];
++
++ kfree(command);
++ return status;
++}
++
++/* ......................................................................... */
++
++/*
++ * Erase blocks of flash.
++ */
++static int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
++{
++ struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
++ unsigned int pageaddr;
++ char* command;
++
++#ifdef DEBUG_DATAFLASH
++ printk("dataflash_erase: addr=%i len=%i\n", instr->addr, instr->len);
++#endif
++
++ /* Sanity checks */
++ if (instr->addr + instr->len > mtd->size)
++ return -EINVAL;
++ if ((instr->len % mtd->erasesize != 0) || (instr->len % priv->page_size != 0))
++ return -EINVAL;
++ if ((instr->addr % priv->page_size) != 0)
++ return -EINVAL;
++
++ command = kmalloc(4, GFP_KERNEL);
++ if (!command)
++ return -ENOMEM;
++
++ while (instr->len > 0) {
++ /* Calculate flash page address */
++ pageaddr = (instr->addr / priv->page_size) << priv->page_offset;
++
++ command[0] = OP_ERASE_PAGE;
++ command[1] = (pageaddr & 0x00FF0000) >> 16;
++ command[2] = (pageaddr & 0x0000FF00) >> 8;
++ command[3] = 0;
++#ifdef DEBUG_DATAFLASH
++ printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr);
++#endif
++
++ /* Send command to SPI device */
++ spi_access_bus(priv->spi);
++ do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
++
++ at91_dataflash_waitready(); /* poll status until ready */
++ spi_release_bus(priv->spi);
++
++ instr->addr += priv->page_size; /* next page */
++ instr->len -= priv->page_size;
++ }
++
++ kfree(command);
++
++ /* Inform MTD subsystem that erase is complete */
++ instr->state = MTD_ERASE_DONE;
++ if (instr->callback)
++ instr->callback(instr);
++
++ return 0;
++}
++
++/*
++ * Read from the DataFlash device.
++ * from : Start offset in flash device
++ * len : Amount to read
++ * retlen : About of data actually read
++ * buf : Buffer containing the data
++ */
++static int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
++{
++ struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
++ unsigned int addr;
++ char* command;
++
++#ifdef DEBUG_DATAFLASH
++ printk("dataflash_read: %lli .. %lli\n", from, from+len);
++#endif
++
++ *retlen = 0;
++
++ /* Sanity checks */
++ if (!len)
++ return 0;
++ if (from + len > mtd->size)
++ return -EINVAL;
++
++ /* Calculate flash page/byte address */
++ addr = (((unsigned)from / priv->page_size) << priv->page_offset) + ((unsigned)from % priv->page_size);
++
++ command = kmalloc(8, GFP_KERNEL);
++ if (!command)
++ return -ENOMEM;
++
++ command[0] = OP_READ_CONTINUOUS;
++ command[1] = (addr & 0x00FF0000) >> 16;
++ command[2] = (addr & 0x0000FF00) >> 8;
++ command[3] = (addr & 0x000000FF);
++#ifdef DEBUG_DATAFLASH
++ printk("READ: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
++#endif
++
++ /* Send command to SPI device */
++ spi_access_bus(priv->spi);
++ do_spi_transfer(2, command, 8, command, 8, buf, len, buf, len);
++ spi_release_bus(priv->spi);
++
++ *retlen = len;
++ kfree(command);
++ return 0;
++}
++
++/*
++ * Write to the DataFlash device.
++ * to : Start offset in flash device
++ * len : Amount to write
++ * retlen : Amount of data actually written
++ * buf : Buffer containing the data
++ */
++static int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
++{
++ struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
++ unsigned int pageaddr, addr, offset, writelen;
++ size_t remaining;
++ u_char *writebuf;
++ unsigned short status;
++ int res = 0;
++ char* command;
++ char* tmpbuf = NULL;
++
++#ifdef DEBUG_DATAFLASH
++ printk("dataflash_write: %lli .. %lli\n", to, to+len);
++#endif
++
++ *retlen = 0;
++
++ /* Sanity checks */
++ if (!len)
++ return 0;
++ if (to + len > mtd->size)
++ return -EINVAL;
++
++ command = kmalloc(4, GFP_KERNEL);
++ if (!command)
++ return -ENOMEM;
++
++ pageaddr = ((unsigned)to / priv->page_size);
++ offset = ((unsigned)to % priv->page_size);
++ if (offset + len > priv->page_size)
++ writelen = priv->page_size - offset;
++ else
++ writelen = len;
++ writebuf = (u_char *)buf;
++ remaining = len;
++
++ /* Allocate temporary buffer */
++ tmpbuf = kmalloc(priv->page_size, GFP_KERNEL);
++ if (!tmpbuf) {
++ kfree(command);
++ return -ENOMEM;
++ }
++
++ /* Gain access to the SPI bus */
++ spi_access_bus(priv->spi);
++
++ while (remaining > 0) {
++#ifdef DEBUG_DATAFLASH
++ printk("write @ %i:%i len=%i\n", pageaddr, offset, writelen);
++#endif
++
++ /* (1) Transfer to Buffer1 */
++ if (writelen != priv->page_size) {
++ addr = pageaddr << priv->page_offset;
++ command[0] = OP_TRANSFER_BUF1;
++ command[1] = (addr & 0x00FF0000) >> 16;
++ command[2] = (addr & 0x0000FF00) >> 8;
++ command[3] = 0;
++#ifdef DEBUG_DATAFLASH
++ printk("TRANSFER: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
++#endif
++ do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
++ at91_dataflash_waitready();
++ }
++
++ /* (2) Program via Buffer1 */
++ addr = (pageaddr << priv->page_offset) + offset;
++ command[0] = OP_PROGRAM_VIA_BUF1;
++ command[1] = (addr & 0x00FF0000) >> 16;
++ command[2] = (addr & 0x0000FF00) >> 8;
++ command[3] = (addr & 0x000000FF);
++#ifdef DEBUG_DATAFLASH
++ printk("PROGRAM: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
++#endif
++ do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, tmpbuf, writelen);
++ at91_dataflash_waitready();
++
++ /* (3) Compare to Buffer1 */
++ addr = pageaddr << priv->page_offset;
++ command[0] = OP_COMPARE_BUF1;
++ command[1] = (addr & 0x00FF0000) >> 16;
++ command[2] = (addr & 0x0000FF00) >> 8;
++ command[3] = 0;
++#ifdef DEBUG_DATAFLASH
++ printk("COMPARE: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
++#endif
++ do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
++ at91_dataflash_waitready();
++
++ /* Get result of the compare operation */
++ status = at91_dataflash_status();
++ if ((status & 0x40) == 1) {
++ printk("at91_dataflash: Write error on page %i\n", pageaddr);
++ remaining = 0;
++ res = -EIO;
++ }
++
++ remaining = remaining - writelen;
++ pageaddr++;
++ offset = 0;
++ writebuf += writelen;
++ *retlen += writelen;
++
++ if (remaining > priv->page_size)
++ writelen = priv->page_size;
++ else
++ writelen = remaining;
++ }
++
++ /* Release SPI bus */
++ spi_release_bus(priv->spi);
++
++ kfree(tmpbuf);
++ kfree(command);
++ return res;
++}
++
++/* ......................................................................... */
++
++/*
++ * Initialize and register DataFlash device with MTD subsystem.
++ */
++static int __init add_dataflash(int channel, char *name, int IDsize,
++ int nr_pages, int pagesize, int pageoffset)
++{
++ struct mtd_info *device;
++ struct dataflash_local *priv;
++#ifdef CONFIG_MTD_PARTITIONS
++ struct mtd_partition *mtd_parts = 0;
++ int mtd_parts_nr = 0;
++#endif
++
++ if (nr_devices >= DATAFLASH_MAX_DEVICES) {
++ printk(KERN_ERR "at91_dataflash: Too many devices detected\n");
++ return 0;
++ }
++
++ device = kmalloc(sizeof(struct mtd_info) + strlen(name) + 8, GFP_KERNEL);
++ if (!device)
++ return -ENOMEM;
++ memset(device, 0, sizeof(struct mtd_info));
++
++ device->name = (char *)&device[1];
++ sprintf(device->name, "%s.spi%d", name, channel);
++ device->size = nr_pages * pagesize;
++ device->erasesize = pagesize;
++ device->writesize = pagesize;
++ device->owner = THIS_MODULE;
++ device->type = MTD_DATAFLASH;
++ device->flags = MTD_WRITEABLE;
++ device->erase = at91_dataflash_erase;
++ device->read = at91_dataflash_read;
++ device->write = at91_dataflash_write;
++
++ priv = (struct dataflash_local *) kmalloc(sizeof(struct dataflash_local), GFP_KERNEL);
++ if (!priv) {
++ kfree(device);
++ return -ENOMEM;
++ }
++ memset(priv, 0, sizeof(struct dataflash_local));
++
++ priv->spi = channel;
++ priv->page_size = pagesize;
++ priv->page_offset = pageoffset;
++ device->priv = priv;
++
++ mtd_devices[nr_devices] = device;
++ nr_devices++;
++ printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, device->size);
++
++#ifdef CONFIG_MTD_PARTITIONS
++#ifdef CONFIG_MTD_CMDLINE_PARTS
++ mtd_parts_nr = parse_mtd_partitions(device, part_probes, &mtd_parts, 0);
++#endif
++ if (mtd_parts_nr <= 0) {
++ switch (IDsize) {
++ case SZ_2M:
++ mtd_parts = static_partitions_2M;
++ mtd_parts_nr = ARRAY_SIZE(static_partitions_2M);
++ break;
++ case SZ_4M:
++ mtd_parts = static_partitions_4M;
++ mtd_parts_nr = ARRAY_SIZE(static_partitions_4M);
++ break;
++ case SZ_8M:
++ mtd_parts = static_partitions_8M;
++ mtd_parts_nr = ARRAY_SIZE(static_partitions_8M);
++ break;
++ }
++ }
++
++ if (mtd_parts_nr > 0) {
++#ifdef DATAFLASH_ALWAYS_ADD_DEVICE
++ add_mtd_device(device);
++#endif
++ return add_mtd_partitions(device, mtd_parts, mtd_parts_nr);
++ }
++#endif
++ return add_mtd_device(device); /* add whole device */
++}
++
++/*
++ * Detect and initialize DataFlash device connected to specified SPI channel.
++ *
++ * Device Density ID code Nr Pages Page Size Page offset
++ * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
++ * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1025 264 9
++ * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
++ * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
++ * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
++ * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
++ * AT45DB0642 64Mbit (8M) xx1111xx (0x3c) 8192 1056 11
++ * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
++ */
++static int __init at91_dataflash_detect(int channel)
++{
++ int res = 0;
++ unsigned short status;
++
++ spi_access_bus(channel);
++ status = at91_dataflash_status();
++ spi_release_bus(channel);
++ if (status != 0xff) { /* no dataflash device there */
++ switch (status & 0x3c) {
++ case 0x0c: /* 0 0 1 1 */
++ res = add_dataflash(channel, "AT45DB011B", SZ_128K, 512, 264, 9);
++ break;
++ case 0x14: /* 0 1 0 1 */
++ res = add_dataflash(channel, "AT45DB021B", SZ_256K, 1025, 264, 9);
++ break;
++ case 0x1c: /* 0 1 1 1 */
++ res = add_dataflash(channel, "AT45DB041B", SZ_512K, 2048, 264, 9);
++ break;
++ case 0x24: /* 1 0 0 1 */
++ res = add_dataflash(channel, "AT45DB081B", SZ_1M, 4096, 264, 9);
++ break;
++ case 0x2c: /* 1 0 1 1 */
++ res = add_dataflash(channel, "AT45DB161B", SZ_2M, 4096, 528, 10);
++ break;
++ case 0x34: /* 1 1 0 1 */
++ res = add_dataflash(channel, "AT45DB321B", SZ_4M, 8192, 528, 10);
++ break;
++ case 0x3c: /* 1 1 1 1 */
++ res = add_dataflash(channel, "AT45DB642", SZ_8M, 8192, 1056, 11);
++ break;
++// Currently unsupported since Atmel removed the "Main Memory Program via Buffer" commands.
++// case 0x10: /* 0 1 0 0 */
++// res = add_dataflash(channel, "AT45DB1282", SZ_16M, 16384, 1056, 11);
++// break;
++ default:
++ printk(KERN_ERR "at91_dataflash: Unknown device (%x)\n", status & 0x3c);
++ }
++ }
++
++ return res;
++}
++
++static int __init at91_dataflash_init(void)
++{
++ spi_transfer_desc = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
++ if (!spi_transfer_desc)
++ return -ENOMEM;
++
++ /* DataFlash (SPI chip select 0) */
++ at91_dataflash_detect(0);
++
++#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
++ /* DataFlash card (SPI chip select 3) */
++ at91_dataflash_detect(3);
++#endif
++
++ return 0;
++}
++
++static void __exit at91_dataflash_exit(void)
++{
++ int i;
++
++ for (i = 0; i < DATAFLASH_MAX_DEVICES; i++) {
++ if (mtd_devices[i]) {
++#ifdef CONFIG_MTD_PARTITIONS
++ del_mtd_partitions(mtd_devices[i]);
++#else
++ del_mtd_device(mtd_devices[i]);
++#endif
++ kfree(mtd_devices[i]->priv);
++ kfree(mtd_devices[i]);
++ }
++ }
++ nr_devices = 0;
++ kfree(spi_transfer_desc);
++}
++
++
++module_init(at91_dataflash_init);
++module_exit(at91_dataflash_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Andrew Victor");
++MODULE_DESCRIPTION("DataFlash driver for Atmel AT91RM9200");
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/devices/mtd_dataflash.c linux-2.6.19/drivers/mtd/devices/mtd_dataflash.c
+--- linux-2.6.19-final/drivers/mtd/devices/mtd_dataflash.c Mon Dec 4 16:33:42 2006
++++ linux-2.6.19/drivers/mtd/devices/mtd_dataflash.c Mon Dec 4 16:12:32 2006
+@@ -480,7 +480,7 @@
+ device->writesize = pagesize;
+ device->owner = THIS_MODULE;
+ device->type = MTD_DATAFLASH;
+- device->flags = MTD_CAP_NORFLASH;
++ device->flags = MTD_WRITEABLE;
+ device->erase = dataflash_erase;
+ device->read = dataflash_read;
+ device->write = dataflash_write;
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/maps/Kconfig linux-2.6.19/drivers/mtd/maps/Kconfig
+--- linux-2.6.19-final/drivers/mtd/maps/Kconfig Mon Dec 4 16:40:13 2006
++++ linux-2.6.19/drivers/mtd/maps/Kconfig Mon Nov 20 10:49:27 2006
+@@ -622,5 +622,25 @@
+
+ This selection automatically selects the map_ram driver.
+
++config MTD_CSB337
++ bool "Flash mapped on Cogent CSB337"
++ depends on MTD && MACH_CSB337
++ help
++ This enables access to the flash chip on the Cogent CSB337
++ single board computer. The default behavior of the startup
++ script the comes with BSPs for that board is to pass the address
++ of a file romfs.img, which is assumed to be a romfs filesystem image
++ to be used as the initial root filesystem.
++
++config MTD_CSB637
++ bool "Flash mapped on Cogent CSB637"
++ depends on MTD && MACH_CSB637
++ help
++ This enables access to the flash chip on the Cogent CSB637
++ single board computer. The default behavior of the startup
++ script the comes with BSPs for that board is to pass the address
++ of a file romfs.img, which is assumed to be a romfs filesystem image
++ to be used as the initial root filesystem.
++
+ endmenu
+
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/maps/Makefile linux-2.6.19/drivers/mtd/maps/Makefile
+--- linux-2.6.19-final/drivers/mtd/maps/Makefile Mon Dec 4 16:40:13 2006
++++ linux-2.6.19/drivers/mtd/maps/Makefile Mon Nov 20 10:49:37 2006
+@@ -70,3 +70,5 @@
+ obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
+ obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
+ obj-$(CONFIG_MTD_TQM834x) += tqm834x.o
++obj-$(CONFIG_MTD_CSB337) += csbxxx.o
++obj-$(CONFIG_MTD_CSB637) += csbxxx.o
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/maps/csbxxx.c linux-2.6.19/drivers/mtd/maps/csbxxx.c
+--- linux-2.6.19-final/drivers/mtd/maps/csbxxx.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/mtd/maps/csbxxx.c Tue Oct 24 08:53:30 2006
+@@ -0,0 +1,143 @@
++/*
++ * Map driver for the Cogent CSBxxx boards.
++ *
++ * Author: Bill Gatliff
++ * Copyright: (C) 2005 Bill Gatliff <bgat@billgatliff.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/dma-mapping.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/map.h>
++#include <linux/mtd/partitions.h>
++#include <asm/io.h>
++#include <asm/hardware.h>
++
++#define MTDID "flash00"
++#define MSG_PREFIX "csbxxx: "
++
++#if defined(CONFIG_MACH_CSB337) || defined(CONFIG_MACH_CSB637)
++#define WINDOW_ADDR 0x10000000
++#define WINDOW_SIZE 0x1000000
++#else
++#error TODO: the MTD map you need goes here...
++#endif
++
++/*
++ * default map definition
++ * (generally overridden on the command line)
++ */
++static struct mtd_partition csbxxx_partitions[] = {
++ {
++ .name = "uMON flash",
++ .size = WINDOW_SIZE,
++ .mask_flags = MTD_WRITEABLE /* force read-only */
++ },
++};
++
++static void csbxxx_map_inval_cache(struct map_info *map, unsigned long from, ssize_t len)
++{
++ consistent_sync((char *)map->cached + from, len, DMA_FROM_DEVICE);
++}
++static struct map_info csbxxx_map = {
++ .size = WINDOW_SIZE,
++ .phys = WINDOW_ADDR,
++ .inval_cache = csbxxx_map_inval_cache,
++ .bankwidth = 2,
++ .name = MTDID,
++};
++
++static const char *probes[] = { "cmdlinepart", NULL };
++
++static struct mtd_info *mymtd = 0;
++static int mtd_parts_nb = 0;
++static struct mtd_partition *mtd_parts = 0;
++
++static int __init init_csbxxx(void)
++{
++ int ret = 0;
++ const char *part_type = 0;
++
++ csbxxx_map.virt = ioremap(csbxxx_map.phys, WINDOW_SIZE);
++ if (!csbxxx_map.virt) {
++ printk(KERN_WARNING "Failed to ioremap %s, MTD disabled\n", csbxxx_map.name);
++ ret = -ENOMEM;
++ goto err;
++ }
++ csbxxx_map.cached = ioremap_cached(csbxxx_map.phys, WINDOW_SIZE);
++ if (!csbxxx_map.cached)
++ printk(KERN_WARNING "Failed to ioremap cached %s\n", csbxxx_map.name);
++
++ simple_map_init(&csbxxx_map);
++
++ printk(KERN_NOTICE "Probing %s at physical address 0x%08lx (%d-bit bankwidth)\n",
++ csbxxx_map.name, csbxxx_map.phys, csbxxx_map.bankwidth * 8);
++
++ mymtd = do_map_probe("cfi_probe", &csbxxx_map);
++ if (!mymtd)
++ goto err;
++
++ mymtd->owner = THIS_MODULE;
++
++ mtd_parts_nb = parse_mtd_partitions(mymtd, probes, &mtd_parts, 0);
++
++#ifdef CONFIG_MTD_PARTITIONS
++ if (mtd_parts_nb > 0)
++ part_type = "command line";
++ else if (mtd_parts_nb == 0) {
++ mtd_parts = csbxxx_partitions;
++ mtd_parts_nb = ARRAY_SIZE(csbxxx_partitions);
++ part_type = "static";
++ }
++ else
++ goto err;
++
++ if (mtd_parts_nb == 0)
++ printk(KERN_NOTICE MSG_PREFIX "no partition info available\n");
++ else {
++ printk(KERN_NOTICE MSG_PREFIX "using %s partition definition\n", part_type);
++ add_mtd_partitions(mymtd, mtd_parts, mtd_parts_nb);
++ }
++#else
++ add_mtd_device(mymtd);
++#endif
++
++ return 0;
++
++err:
++ if (csbxxx_map.virt)
++ iounmap(csbxxx_map.virt);
++ if (csbxxx_map.cached)
++ iounmap(csbxxx_map.cached);
++ if (!ret)
++ ret = -EIO;
++
++ return ret;
++}
++
++static void __exit cleanup_csbxxx(void)
++{
++ if (!mymtd)
++ return;
++
++ del_mtd_partitions(mymtd);
++
++ map_destroy(mymtd);
++ iounmap((void *)csbxxx_map.virt);
++ if (csbxxx_map.cached)
++ iounmap(csbxxx_map.cached);
++}
++
++module_init(init_csbxxx);
++module_exit(cleanup_csbxxx);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Bill Gatliff <bgat@billgatliff.com>");
++MODULE_DESCRIPTION("MTD map driver for Cogent CSBXXX");
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/nand/Kconfig linux-2.6.19/drivers/mtd/nand/Kconfig
+--- linux-2.6.19-final/drivers/mtd/nand/Kconfig Mon Dec 4 16:40:13 2006
++++ linux-2.6.19/drivers/mtd/nand/Kconfig Thu Oct 12 17:07:39 2006
+@@ -232,6 +232,13 @@
+
+ If you say "m", the module will be called "cs553x_nand.ko".
+
++config MTD_NAND_AT91
++ bool "Support for NAND Flash / SmartMedia on AT91"
++ depends on MTD_NAND && ARCH_AT91
++ help
++ Enables support for NAND Flash / Smart Media Card interface
++ on Atmel AT91 processors.
++
+ config MTD_NAND_NANDSIM
+ tristate "Support for NAND Flash Simulator"
+ depends on MTD_NAND && MTD_PARTITIONS
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/nand/Makefile linux-2.6.19/drivers/mtd/nand/Makefile
+--- linux-2.6.19-final/drivers/mtd/nand/Makefile Mon Dec 4 16:33:43 2006
++++ linux-2.6.19/drivers/mtd/nand/Makefile Thu Oct 12 17:07:39 2006
+@@ -22,5 +22,6 @@
+ obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
+ obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
+ obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
++obj-$(CONFIG_MTD_NAND_AT91) += at91_nand.o
+
+ nand-objs = nand_base.o nand_bbt.o
+diff -urN -x CVS linux-2.6.19-final/drivers/mtd/nand/at91_nand.c linux-2.6.19/drivers/mtd/nand/at91_nand.c
+--- linux-2.6.19-final/drivers/mtd/nand/at91_nand.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/mtd/nand/at91_nand.c Wed Nov 15 08:12:22 2006
+@@ -0,0 +1,223 @@
++/*
++ * drivers/mtd/nand/at91_nand.c
++ *
++ * Copyright (C) 2003 Rick Bronson
++ *
++ * Derived from drivers/mtd/nand/autcpu12.c
++ * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
++ *
++ * Derived from drivers/mtd/spia.c
++ * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/io.h>
++#include <asm/sizes.h>
++
++#include <asm/hardware.h>
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++
++struct at91_nand_host {
++ struct nand_chip nand_chip;
++ struct mtd_info mtd;
++ void __iomem *io_base;
++ struct at91_nand_data *board;
++};
++
++/*
++ * Hardware specific access to control-lines
++ */
++static void at91_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
++{
++ struct nand_chip *nand_chip = mtd->priv;
++ struct at91_nand_host *host = nand_chip->priv;
++
++ if (cmd == NAND_CMD_NONE)
++ return;
++
++ if (ctrl & NAND_CLE)
++ writeb(cmd, host->io_base + (1 << host->board->cle));
++ else
++ writeb(cmd, host->io_base + (1 << host->board->ale));
++}
++
++/*
++ * Read the Device Ready pin.
++ */
++static int at91_nand_device_ready(struct mtd_info *mtd)
++{
++ struct nand_chip *nand_chip = mtd->priv;
++ struct at91_nand_host *host = nand_chip->priv;
++
++ return at91_get_gpio_value(host->board->rdy_pin);
++}
++
++/*
++ * Enable NAND.
++ */
++static void at91_nand_enable(struct at91_nand_host *host)
++{
++ if (host->board->enable_pin)
++ at91_set_gpio_value(host->board->enable_pin, 0);
++}
++
++/*
++ * Disable NAND.
++ */
++static void at91_nand_disable(struct at91_nand_host *host)
++{
++ if (host->board->enable_pin)
++ at91_set_gpio_value(host->board->enable_pin, 1);
++}
++
++/*
++ * Probe for the NAND device.
++ */
++static int __init at91_nand_probe(struct platform_device *pdev)
++{
++ struct at91_nand_host *host;
++ struct mtd_info *mtd;
++ struct nand_chip *nand_chip;
++ int res;
++
++#ifdef CONFIG_MTD_PARTITIONS
++ struct mtd_partition *partitions = NULL;
++ int num_partitions = 0;
++#endif
++
++ /* Allocate memory for the device structure (and zero it) */
++ host = kzalloc(sizeof(struct at91_nand_host), GFP_KERNEL);
++ if (!host) {
++ printk(KERN_ERR "at91_nand: failed to allocate device structure.\n");
++ return -ENOMEM;
++ }
++
++ host->io_base = ioremap(pdev->resource[0].start,
++ pdev->resource[0].end - pdev->resource[0].start + 1);
++ if (host->io_base == NULL) {
++ printk(KERN_ERR "at91_nand: ioremap failed\n");
++ kfree(host);
++ return -EIO;
++ }
++
++ mtd = &host->mtd;
++ nand_chip = &host->nand_chip;
++ host->board = pdev->dev.platform_data;
++
++ nand_chip->priv = host; /* link the private data structures */
++ mtd->priv = nand_chip;
++ mtd->owner = THIS_MODULE;
++
++ /* Set address of NAND IO lines */
++ nand_chip->IO_ADDR_R = host->io_base;
++ nand_chip->IO_ADDR_W = host->io_base;
++ nand_chip->cmd_ctrl = at91_nand_cmd_ctrl;
++ nand_chip->dev_ready = at91_nand_device_ready;
++ nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
++ nand_chip->chip_delay = 20; /* 20us command delay time */
++
++ if (host->board->bus_width_16) /* 16-bit bus width */
++ nand_chip->options |= NAND_BUSWIDTH_16;
++
++ platform_set_drvdata(pdev, host);
++ at91_nand_enable(host);
++
++ if (host->board->det_pin) {
++ if (at91_get_gpio_value(host->board->det_pin)) {
++ printk ("No SmartMedia card inserted.\n");
++ res = ENXIO;
++ goto out;
++ }
++ }
++
++ /* Scan to find existance of the device */
++ if (nand_scan(mtd, 1)) {
++ res = -ENXIO;
++ goto out;
++ }
++
++#ifdef CONFIG_MTD_PARTITIONS
++ if (host->board->partition_info)
++ partitions = host->board->partition_info(mtd->size, &num_partitions);
++
++ if ((!partitions) || (num_partitions == 0)) {
++ printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n");
++ res = ENXIO;
++ goto release;
++ }
++
++ res = add_mtd_partitions(mtd, partitions, num_partitions);
++#else
++ res = add_mtd_device(mtd);
++#endif
++
++ if (!res)
++ return res;
++
++release:
++ nand_release(mtd);
++out:
++ at91_nand_disable(host);
++ platform_set_drvdata(pdev, NULL);
++ iounmap(host->io_base);
++ kfree(host);
++ return res;
++}
++
++/*
++ * Remove a NAND device.
++ */
++static int __devexit at91_nand_remove(struct platform_device *pdev)
++{
++ struct at91_nand_host *host = platform_get_drvdata(pdev);
++ struct mtd_info *mtd = &host->mtd;
++
++ nand_release(mtd);
++
++ at91_nand_disable(host);
++
++ iounmap(host->io_base);
++ kfree(host);
++
++ return 0;
++}
++
++static struct platform_driver at91_nand_driver = {
++ .probe = at91_nand_probe,
++ .remove = at91_nand_remove,
++ .driver = {
++ .name = "at91_nand",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init at91_nand_init(void)
++{
++ return platform_driver_register(&at91_nand_driver);
++}
++
++
++static void __exit at91_nand_exit(void)
++{
++ platform_driver_unregister(&at91_nand_driver);
++}
++
++
++module_init(at91_nand_init);
++module_exit(at91_nand_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Rick Bronson");
++MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91RM9200");
+diff -urN -x CVS linux-2.6.19-final/drivers/net/arm/at91_ether.c linux-2.6.19/drivers/net/arm/at91_ether.c
+--- linux-2.6.19-final/drivers/net/arm/at91_ether.c Mon Dec 4 16:40:14 2006
++++ linux-2.6.19/drivers/net/arm/at91_ether.c Thu Nov 23 15:50:12 2006
+@@ -41,9 +41,6 @@
+ #define DRV_NAME "at91_ether"
+ #define DRV_VERSION "1.0"
+
+-static struct net_device *at91_dev;
+-
+-static struct timer_list check_timer;
+ #define LINK_POLL_INTERVAL (HZ)
+
+ /* ..................................................................... */
+@@ -252,8 +249,8 @@
+ * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
+ * or board does not have it connected.
+ */
+- check_timer.expires = jiffies + LINK_POLL_INTERVAL;
+- add_timer(&check_timer);
++ lp->check_timer.expires = jiffies + LINK_POLL_INTERVAL;
++ add_timer(&lp->check_timer);
+ return;
+ }
+
+@@ -300,7 +297,7 @@
+
+ irq_number = lp->board_data.phy_irq_pin;
+ if (!irq_number) {
+- del_timer_sync(&check_timer);
++ del_timer_sync(&lp->check_timer);
+ return;
+ }
+
+@@ -362,13 +359,14 @@
+ static void at91ether_check_link(unsigned long dev_id)
+ {
+ struct net_device *dev = (struct net_device *) dev_id;
++ struct at91_private *lp = (struct at91_private *) dev->priv;
+
+ enable_mdi();
+ update_linkspeed(dev, 1);
+ disable_mdi();
+
+- check_timer.expires = jiffies + LINK_POLL_INTERVAL;
+- add_timer(&check_timer);
++ lp->check_timer.expires = jiffies + LINK_POLL_INTERVAL;
++ add_timer(&lp->check_timer);
+ }
+
+ /* ......................... ADDRESS MANAGEMENT ........................ */
+@@ -857,14 +855,13 @@
+ while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
+ p_recv = dlist->recv_buf[lp->rxBuffIndex];
+ pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
+- skb = alloc_skb(pktlen + 2, GFP_ATOMIC);
++ skb = dev_alloc_skb(pktlen + 2);
+ if (skb != NULL) {
+ skb_reserve(skb, 2);
+ memcpy(skb_put(skb, pktlen), p_recv, pktlen);
+
+ skb->dev = dev;
+ skb->protocol = eth_type_trans(skb, dev);
+- skb->len = pktlen;
+ dev->last_rx = jiffies;
+ lp->stats.rx_bytes += pktlen;
+ netif_rx(skb);
+@@ -927,27 +924,43 @@
+ return IRQ_HANDLED;
+ }
+
++#ifdef CONFIG_NET_POLL_CONTROLLER
++static void at91ether_poll_controller(struct net_device *dev)
++{
++ unsigned long flags;
++
++ local_irq_save(flags);
++ at91ether_interrupt(dev->irq, dev, NULL);
++ local_irq_restore(flags);
++}
++#endif
++
+ /*
+ * Initialize the ethernet interface
+ */
+ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
+ struct platform_device *pdev, struct clk *ether_clk)
+ {
+- struct at91_eth_data *board_data = pdev->dev.platform_data;
++ struct eth_platform_data *board_data = pdev->dev.platform_data;
+ struct net_device *dev;
+ struct at91_private *lp;
+ unsigned int val;
+- int res;
+-
+- if (at91_dev) /* already initialized */
+- return 0;
++ struct resource *res;
++ int ret;
+
+ dev = alloc_etherdev(sizeof(struct at91_private));
+ if (!dev)
+ return -ENOMEM;
+
+- dev->base_addr = AT91_VA_BASE_EMAC;
+- dev->irq = AT91RM9200_ID_EMAC;
++ /* Get I/O base address and IRQ */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ free_netdev(dev);
++ return -ENODEV;
++ }
++ dev->base_addr = res->start;
++ dev->irq = platform_get_irq(pdev, 0);
++
+ SET_MODULE_OWNER(dev);
+
+ /* Install the interrupt handler */
+@@ -979,6 +992,9 @@
+ dev->set_mac_address = set_mac_address;
+ dev->ethtool_ops = &at91ether_ethtool_ops;
+ dev->do_ioctl = at91ether_ioctl;
++#ifdef CONFIG_NET_POLL_CONTROLLER
++ dev->poll_controller = at91ether_poll_controller;
++#endif
+
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+@@ -1017,14 +1033,13 @@
+ lp->phy_address = phy_address; /* MDI address of PHY */
+
+ /* Register the network interface */
+- res = register_netdev(dev);
+- if (res) {
++ ret = register_netdev(dev);
++ if (ret) {
+ free_irq(dev->irq, dev);
+ free_netdev(dev);
+ dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
+- return res;
++ return ret;
+ }
+- at91_dev = dev;
+
+ /* Determine current link speed */
+ spin_lock_irq(&lp->lock);
+@@ -1036,9 +1051,9 @@
+
+ /* If board has no PHY IRQ, use a timer to poll the PHY */
+ if (!lp->board_data.phy_irq_pin) {
+- init_timer(&check_timer);
+- check_timer.data = (unsigned long)dev;
+- check_timer.function = at91ether_check_link;
++ init_timer(&lp->check_timer);
++ lp->check_timer.data = (unsigned long)dev;
++ lp->check_timer.function = at91ether_check_link;
+ }
+
+ /* Display ethernet banner */
+@@ -1115,15 +1130,16 @@
+
+ static int __devexit at91ether_remove(struct platform_device *pdev)
+ {
+- struct at91_private *lp = (struct at91_private *) at91_dev->priv;
++ struct net_device *dev = platform_get_drvdata(pdev);
++ struct at91_private *lp = (struct at91_private *) dev->priv;
+
+- unregister_netdev(at91_dev);
+- free_irq(at91_dev->irq, at91_dev);
++ unregister_netdev(dev);
++ free_irq(dev->irq, dev);
+ dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
+ clk_put(lp->ether_clk);
+
+- free_netdev(at91_dev);
+- at91_dev = NULL;
++ platform_set_drvdata(pdev, NULL);
++ free_netdev(dev);
+ return 0;
+ }
+
+@@ -1131,8 +1147,8 @@
+
+ static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
+ {
+- struct at91_private *lp = (struct at91_private *) at91_dev->priv;
+ struct net_device *net_dev = platform_get_drvdata(pdev);
++ struct at91_private *lp = (struct at91_private *) net_dev->priv;
+ int phy_irq = lp->board_data.phy_irq_pin;
+
+ if (netif_running(net_dev)) {
+@@ -1149,8 +1165,8 @@
+
+ static int at91ether_resume(struct platform_device *pdev)
+ {
+- struct at91_private *lp = (struct at91_private *) at91_dev->priv;
+ struct net_device *net_dev = platform_get_drvdata(pdev);
++ struct at91_private *lp = (struct at91_private *) net_dev->priv;
+ int phy_irq = lp->board_data.phy_irq_pin;
+
+ if (netif_running(net_dev)) {
+diff -urN -x CVS linux-2.6.19-final/drivers/net/arm/at91_ether.h linux-2.6.19/drivers/net/arm/at91_ether.h
+--- linux-2.6.19-final/drivers/net/arm/at91_ether.h Mon Dec 4 16:33:44 2006
++++ linux-2.6.19/drivers/net/arm/at91_ether.h Thu Nov 23 15:50:12 2006
+@@ -79,7 +79,7 @@
+ {
+ struct net_device_stats stats;
+ struct mii_if_info mii; /* ethtool support */
+- struct at91_eth_data board_data; /* board-specific configuration */
++ struct eth_platform_data board_data; /* board-specific configuration */
+ struct clk *ether_clk; /* clock */
+
+ /* PHY */
+@@ -87,6 +87,7 @@
+ spinlock_t lock; /* lock for MDI interface */
+ short phy_media; /* media interface type */
+ unsigned short phy_address; /* 5-bit MDI address of PHY (0..31) */
++ struct timer_list check_timer; /* Poll link status */
+
+ /* Transmit */
+ struct sk_buff *skb; /* holds skb until xmit interrupt completes */
+diff -urN -x CVS linux-2.6.19-final/drivers/pcmcia/at91_cf.c linux-2.6.19/drivers/pcmcia/at91_cf.c
+--- linux-2.6.19-final/drivers/pcmcia/at91_cf.c Mon Dec 4 16:40:25 2006
++++ linux-2.6.19/drivers/pcmcia/at91_cf.c Thu Nov 16 17:27:11 2006
+@@ -23,19 +23,20 @@
+ #include <asm/io.h>
+ #include <asm/sizes.h>
+
+-#include <asm/arch/at91rm9200.h>
+ #include <asm/arch/board.h>
+ #include <asm/arch/gpio.h>
++#include <asm/arch/at91rm9200_mc.h>
+
+
+ /*
+ * A0..A10 work in each range; A23 indicates I/O space; A25 is CFRNW;
+ * some other bit in {A24,A22..A11} is nREG to flag memory access
+ * (vs attributes). So more than 2KB/region would just be waste.
++ * Note: These are offsets from the physical base address.
+ */
+-#define CF_ATTR_PHYS (AT91_CF_BASE)
+-#define CF_IO_PHYS (AT91_CF_BASE + (1 << 23))
+-#define CF_MEM_PHYS (AT91_CF_BASE + 0x017ff800)
++#define CF_ATTR_PHYS (0)
++#define CF_IO_PHYS (1 << 23)
++#define CF_MEM_PHYS (0x017ff800)
+
+ /*--------------------------------------------------------------------------*/
+
+@@ -48,6 +49,8 @@
+
+ struct platform_device *pdev;
+ struct at91_cf_data *board;
++
++ unsigned long phys_baseaddr;
+ };
+
+ #define SZ_2K (2 * SZ_1K)
+@@ -154,9 +157,8 @@
+
+ /*
+ * Use 16 bit accesses unless/until we need 8-bit i/o space.
+- * Always set CSR4 ... PCMCIA won't always unmap things.
+ */
+- csr = at91_sys_read(AT91_SMC_CSR(4)) & ~AT91_SMC_DBW;
++ csr = at91_sys_read(AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
+
+ /*
+ * NOTE: this CF controller ignores IOIS16, so we can't really do
+@@ -168,14 +170,14 @@
+ * some cards only like that way to get at the odd byte, despite
+ * CF 3.0 spec table 35 also giving the D8-D15 option.
+ */
+- if (!(io->flags & (MAP_16BIT|MAP_AUTOSZ))) {
++ if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) {
+ csr |= AT91_SMC_DBW_8;
+ pr_debug("%s: 8bit i/o bus\n", driver_name);
+ } else {
+ csr |= AT91_SMC_DBW_16;
+ pr_debug("%s: 16bit i/o bus\n", driver_name);
+ }
+- at91_sys_write(AT91_SMC_CSR(4), csr);
++ at91_sys_write(AT91_SMC_CSR(cf->board->chipselect), csr);
+
+ io->start = cf->socket.io_offset;
+ io->stop = io->start + SZ_2K - 1;
+@@ -194,11 +196,11 @@
+
+ cf = container_of(s, struct at91_cf_socket, socket);
+
+- map->flags &= MAP_ACTIVE|MAP_ATTRIB|MAP_16BIT;
++ map->flags &= (MAP_ACTIVE | MAP_ATTRIB | MAP_16BIT);
+ if (map->flags & MAP_ATTRIB)
+- map->static_start = CF_ATTR_PHYS;
++ map->static_start = cf->phys_baseaddr + CF_ATTR_PHYS;
+ else
+- map->static_start = CF_MEM_PHYS;
++ map->static_start = cf->phys_baseaddr + CF_MEM_PHYS;
+
+ return 0;
+ }
+@@ -219,7 +221,6 @@
+ struct at91_cf_socket *cf;
+ struct at91_cf_data *board = pdev->dev.platform_data;
+ struct resource *io;
+- unsigned int csa;
+ int status;
+
+ if (!board || !board->det_pin || !board->rst_pin)
+@@ -235,33 +236,11 @@
+
+ cf->board = board;
+ cf->pdev = pdev;
++ cf->phys_baseaddr = io->start;
+ platform_set_drvdata(pdev, cf);
+
+- /* CF takes over CS4, CS5, CS6 */
+- csa = at91_sys_read(AT91_EBI_CSA);
+- at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
+-
+- /* nWAIT is _not_ a default setting */
+- (void) at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
+-
+- /*
+- * Static memory controller timing adjustments.
+- * REVISIT: these timings are in terms of MCK cycles, so
+- * when MCK changes (cpufreq etc) so must these values...
+- */
+- at91_sys_write(AT91_SMC_CSR(4),
+- AT91_SMC_ACSS_STD
+- | AT91_SMC_DBW_16
+- | AT91_SMC_BAT
+- | AT91_SMC_WSEN
+- | AT91_SMC_NWS_(32) /* wait states */
+- | AT91_SMC_RWSETUP_(6) /* setup time */
+- | AT91_SMC_RWHOLD_(4) /* hold time */
+- );
+-
+ /* must be a GPIO; ergo must trigger on both edges */
+- status = request_irq(board->det_pin, at91_cf_irq,
+- IRQF_SAMPLE_RANDOM, driver_name, cf);
++ status = request_irq(board->det_pin, at91_cf_irq, 0, driver_name, cf);
+ if (status < 0)
+ goto fail0;
+ device_init_wakeup(&pdev->dev, 1);
+@@ -282,14 +261,18 @@
+ cf->socket.pci_irq = NR_IRQS + 1;
+
+ /* pcmcia layer only remaps "real" memory not iospace */
+- cf->socket.io_offset = (unsigned long) ioremap(CF_IO_PHYS, SZ_2K);
+- if (!cf->socket.io_offset)
++ cf->socket.io_offset = (unsigned long) ioremap(cf->phys_baseaddr + CF_IO_PHYS, SZ_2K);
++ if (!cf->socket.io_offset) {
++ status = -ENXIO;
+ goto fail1;
++ }
+
+- /* reserve CS4, CS5, and CS6 regions; but use just CS4 */
++ /* reserve chip-select regions */
+ if (!request_mem_region(io->start, io->end + 1 - io->start,
+- driver_name))
++ driver_name)) {
++ status = -ENXIO;
+ goto fail1;
++ }
+
+ pr_info("%s: irqs det #%d, io #%d\n", driver_name,
+ board->det_pin, board->irq_pin);
+@@ -319,9 +302,7 @@
+ fail0a:
+ device_init_wakeup(&pdev->dev, 0);
+ free_irq(board->det_pin, cf);
+- device_init_wakeup(&pdev->dev, 0);
+ fail0:
+- at91_sys_write(AT91_EBI_CSA, csa);
+ kfree(cf);
+ return status;
+ }
+@@ -331,19 +312,15 @@
+ struct at91_cf_socket *cf = platform_get_drvdata(pdev);
+ struct at91_cf_data *board = cf->board;
+ struct resource *io = cf->socket.io[0].res;
+- unsigned int csa;
+
+ pcmcia_unregister_socket(&cf->socket);
+ if (board->irq_pin)
+ free_irq(board->irq_pin, cf);
+- free_irq(board->det_pin, cf);
+ device_init_wakeup(&pdev->dev, 0);
++ free_irq(board->det_pin, cf);
+ iounmap((void __iomem *) cf->socket.io_offset);
+ release_mem_region(io->start, io->end + 1 - io->start);
+
+- csa = at91_sys_read(AT91_EBI_CSA);
+- at91_sys_write(AT91_EBI_CSA, csa & ~AT91_EBI_CS4A);
+-
+ kfree(cf);
+ return 0;
+ }
+diff -urN -x CVS linux-2.6.19-final/drivers/rtc/Kconfig linux-2.6.19/drivers/rtc/Kconfig
+--- linux-2.6.19-final/drivers/rtc/Kconfig Mon Dec 4 16:40:27 2006
++++ linux-2.6.19/drivers/rtc/Kconfig Thu Oct 12 17:07:39 2006
+@@ -280,7 +280,7 @@
+ To compile this driver as a module, choose M here: the
+ module will be called rtc-pl031.
+
+-config RTC_DRV_AT91
++config RTC_DRV_AT91RM9200
+ tristate "AT91RM9200"
+ depends on RTC_CLASS && ARCH_AT91RM9200
+ help
+diff -urN -x CVS linux-2.6.19-final/drivers/rtc/Makefile linux-2.6.19/drivers/rtc/Makefile
+--- linux-2.6.19-final/drivers/rtc/Makefile Mon Dec 4 16:40:27 2006
++++ linux-2.6.19/drivers/rtc/Makefile Fri Oct 13 10:49:07 2006
+@@ -34,5 +34,5 @@
+ obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o
+ obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o
+ obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o
+-obj-$(CONFIG_RTC_DRV_AT91) += rtc-at91.o
++obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
+ obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o
+diff -urN -x CVS linux-2.6.19-final/drivers/rtc/rtc-at91.c linux-2.6.19/drivers/rtc/rtc-at91.c
+--- linux-2.6.19-final/drivers/rtc/rtc-at91.c Mon Dec 4 16:40:27 2006
++++ linux-2.6.19/drivers/rtc/rtc-at91.c Thu Jan 1 02:00:00 1970
+@@ -1,429 +0,0 @@
+-/*
+- * Real Time Clock interface for Linux on Atmel AT91RM9200
+- *
+- * Copyright (C) 2002 Rick Bronson
+- *
+- * Converted to RTC class model by Andrew Victor
+- *
+- * Ported to Linux 2.6 by Steven Scholz
+- * Based on s3c2410-rtc.c Simtec Electronics
+- *
+- * Based on sa1100-rtc.c by Nils Faerber
+- * Based on rtc.c by Paul Gortmaker
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * as published by the Free Software Foundation; either version
+- * 2 of the License, or (at your option) any later version.
+- *
+- */
+-
+-#include <linux/module.h>
+-#include <linux/kernel.h>
+-#include <linux/platform_device.h>
+-#include <linux/time.h>
+-#include <linux/rtc.h>
+-#include <linux/bcd.h>
+-#include <linux/interrupt.h>
+-#include <linux/ioctl.h>
+-#include <linux/completion.h>
+-
+-#include <asm/uaccess.h>
+-#include <asm/rtc.h>
+-
+-#include <asm/mach/time.h>
+-
+-
+-#define AT91_RTC_FREQ 1
+-#define AT91_RTC_EPOCH 1900UL /* just like arch/arm/common/rtctime.c */
+-
+-static DECLARE_COMPLETION(at91_rtc_updated);
+-static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
+-
+-/*
+- * Decode time/date into rtc_time structure
+- */
+-static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
+- struct rtc_time *tm)
+-{
+- unsigned int time, date;
+-
+- /* must read twice in case it changes */
+- do {
+- time = at91_sys_read(timereg);
+- date = at91_sys_read(calreg);
+- } while ((time != at91_sys_read(timereg)) ||
+- (date != at91_sys_read(calreg)));
+-
+- tm->tm_sec = BCD2BIN((time & AT91_RTC_SEC) >> 0);
+- tm->tm_min = BCD2BIN((time & AT91_RTC_MIN) >> 8);
+- tm->tm_hour = BCD2BIN((time & AT91_RTC_HOUR) >> 16);
+-
+- /*
+- * The Calendar Alarm register does not have a field for
+- * the year - so these will return an invalid value. When an
+- * alarm is set, at91_alarm_year wille store the current year.
+- */
+- tm->tm_year = BCD2BIN(date & AT91_RTC_CENT) * 100; /* century */
+- tm->tm_year += BCD2BIN((date & AT91_RTC_YEAR) >> 8); /* year */
+-
+- tm->tm_wday = BCD2BIN((date & AT91_RTC_DAY) >> 21) - 1; /* day of the week [0-6], Sunday=0 */
+- tm->tm_mon = BCD2BIN((date & AT91_RTC_MONTH) >> 16) - 1;
+- tm->tm_mday = BCD2BIN((date & AT91_RTC_DATE) >> 24);
+-}
+-
+-/*
+- * Read current time and date in RTC
+- */
+-static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
+-{
+- at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
+- tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
+- tm->tm_year = tm->tm_year - 1900;
+-
+- pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
+- 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
+- tm->tm_hour, tm->tm_min, tm->tm_sec);
+-
+- return 0;
+-}
+-
+-/*
+- * Set current time and date in RTC
+- */
+-static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
+-{
+- unsigned long cr;
+-
+- pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
+- 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
+- tm->tm_hour, tm->tm_min, tm->tm_sec);
+-
+- /* Stop Time/Calendar from counting */
+- cr = at91_sys_read(AT91_RTC_CR);
+- at91_sys_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
+-
+- at91_sys_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
+- wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
+- at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
+-
+- at91_sys_write(AT91_RTC_TIMR,
+- BIN2BCD(tm->tm_sec) << 0
+- | BIN2BCD(tm->tm_min) << 8
+- | BIN2BCD(tm->tm_hour) << 16);
+-
+- at91_sys_write(AT91_RTC_CALR,
+- BIN2BCD((tm->tm_year + 1900) / 100) /* century */
+- | BIN2BCD(tm->tm_year % 100) << 8 /* year */
+- | BIN2BCD(tm->tm_mon + 1) << 16 /* tm_mon starts at zero */
+- | BIN2BCD(tm->tm_wday + 1) << 21 /* day of the week [0-6], Sunday=0 */
+- | BIN2BCD(tm->tm_mday) << 24);
+-
+- /* Restart Time/Calendar */
+- cr = at91_sys_read(AT91_RTC_CR);
+- at91_sys_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
+-
+- return 0;
+-}
+-
+-/*
+- * Read alarm time and date in RTC
+- */
+-static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
+-{
+- struct rtc_time *tm = &alrm->time;
+-
+- at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
+- tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
+- tm->tm_year = at91_alarm_year - 1900;
+-
+- pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
+- 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
+- tm->tm_hour, tm->tm_min, tm->tm_sec);
+-
+- return 0;
+-}
+-
+-/*
+- * Set alarm time and date in RTC
+- */
+-static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+-{
+- struct rtc_time tm;
+-
+- at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, &tm);
+-
+- at91_alarm_year = tm.tm_year;
+-
+- tm.tm_hour = alrm->time.tm_hour;
+- tm.tm_min = alrm->time.tm_min;
+- tm.tm_sec = alrm->time.tm_sec;
+-
+- at91_sys_write(AT91_RTC_TIMALR,
+- BIN2BCD(tm.tm_sec) << 0
+- | BIN2BCD(tm.tm_min) << 8
+- | BIN2BCD(tm.tm_hour) << 16
+- | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
+- at91_sys_write(AT91_RTC_CALALR,
+- BIN2BCD(tm.tm_mon + 1) << 16 /* tm_mon starts at zero */
+- | BIN2BCD(tm.tm_mday) << 24
+- | AT91_RTC_DATEEN | AT91_RTC_MTHEN);
+-
+- pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
+- at91_alarm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour,
+- tm.tm_min, tm.tm_sec);
+-
+- return 0;
+-}
+-
+-/*
+- * Handle commands from user-space
+- */
+-static int at91_rtc_ioctl(struct device *dev, unsigned int cmd,
+- unsigned long arg)
+-{
+- int ret = 0;
+-
+- pr_debug("%s(): cmd=%08x, arg=%08lx.\n", __FUNCTION__, cmd, arg);
+-
+- switch (cmd) {
+- case RTC_AIE_OFF: /* alarm off */
+- at91_sys_write(AT91_RTC_IDR, AT91_RTC_ALARM);
+- break;
+- case RTC_AIE_ON: /* alarm on */
+- at91_sys_write(AT91_RTC_IER, AT91_RTC_ALARM);
+- break;
+- case RTC_UIE_OFF: /* update off */
+- case RTC_PIE_OFF: /* periodic off */
+- at91_sys_write(AT91_RTC_IDR, AT91_RTC_SECEV);
+- break;
+- case RTC_UIE_ON: /* update on */
+- case RTC_PIE_ON: /* periodic on */
+- at91_sys_write(AT91_RTC_IER, AT91_RTC_SECEV);
+- break;
+- case RTC_IRQP_READ: /* read periodic alarm frequency */
+- ret = put_user(AT91_RTC_FREQ, (unsigned long *) arg);
+- break;
+- case RTC_IRQP_SET: /* set periodic alarm frequency */
+- if (arg != AT91_RTC_FREQ)
+- ret = -EINVAL;
+- break;
+- default:
+- ret = -ENOIOCTLCMD;
+- break;
+- }
+-
+- return ret;
+-}
+-
+-/*
+- * Provide additional RTC information in /proc/driver/rtc
+- */
+-static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
+-{
+- unsigned long imr = at91_sys_read(AT91_RTC_IMR);
+-
+- seq_printf(seq, "alarm_IRQ\t: %s\n",
+- (imr & AT91_RTC_ALARM) ? "yes" : "no");
+- seq_printf(seq, "update_IRQ\t: %s\n",
+- (imr & AT91_RTC_ACKUPD) ? "yes" : "no");
+- seq_printf(seq, "periodic_IRQ\t: %s\n",
+- (imr & AT91_RTC_SECEV) ? "yes" : "no");
+- seq_printf(seq, "periodic_freq\t: %ld\n",
+- (unsigned long) AT91_RTC_FREQ);
+-
+- return 0;
+-}
+-
+-/*
+- * IRQ handler for the RTC
+- */
+-static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
+-{
+- struct platform_device *pdev = dev_id;
+- struct rtc_device *rtc = platform_get_drvdata(pdev);
+- unsigned int rtsr;
+- unsigned long events = 0;
+-
+- rtsr = at91_sys_read(AT91_RTC_SR) & at91_sys_read(AT91_RTC_IMR);
+- if (rtsr) { /* this interrupt is shared! Is it ours? */
+- if (rtsr & AT91_RTC_ALARM)
+- events |= (RTC_AF | RTC_IRQF);
+- if (rtsr & AT91_RTC_SECEV)
+- events |= (RTC_UF | RTC_IRQF);
+- if (rtsr & AT91_RTC_ACKUPD)
+- complete(&at91_rtc_updated);
+-
+- at91_sys_write(AT91_RTC_SCCR, rtsr); /* clear status reg */
+-
+- rtc_update_irq(&rtc->class_dev, 1, events);
+-
+- pr_debug("%s(): num=%ld, events=0x%02lx\n", __FUNCTION__,
+- events >> 8, events & 0x000000FF);
+-
+- return IRQ_HANDLED;
+- }
+- return IRQ_NONE; /* not handled */
+-}
+-
+-static const struct rtc_class_ops at91_rtc_ops = {
+- .ioctl = at91_rtc_ioctl,
+- .read_time = at91_rtc_readtime,
+- .set_time = at91_rtc_settime,
+- .read_alarm = at91_rtc_readalarm,
+- .set_alarm = at91_rtc_setalarm,
+- .proc = at91_rtc_proc,
+-};
+-
+-/*
+- * Initialize and install RTC driver
+- */
+-static int __init at91_rtc_probe(struct platform_device *pdev)
+-{
+- struct rtc_device *rtc;
+- int ret;
+-
+- at91_sys_write(AT91_RTC_CR, 0);
+- at91_sys_write(AT91_RTC_MR, 0); /* 24 hour mode */
+-
+- /* Disable all interrupts */
+- at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+- AT91_RTC_SECEV | AT91_RTC_TIMEV |
+- AT91_RTC_CALEV);
+-
+- ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
+- IRQF_DISABLED | IRQF_SHARED,
+- "at91_rtc", pdev);
+- if (ret) {
+- printk(KERN_ERR "at91_rtc: IRQ %d already in use.\n",
+- AT91_ID_SYS);
+- return ret;
+- }
+-
+- rtc = rtc_device_register(pdev->name, &pdev->dev,
+- &at91_rtc_ops, THIS_MODULE);
+- if (IS_ERR(rtc)) {
+- free_irq(AT91_ID_SYS, pdev);
+- return PTR_ERR(rtc);
+- }
+- platform_set_drvdata(pdev, rtc);
+- device_init_wakeup(&pdev->dev, 1);
+-
+- printk(KERN_INFO "AT91 Real Time Clock driver.\n");
+- return 0;
+-}
+-
+-/*
+- * Disable and remove the RTC driver
+- */
+-static int __devexit at91_rtc_remove(struct platform_device *pdev)
+-{
+- struct rtc_device *rtc = platform_get_drvdata(pdev);
+-
+- /* Disable all interrupts */
+- at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+- AT91_RTC_SECEV | AT91_RTC_TIMEV |
+- AT91_RTC_CALEV);
+- free_irq(AT91_ID_SYS, pdev);
+-
+- rtc_device_unregister(rtc);
+- platform_set_drvdata(pdev, NULL);
+- device_init_wakeup(&pdev->dev, 0);
+-
+- return 0;
+-}
+-
+-#ifdef CONFIG_PM
+-
+-/* AT91RM9200 RTC Power management control */
+-
+-static struct timespec at91_rtc_delta;
+-static u32 at91_rtc_imr;
+-
+-static int at91_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+-{
+- struct rtc_time tm;
+- struct timespec time;
+-
+- time.tv_nsec = 0;
+-
+- /* calculate time delta for suspend */
+- at91_rtc_readtime(&pdev->dev, &tm);
+- rtc_tm_to_time(&tm, &time.tv_sec);
+- save_time_delta(&at91_rtc_delta, &time);
+-
+- /* this IRQ is shared with DBGU and other hardware which isn't
+- * necessarily doing PM like we are...
+- */
+- at91_rtc_imr = at91_sys_read(AT91_RTC_IMR)
+- & (AT91_RTC_ALARM|AT91_RTC_SECEV);
+- if (at91_rtc_imr) {
+- if (device_may_wakeup(&pdev->dev))
+- enable_irq_wake(AT91_ID_SYS);
+- else
+- at91_sys_write(AT91_RTC_IDR, at91_rtc_imr);
+- }
+-
+- pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
+- 1900 + tm.tm_year, tm.tm_mon, tm.tm_mday,
+- tm.tm_hour, tm.tm_min, tm.tm_sec);
+-
+- return 0;
+-}
+-
+-static int at91_rtc_resume(struct platform_device *pdev)
+-{
+- struct rtc_time tm;
+- struct timespec time;
+-
+- time.tv_nsec = 0;
+-
+- at91_rtc_readtime(&pdev->dev, &tm);
+- rtc_tm_to_time(&tm, &time.tv_sec);
+- restore_time_delta(&at91_rtc_delta, &time);
+-
+- if (at91_rtc_imr) {
+- if (device_may_wakeup(&pdev->dev))
+- disable_irq_wake(AT91_ID_SYS);
+- else
+- at91_sys_write(AT91_RTC_IER, at91_rtc_imr);
+- }
+-
+- pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
+- 1900 + tm.tm_year, tm.tm_mon, tm.tm_mday,
+- tm.tm_hour, tm.tm_min, tm.tm_sec);
+-
+- return 0;
+-}
+-#else
+-#define at91_rtc_suspend NULL
+-#define at91_rtc_resume NULL
+-#endif
+-
+-static struct platform_driver at91_rtc_driver = {
+- .probe = at91_rtc_probe,
+- .remove = at91_rtc_remove,
+- .suspend = at91_rtc_suspend,
+- .resume = at91_rtc_resume,
+- .driver = {
+- .name = "at91_rtc",
+- .owner = THIS_MODULE,
+- },
+-};
+-
+-static int __init at91_rtc_init(void)
+-{
+- return platform_driver_register(&at91_rtc_driver);
+-}
+-
+-static void __exit at91_rtc_exit(void)
+-{
+- platform_driver_unregister(&at91_rtc_driver);
+-}
+-
+-module_init(at91_rtc_init);
+-module_exit(at91_rtc_exit);
+-
+-MODULE_AUTHOR("Rick Bronson");
+-MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
+-MODULE_LICENSE("GPL");
+diff -urN -x CVS linux-2.6.19-final/drivers/rtc/rtc-at91rm9200.c linux-2.6.19/drivers/rtc/rtc-at91rm9200.c
+--- linux-2.6.19-final/drivers/rtc/rtc-at91rm9200.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/rtc/rtc-at91rm9200.c Thu Nov 30 09:08:25 2006
+@@ -0,0 +1,430 @@
++/*
++ * Real Time Clock interface for Linux on Atmel AT91RM9200
++ *
++ * Copyright (C) 2002 Rick Bronson
++ *
++ * Converted to RTC class model by Andrew Victor
++ *
++ * Ported to Linux 2.6 by Steven Scholz
++ * Based on s3c2410-rtc.c Simtec Electronics
++ *
++ * Based on sa1100-rtc.c by Nils Faerber
++ * Based on rtc.c by Paul Gortmaker
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/time.h>
++#include <linux/rtc.h>
++#include <linux/bcd.h>
++#include <linux/interrupt.h>
++#include <linux/ioctl.h>
++#include <linux/completion.h>
++
++#include <asm/uaccess.h>
++#include <asm/rtc.h>
++
++#include <asm/mach/time.h>
++#include <asm/arch/at91_rtc.h>
++
++
++#define AT91_RTC_FREQ 1
++#define AT91_RTC_EPOCH 1900UL /* just like arch/arm/common/rtctime.c */
++
++static DECLARE_COMPLETION(at91_rtc_updated);
++static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
++
++/*
++ * Decode time/date into rtc_time structure
++ */
++static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
++ struct rtc_time *tm)
++{
++ unsigned int time, date;
++
++ /* must read twice in case it changes */
++ do {
++ time = at91_sys_read(timereg);
++ date = at91_sys_read(calreg);
++ } while ((time != at91_sys_read(timereg)) ||
++ (date != at91_sys_read(calreg)));
++
++ tm->tm_sec = BCD2BIN((time & AT91_RTC_SEC) >> 0);
++ tm->tm_min = BCD2BIN((time & AT91_RTC_MIN) >> 8);
++ tm->tm_hour = BCD2BIN((time & AT91_RTC_HOUR) >> 16);
++
++ /*
++ * The Calendar Alarm register does not have a field for
++ * the year - so these will return an invalid value. When an
++ * alarm is set, at91_alarm_year wille store the current year.
++ */
++ tm->tm_year = BCD2BIN(date & AT91_RTC_CENT) * 100; /* century */
++ tm->tm_year += BCD2BIN((date & AT91_RTC_YEAR) >> 8); /* year */
++
++ tm->tm_wday = BCD2BIN((date & AT91_RTC_DAY) >> 21) - 1; /* day of the week [0-6], Sunday=0 */
++ tm->tm_mon = BCD2BIN((date & AT91_RTC_MONTH) >> 16) - 1;
++ tm->tm_mday = BCD2BIN((date & AT91_RTC_DATE) >> 24);
++}
++
++/*
++ * Read current time and date in RTC
++ */
++static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
++{
++ at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
++ tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
++ tm->tm_year = tm->tm_year - 1900;
++
++ pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
++ 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
++ tm->tm_hour, tm->tm_min, tm->tm_sec);
++
++ return 0;
++}
++
++/*
++ * Set current time and date in RTC
++ */
++static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
++{
++ unsigned long cr;
++
++ pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
++ 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
++ tm->tm_hour, tm->tm_min, tm->tm_sec);
++
++ /* Stop Time/Calendar from counting */
++ cr = at91_sys_read(AT91_RTC_CR);
++ at91_sys_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
++
++ at91_sys_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
++ wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
++ at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
++
++ at91_sys_write(AT91_RTC_TIMR,
++ BIN2BCD(tm->tm_sec) << 0
++ | BIN2BCD(tm->tm_min) << 8
++ | BIN2BCD(tm->tm_hour) << 16);
++
++ at91_sys_write(AT91_RTC_CALR,
++ BIN2BCD((tm->tm_year + 1900) / 100) /* century */
++ | BIN2BCD(tm->tm_year % 100) << 8 /* year */
++ | BIN2BCD(tm->tm_mon + 1) << 16 /* tm_mon starts at zero */
++ | BIN2BCD(tm->tm_wday + 1) << 21 /* day of the week [0-6], Sunday=0 */
++ | BIN2BCD(tm->tm_mday) << 24);
++
++ /* Restart Time/Calendar */
++ cr = at91_sys_read(AT91_RTC_CR);
++ at91_sys_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
++
++ return 0;
++}
++
++/*
++ * Read alarm time and date in RTC
++ */
++static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
++{
++ struct rtc_time *tm = &alrm->time;
++
++ at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
++ tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
++ tm->tm_year = at91_alarm_year - 1900;
++
++ pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
++ 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
++ tm->tm_hour, tm->tm_min, tm->tm_sec);
++
++ return 0;
++}
++
++/*
++ * Set alarm time and date in RTC
++ */
++static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
++{
++ struct rtc_time tm;
++
++ at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, &tm);
++
++ at91_alarm_year = tm.tm_year;
++
++ tm.tm_hour = alrm->time.tm_hour;
++ tm.tm_min = alrm->time.tm_min;
++ tm.tm_sec = alrm->time.tm_sec;
++
++ at91_sys_write(AT91_RTC_TIMALR,
++ BIN2BCD(tm.tm_sec) << 0
++ | BIN2BCD(tm.tm_min) << 8
++ | BIN2BCD(tm.tm_hour) << 16
++ | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
++ at91_sys_write(AT91_RTC_CALALR,
++ BIN2BCD(tm.tm_mon + 1) << 16 /* tm_mon starts at zero */
++ | BIN2BCD(tm.tm_mday) << 24
++ | AT91_RTC_DATEEN | AT91_RTC_MTHEN);
++
++ pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
++ at91_alarm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour,
++ tm.tm_min, tm.tm_sec);
++
++ return 0;
++}
++
++/*
++ * Handle commands from user-space
++ */
++static int at91_rtc_ioctl(struct device *dev, unsigned int cmd,
++ unsigned long arg)
++{
++ int ret = 0;
++
++ pr_debug("%s(): cmd=%08x, arg=%08lx.\n", __FUNCTION__, cmd, arg);
++
++ switch (cmd) {
++ case RTC_AIE_OFF: /* alarm off */
++ at91_sys_write(AT91_RTC_IDR, AT91_RTC_ALARM);
++ break;
++ case RTC_AIE_ON: /* alarm on */
++ at91_sys_write(AT91_RTC_IER, AT91_RTC_ALARM);
++ break;
++ case RTC_UIE_OFF: /* update off */
++ case RTC_PIE_OFF: /* periodic off */
++ at91_sys_write(AT91_RTC_IDR, AT91_RTC_SECEV);
++ break;
++ case RTC_UIE_ON: /* update on */
++ case RTC_PIE_ON: /* periodic on */
++ at91_sys_write(AT91_RTC_IER, AT91_RTC_SECEV);
++ break;
++ case RTC_IRQP_READ: /* read periodic alarm frequency */
++ ret = put_user(AT91_RTC_FREQ, (unsigned long *) arg);
++ break;
++ case RTC_IRQP_SET: /* set periodic alarm frequency */
++ if (arg != AT91_RTC_FREQ)
++ ret = -EINVAL;
++ break;
++ default:
++ ret = -ENOIOCTLCMD;
++ break;
++ }
++
++ return ret;
++}
++
++/*
++ * Provide additional RTC information in /proc/driver/rtc
++ */
++static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
++{
++ unsigned long imr = at91_sys_read(AT91_RTC_IMR);
++
++ seq_printf(seq, "alarm_IRQ\t: %s\n",
++ (imr & AT91_RTC_ALARM) ? "yes" : "no");
++ seq_printf(seq, "update_IRQ\t: %s\n",
++ (imr & AT91_RTC_ACKUPD) ? "yes" : "no");
++ seq_printf(seq, "periodic_IRQ\t: %s\n",
++ (imr & AT91_RTC_SECEV) ? "yes" : "no");
++ seq_printf(seq, "periodic_freq\t: %ld\n",
++ (unsigned long) AT91_RTC_FREQ);
++
++ return 0;
++}
++
++/*
++ * IRQ handler for the RTC
++ */
++static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
++{
++ struct platform_device *pdev = dev_id;
++ struct rtc_device *rtc = platform_get_drvdata(pdev);
++ unsigned int rtsr;
++ unsigned long events = 0;
++
++ rtsr = at91_sys_read(AT91_RTC_SR) & at91_sys_read(AT91_RTC_IMR);
++ if (rtsr) { /* this interrupt is shared! Is it ours? */
++ if (rtsr & AT91_RTC_ALARM)
++ events |= (RTC_AF | RTC_IRQF);
++ if (rtsr & AT91_RTC_SECEV)
++ events |= (RTC_UF | RTC_IRQF);
++ if (rtsr & AT91_RTC_ACKUPD)
++ complete(&at91_rtc_updated);
++
++ at91_sys_write(AT91_RTC_SCCR, rtsr); /* clear status reg */
++
++ rtc_update_irq(&rtc->class_dev, 1, events);
++
++ pr_debug("%s(): num=%ld, events=0x%02lx\n", __FUNCTION__,
++ events >> 8, events & 0x000000FF);
++
++ return IRQ_HANDLED;
++ }
++ return IRQ_NONE; /* not handled */
++}
++
++static const struct rtc_class_ops at91_rtc_ops = {
++ .ioctl = at91_rtc_ioctl,
++ .read_time = at91_rtc_readtime,
++ .set_time = at91_rtc_settime,
++ .read_alarm = at91_rtc_readalarm,
++ .set_alarm = at91_rtc_setalarm,
++ .proc = at91_rtc_proc,
++};
++
++/*
++ * Initialize and install RTC driver
++ */
++static int __init at91_rtc_probe(struct platform_device *pdev)
++{
++ struct rtc_device *rtc;
++ int ret;
++
++ at91_sys_write(AT91_RTC_CR, 0);
++ at91_sys_write(AT91_RTC_MR, 0); /* 24 hour mode */
++
++ /* Disable all interrupts */
++ at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
++ AT91_RTC_SECEV | AT91_RTC_TIMEV |
++ AT91_RTC_CALEV);
++
++ ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
++ IRQF_DISABLED | IRQF_SHARED,
++ "at91_rtc", pdev);
++ if (ret) {
++ printk(KERN_ERR "at91_rtc: IRQ %d already in use.\n",
++ AT91_ID_SYS);
++ return ret;
++ }
++
++ rtc = rtc_device_register(pdev->name, &pdev->dev,
++ &at91_rtc_ops, THIS_MODULE);
++ if (IS_ERR(rtc)) {
++ free_irq(AT91_ID_SYS, pdev);
++ return PTR_ERR(rtc);
++ }
++ platform_set_drvdata(pdev, rtc);
++ device_init_wakeup(&pdev->dev, 1);
++
++ printk(KERN_INFO "AT91 Real Time Clock driver.\n");
++ return 0;
++}
++
++/*
++ * Disable and remove the RTC driver
++ */
++static int __devexit at91_rtc_remove(struct platform_device *pdev)
++{
++ struct rtc_device *rtc = platform_get_drvdata(pdev);
++
++ /* Disable all interrupts */
++ at91_sys_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
++ AT91_RTC_SECEV | AT91_RTC_TIMEV |
++ AT91_RTC_CALEV);
++ free_irq(AT91_ID_SYS, pdev);
++
++ rtc_device_unregister(rtc);
++ platform_set_drvdata(pdev, NULL);
++ device_init_wakeup(&pdev->dev, 0);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++
++/* AT91RM9200 RTC Power management control */
++
++static struct timespec at91_rtc_delta;
++static u32 at91_rtc_imr;
++
++static int at91_rtc_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct rtc_time tm;
++ struct timespec time;
++
++ time.tv_nsec = 0;
++
++ /* calculate time delta for suspend */
++ at91_rtc_readtime(&pdev->dev, &tm);
++ rtc_tm_to_time(&tm, &time.tv_sec);
++ save_time_delta(&at91_rtc_delta, &time);
++
++ /* this IRQ is shared with DBGU and other hardware which isn't
++ * necessarily doing PM like we are...
++ */
++ at91_rtc_imr = at91_sys_read(AT91_RTC_IMR)
++ & (AT91_RTC_ALARM|AT91_RTC_SECEV);
++ if (at91_rtc_imr) {
++ if (device_may_wakeup(&pdev->dev))
++ enable_irq_wake(AT91_ID_SYS);
++ else
++ at91_sys_write(AT91_RTC_IDR, at91_rtc_imr);
++ }
++
++ pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
++ 1900 + tm.tm_year, tm.tm_mon, tm.tm_mday,
++ tm.tm_hour, tm.tm_min, tm.tm_sec);
++
++ return 0;
++}
++
++static int at91_rtc_resume(struct platform_device *pdev)
++{
++ struct rtc_time tm;
++ struct timespec time;
++
++ time.tv_nsec = 0;
++
++ at91_rtc_readtime(&pdev->dev, &tm);
++ rtc_tm_to_time(&tm, &time.tv_sec);
++ restore_time_delta(&at91_rtc_delta, &time);
++
++ if (at91_rtc_imr) {
++ if (device_may_wakeup(&pdev->dev))
++ disable_irq_wake(AT91_ID_SYS);
++ else
++ at91_sys_write(AT91_RTC_IER, at91_rtc_imr);
++ }
++
++ pr_debug("%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __FUNCTION__,
++ 1900 + tm.tm_year, tm.tm_mon, tm.tm_mday,
++ tm.tm_hour, tm.tm_min, tm.tm_sec);
++
++ return 0;
++}
++#else
++#define at91_rtc_suspend NULL
++#define at91_rtc_resume NULL
++#endif
++
++static struct platform_driver at91_rtc_driver = {
++ .probe = at91_rtc_probe,
++ .remove = at91_rtc_remove,
++ .suspend = at91_rtc_suspend,
++ .resume = at91_rtc_resume,
++ .driver = {
++ .name = "at91_rtc",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init at91_rtc_init(void)
++{
++ return platform_driver_register(&at91_rtc_driver);
++}
++
++static void __exit at91_rtc_exit(void)
++{
++ platform_driver_unregister(&at91_rtc_driver);
++}
++
++module_init(at91_rtc_init);
++module_exit(at91_rtc_exit);
++
++MODULE_AUTHOR("Rick Bronson");
++MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
++MODULE_LICENSE("GPL");
+diff -urN -x CVS linux-2.6.19-final/drivers/serial/atmel_serial.c linux-2.6.19/drivers/serial/atmel_serial.c
+--- linux-2.6.19-final/drivers/serial/atmel_serial.c Mon Dec 4 16:40:48 2006
++++ linux-2.6.19/drivers/serial/atmel_serial.c Fri Nov 10 09:17:31 2006
+@@ -1,5 +1,5 @@
+ /*
+- * linux/drivers/char/at91_serial.c
++ * linux/drivers/char/atmel_serial.c
+ *
+ * Driver for Atmel AT91 / AT32 Serial ports
+ * Copyright (C) 2003 Rick Bronson
+@@ -7,6 +7,8 @@
+ * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
+ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
++ * DMA support added by Chip Coldwell.
++ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+@@ -33,19 +35,25 @@
+ #include <linux/sysrq.h>
+ #include <linux/tty_flip.h>
+ #include <linux/platform_device.h>
++#include <linux/dma-mapping.h>
+
+ #include <asm/io.h>
+
+-#include <asm/arch/at91rm9200_pdc.h>
+ #include <asm/mach/serial_at91.h>
+ #include <asm/arch/board.h>
++#include <asm/arch/at91_pdc.h>
+ #ifdef CONFIG_ARM
+-#include <asm/arch/system.h>
++#include <asm/arch/cpu.h>
+ #include <asm/arch/gpio.h>
+ #endif
+
+ #include "atmel_serial.h"
+
++#define SUPPORT_PDC
++#define PDC_BUFFER_SIZE (L1_CACHE_BYTES << 3)
++#warning "Revisit"
++#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
++
+ #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+ #define SUPPORT_SYSRQ
+ #endif
+@@ -89,23 +97,30 @@
+ // #define UART_GET_CR(port) readl((port)->membase + ATMEL_US_CR) // is write-only
+
+ /* PDC registers */
+-#define UART_PUT_PTCR(port,v) writel(v, (port)->membase + ATMEL_PDC_PTCR)
+-#define UART_GET_PTSR(port) readl((port)->membase + ATMEL_PDC_PTSR)
++#define UART_PUT_PTCR(port,v) writel(v, (port)->membase + AT91_PDC_PTCR)
++#define UART_GET_PTSR(port) readl((port)->membase + AT91_PDC_PTSR)
+
+-#define UART_PUT_RPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RPR)
+-#define UART_GET_RPR(port) readl((port)->membase + ATMEL_PDC_RPR)
+-#define UART_PUT_RCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RCR)
+-#define UART_PUT_RNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNPR)
+-#define UART_PUT_RNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_RNCR)
+-
+-#define UART_PUT_TPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TPR)
+-#define UART_PUT_TCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TCR)
+-//#define UART_PUT_TNPR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNPR)
+-//#define UART_PUT_TNCR(port,v) writel(v, (port)->membase + ATMEL_PDC_TNCR)
++#define UART_PUT_RPR(port,v) writel(v, (port)->membase + AT91_PDC_RPR)
++#define UART_GET_RPR(port) readl((port)->membase + AT91_PDC_RPR)
++#define UART_PUT_RCR(port,v) writel(v, (port)->membase + AT91_PDC_RCR)
++#define UART_PUT_RNPR(port,v) writel(v, (port)->membase + AT91_PDC_RNPR)
++#define UART_PUT_RNCR(port,v) writel(v, (port)->membase + AT91_PDC_RNCR)
++
++#define UART_PUT_TPR(port,v) writel(v, (port)->membase + AT91_PDC_TPR)
++#define UART_PUT_TCR(port,v) writel(v, (port)->membase + AT91_PDC_TCR)
++//#define UART_PUT_TNPR(port,v) writel(v, (port)->membase + AT91_PDC_TNPR)
++//#define UART_PUT_TNCR(port,v) writel(v, (port)->membase + AT91_PDC_TNCR)
+
+ static int (*atmel_open_hook)(struct uart_port *);
+ static void (*atmel_close_hook)(struct uart_port *);
+
++struct atmel_dma_buffer {
++ unsigned char *buf;
++ dma_addr_t dma_addr;
++ size_t dma_size;
++ unsigned int ofs;
++};
++
+ /*
+ * We wrap our port structure around the generic uart_port.
+ */
+@@ -113,10 +128,20 @@
+ struct uart_port uart; /* uart */
+ struct clk *clk; /* uart clock */
+ unsigned short suspended; /* is port suspended? */
++
++ short use_dma_rx; /* enable PDC receiver */
++ short pdc_rx_idx; /* current PDC RX buffer */
++ struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
++
++ short use_dma_tx; /* enable PDC transmitter */
++ struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
+ };
+
+ static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
+
++#define PDC_RX_BUF(port) &(port)->pdc_rx[(port)->pdc_rx_idx]
++#define PDC_RX_SWITCH(port) (port)->pdc_rx_idx = !(port)->pdc_rx_idx
++
+ #ifdef SUPPORT_SYSRQ
+ static struct console atmel_console;
+ #endif
+@@ -137,8 +162,8 @@
+ unsigned int control = 0;
+ unsigned int mode;
+
+-#ifdef CONFIG_ARM
+- if (arch_identify() == ARCH_ID_AT91RM9200) {
++#ifdef CONFIG_ARCH_AT91RM9200
++ if (cpu_is_at91rm9200()) {
+ /*
+ * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
+ * We need to drive the pin manually.
+@@ -204,7 +229,12 @@
+ {
+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
+
+- UART_PUT_IDR(port, ATMEL_US_TXRDY);
++ if (atmel_port->use_dma_tx) {
++ UART_PUT_PTCR(port, AT91_PDC_TXTDIS); /* disable PDC transmit */
++ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
++ }
++ else
++ UART_PUT_IDR(port, ATMEL_US_TXRDY);
+ }
+
+ /*
+@@ -214,7 +244,17 @@
+ {
+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
+
+- UART_PUT_IER(port, ATMEL_US_TXRDY);
++ if (atmel_port->use_dma_tx) {
++ if (UART_GET_PTSR(port) & AT91_PDC_TXTEN)
++ /* The transmitter is already running. Yes, we
++ really need this.*/
++ return;
++
++ UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
++ UART_PUT_PTCR(port, AT91_PDC_TXTEN); /* re-enable PDC transmit */
++ }
++ else
++ UART_PUT_IER(port, ATMEL_US_TXRDY);
+ }
+
+ /*
+@@ -224,7 +264,12 @@
+ {
+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
+
+- UART_PUT_IDR(port, ATMEL_US_RXRDY);
++ if (atmel_port->use_dma_rx) {
++ UART_PUT_PTCR(port, AT91_PDC_RXTDIS); /* disable PDC receive */
++ UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
++ }
++ else
++ UART_PUT_IDR(port, ATMEL_US_RXRDY);
+ }
+
+ /*
+@@ -247,6 +292,134 @@
+ }
+
+ /*
++ * Receive data via the PDC. A buffer has been fulled.
++ */
++static void at91_pdc_endrx(struct uart_port *port)
++{
++ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
++ struct tty_struct *tty = port->info->tty;
++ struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port);
++ unsigned int count;
++
++ count = pdc->dma_size - pdc->ofs;
++ if (likely(count > 0)) {
++ dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
++ tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
++ tty_flip_buffer_push(tty);
++
++ port->icount.rx += count;
++ }
++
++ /* Set this buffer as the next receive buffer */
++ pdc->ofs = 0;
++ UART_PUT_RNPR(port, pdc->dma_addr);
++ UART_PUT_RNCR(port, pdc->dma_size);
++
++ /* Switch to next buffer */
++ PDC_RX_SWITCH(atmel_port); /* next PDC buffer */
++}
++
++/*
++ * Receive data via the PDC. At least one byte was received, but the
++ * buffer was not full when the inter-character timeout expired.
++ */
++static void at91_pdc_timeout(struct uart_port *port)
++{
++ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
++ struct tty_struct *tty = port->info->tty;
++ struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port);
++ /* unsigned */ int ofs, count;
++
++ ofs = UART_GET_RPR(port) - pdc->dma_addr; /* current DMA adress */
++ count = ofs - pdc->ofs;
++
++ if (likely(count > 0)) {
++ dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
++ tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
++ tty_flip_buffer_push(tty);
++
++ pdc->ofs = ofs;
++ port->icount.rx += count;
++ }
++
++ /* reset the UART timeout */
++ UART_PUT_CR(port, ATMEL_US_STTTO);
++}
++
++/*
++ * Deal with parity, framing and overrun errors.
++ */
++static void at91_pdc_rxerr(struct uart_port *port, unsigned int status)
++{
++ /* clear error */
++ UART_PUT_CR(port, ATMEL_US_RSTSTA);
++
++ if (status & ATMEL_US_RXBRK) {
++ status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */
++ port->icount.brk++;
++ }
++ if (status & ATMEL_US_PARE)
++ port->icount.parity++;
++ if (status & ATMEL_US_FRAME)
++ port->icount.frame++;
++ if (status & ATMEL_US_OVRE)
++ port->icount.overrun++;
++}
++
++/*
++ * A transmission via the PDC is complete.
++ */
++static void at91_pdc_endtx(struct uart_port *port)
++{
++ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
++ struct circ_buf *xmit = &port->info->xmit;
++ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
++
++ xmit->tail += pdc->ofs;
++ if (xmit->tail >= SERIAL_XMIT_SIZE)
++ xmit->tail -= SERIAL_XMIT_SIZE;
++
++ port->icount.tx += pdc->ofs;
++ pdc->ofs = 0;
++
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++ uart_write_wakeup(port);
++}
++
++/*
++ * The PDC transmitter is idle, so either start the next transfer or
++ * disable the transmitter.
++ */
++static void at91_pdc_txbufe(struct uart_port *port)
++{
++ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
++ struct circ_buf *xmit = &port->info->xmit;
++ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
++ int count;
++
++ if (!uart_circ_empty(xmit)) {
++ /* more to transmit - setup next transfer */
++ UART_PUT_PTCR(port, AT91_PDC_TXTDIS); /* disable PDC transmit */
++ dma_sync_single_for_device(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE);
++
++ if (xmit->tail < xmit->head)
++ count = xmit->head - xmit->tail;
++ else
++ count = SERIAL_XMIT_SIZE - xmit->tail;
++ pdc->ofs = count;
++
++ UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
++ UART_PUT_TCR(port, count);
++ UART_PUT_PTCR(port, AT91_PDC_TXTEN); /* re-enable PDC transmit */
++ }
++ else {
++ /* nothing left to transmit - disable the transmitter */
++ UART_PUT_PTCR(port, AT91_PDC_TXTDIS); /* disable PDC transmit */
++ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
++ }
++}
++
++/*
+ * Characters received (called from interrupt handler)
+ */
+ static void atmel_rx_chars(struct uart_port *port)
+@@ -348,6 +521,14 @@
+ status = UART_GET_CSR(port);
+ pending = status & UART_GET_IMR(port);
+ while (pending) {
++ /* PDC receive */
++ if (pending & ATMEL_US_ENDRX)
++ at91_pdc_endrx(port);
++ if (pending & ATMEL_US_TIMEOUT)
++ at91_pdc_timeout(port);
++ if (atmel_port->use_dma_rx && pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | ATMEL_US_FRAME | ATMEL_US_PARE))
++ at91_pdc_rxerr(port, pending);
++
+ /* Interrupt receive */
+ if (pending & ATMEL_US_RXRDY)
+ atmel_rx_chars(port);
+@@ -362,6 +543,12 @@
+ if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC))
+ wake_up_interruptible(&port->info->delta_msr_wait);
+
++ /* PDC transmit */
++ if (pending & ATMEL_US_ENDTX)
++ at91_pdc_endtx(port);
++ if (pending & ATMEL_US_TXBUFE)
++ at91_pdc_txbufe(port);
++
+ /* Interrupt transmit */
+ if (pending & ATMEL_US_TXRDY)
+ atmel_tx_chars(port);
+@@ -399,6 +586,47 @@
+ return retval;
+ }
+
++ /*
++ * Initialize DMA (if necessary)
++ */
++ if (atmel_port->use_dma_rx) {
++ int i;
++
++ for (i = 0; i < 2; i++) {
++ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
++
++ pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
++ if (pdc->buf == NULL) {
++ if (i != 0) {
++ dma_unmap_single(port->dev, atmel_port->pdc_rx[0].dma_addr, PDC_BUFFER_SIZE, DMA_FROM_DEVICE);
++ kfree(atmel_port->pdc_rx[0].buf);
++ }
++ free_irq(port->irq, port);
++ return -ENOMEM;
++ }
++ pdc->dma_addr = dma_map_single(port->dev, pdc->buf, PDC_BUFFER_SIZE, DMA_FROM_DEVICE);
++ pdc->dma_size = PDC_BUFFER_SIZE;
++ pdc->ofs = 0;
++ }
++
++ atmel_port->pdc_rx_idx = 0;
++
++ UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
++ UART_PUT_RCR(port, PDC_BUFFER_SIZE);
++
++ UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
++ UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
++ }
++ if (atmel_port->use_dma_tx) {
++ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
++ struct circ_buf *xmit = &port->info->xmit;
++
++ pdc->buf = xmit->buf;
++ pdc->dma_addr = dma_map_single(port->dev, pdc->buf, SERIAL_XMIT_SIZE, DMA_TO_DEVICE);
++ pdc->dma_size = SERIAL_XMIT_SIZE;
++ pdc->ofs = 0;
++ }
++
+ /*
+ * If there is a specific "open" function (to register
+ * control line interrupts)
+@@ -417,7 +645,15 @@
+ UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
+ UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */
+
+- UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */
++ if (atmel_port->use_dma_rx) {
++ UART_PUT_RTOR(port, PDC_RX_TIMEOUT); /* set UART timeout */
++ UART_PUT_CR(port, ATMEL_US_STTTO);
++
++ UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
++ UART_PUT_PTCR(port, AT91_PDC_RXTEN); /* enable PDC controller */
++ }
++ else
++ UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */
+
+ return 0;
+ }
+@@ -430,6 +666,25 @@
+ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
+
+ /*
++ * Shut-down the DMA.
++ */
++ if (atmel_port->use_dma_rx) {
++ int i;
++
++ for (i = 0; i < 2; i++) {
++ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
++
++ dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
++ kfree(pdc->buf);
++ }
++ }
++ if (atmel_port->use_dma_tx) {
++ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
++
++ dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE);
++ }
++
++ /*
+ * Disable all interrupts, port and break condition.
+ */
+ UART_PUT_CR(port, ATMEL_US_RSTSTA);
+@@ -480,6 +735,7 @@
+ */
+ static void atmel_set_termios(struct uart_port *port, struct termios * termios, struct termios * old)
+ {
++ struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
+ unsigned long flags;
+ unsigned int mode, imr, quot, baud;
+
+@@ -533,6 +789,9 @@
+ if (termios->c_iflag & (BRKINT | PARMRK))
+ port->read_status_mask |= ATMEL_US_RXBRK;
+
++ if (atmel_port->use_dma_rx) /* need to enable error interrupts */
++ UART_PUT_IER(port, port->read_status_mask);
++
+ /*
+ * Characters to ignore
+ */
+@@ -711,6 +970,11 @@
+ clk_enable(atmel_port->clk);
+ port->uartclk = clk_get_rate(atmel_port->clk);
+ }
++
++#ifdef SUPPORT_PDC
++ atmel_port->use_dma_rx = data->use_dma_rx;
++ atmel_port->use_dma_tx = data->use_dma_tx;
++#endif
+ }
+
+ /*
+diff -urN -x CVS linux-2.6.19-final/drivers/serial/atmel_serial.h linux-2.6.19/drivers/serial/atmel_serial.h
+--- linux-2.6.19-final/drivers/serial/atmel_serial.h Mon Dec 4 16:40:48 2006
++++ linux-2.6.19/drivers/serial/atmel_serial.h Wed Nov 8 12:29:58 2006
+@@ -31,8 +31,8 @@
+ #define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */
+ #define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
+ #define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */
+-#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable */
+-#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable */
++#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
++#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
+ #define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */
+ #define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */
+
+@@ -92,9 +92,9 @@
+ #define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
+ #define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */
+ #define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */
+-#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change */
+-#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change */
+-#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change */
++#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
++#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
++#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
+ #define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */
+ #define ATMEL_US_RI (1 << 20) /* RI */
+ #define ATMEL_US_DSR (1 << 21) /* DSR */
+@@ -106,6 +106,7 @@
+ #define ATMEL_US_CSR 0x14 /* Channel Status Register */
+ #define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
+ #define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
++#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
+
+ #define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
+ #define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
+diff -urN -x CVS linux-2.6.19-final/drivers/spi/Kconfig linux-2.6.19/drivers/spi/Kconfig
+--- linux-2.6.19-final/drivers/spi/Kconfig Mon Dec 4 16:29:01 2006
++++ linux-2.6.19/drivers/spi/Kconfig Wed Nov 15 14:54:04 2006
+@@ -51,6 +51,13 @@
+ comment "SPI Master Controller Drivers"
+ depends on SPI_MASTER
+
++config SPI_ATMEL
++ tristate "Atmel SPI Controller"
++ depends on (ARCH_AT91 || AVR32) && SPI_MASTER
++ help
++ This selects a driver for the Atmel SPI Controller, present on
++ many AT32 (AVR32) and AT91 (ARM) chips.
++
+ config SPI_BITBANG
+ tristate "Bitbanging SPI master"
+ depends on SPI_MASTER && EXPERIMENTAL
+@@ -75,6 +82,25 @@
+ inexpensive battery powered microcontroller evaluation board.
+ This same cable can be used to flash new firmware.
+
++config SPI_AT91
++ tristate "AT91 SPI Master"
++ depends on SPI_MASTER && ARCH_AT91 && !SPI_ATMEL && EXPERIMENTAL
++ select SPI_BITBANG
++ select SPI_AT91_MANUAL_CS
++ help
++ This is dumb PIO bitbanging driver for the Atmel
++ AT91RM9200 and AT91SAM926x processors.
++ (Someone should provide a drop-in replacemnt of this code,
++ using the native SPI hardware and its DMA controller).
++
++config SPI_AT91_MANUAL_CS
++ bool
++ depends on ARCH_AT91RM9200
++ help
++ Works around an AT91RM9200 problem whereby the SPI chip-select
++ will be wrongly disabled. The workaround uses those pins as
++ GPIOs instead of letting the SPI controller manage them.
++
+ config SPI_MPC83xx
+ tristate "Freescale MPC83xx SPI controller"
+ depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
+diff -urN -x CVS linux-2.6.19-final/drivers/spi/Makefile linux-2.6.19/drivers/spi/Makefile
+--- linux-2.6.19-final/drivers/spi/Makefile Mon Dec 4 16:29:01 2006
++++ linux-2.6.19/drivers/spi/Makefile Wed Nov 15 14:54:35 2006
+@@ -17,6 +17,8 @@
+ obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o
+ obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
+ obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o
++obj-$(CONFIG_SPI_AT91) += spi_at91_bitbang.o
++obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
+ # ... add above this line ...
+
+ # SPI protocol drivers (device/link on bus)
+diff -urN -x CVS linux-2.6.19-final/drivers/spi/atmel_spi.c linux-2.6.19/drivers/spi/atmel_spi.c
+--- linux-2.6.19-final/drivers/spi/atmel_spi.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/spi/atmel_spi.c Wed Nov 22 09:22:22 2006
+@@ -0,0 +1,684 @@
++/*
++ * Driver for Atmel AT32 and AT91 SPI Controllers
++ *
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/clk.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/spi/spi.h>
++
++#include <asm/io.h>
++#include <asm/arch/board.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/at91_pdc.h>
++
++#include "atmel_spi.h"
++
++#define spi_readl(port, reg) __raw_readl((port)->regs + (reg))
++#define spi_writel(port, reg, value) __raw_writel((value), (port)->regs + (reg))
++
++/*
++ * The core SPI transfer engine just talks to a register bank to set up
++ * DMA transfers; transfer queue progress is driven by IRQs. The clock
++ * framework provides the base clock, subdivided for each spi_device.
++ *
++ * Newer controllers, marked with "new_1" flag, have:
++ * - CR.LASTXFER
++ * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
++ * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
++ * - SPI_CSRx.CSAAT
++ * - SPI_CSRx.SBCR allows faster clocking
++ */
++struct atmel_spi {
++ spinlock_t lock;
++
++ void __iomem *regs;
++ int irq;
++ struct clk *clk;
++ struct platform_device *pdev;
++ unsigned new_1:1;
++
++ u8 stopping;
++ struct list_head queue;
++ struct spi_transfer *current_transfer;
++ unsigned long remaining_bytes;
++
++ void *buffer;
++ dma_addr_t buffer_dma;
++};
++
++#define BUFFER_SIZE PAGE_SIZE
++#define INVALID_DMA_ADDRESS 0xffffffff
++
++/*
++ * TODO: We really want to use the same GPIO API on both architectures.
++ */
++#ifdef CONFIG_ARM
++
++static inline int request_gpio(unsigned int pin)
++{
++ return 0;
++}
++
++static inline void free_gpio(unsigned int pin)
++{
++
++}
++
++static inline void gpio_set_value(unsigned int pin, int value)
++{
++ at91_set_gpio_value(pin, value);
++}
++
++static inline void gpio_set_output_enable(unsigned int pin, int enabled)
++{
++ at91_set_gpio_output(pin, enabled);
++}
++
++static inline void gpio_set_pullup_enable(unsigned int pin, int enabled)
++{
++
++}
++#endif
++
++/*
++ * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
++ * they assume that spi slave device state will not change on deselect, so
++ * that automagic deselection is OK. Not so! Workaround uses nCSx pins
++ * as GPIOs; or newer controllers have CSAAT and friends.
++ *
++ * Since the CSAAT functionality is a bit weird on newer controllers
++ * as well, we use GPIO to control nCSx pins on all controllers.
++ */
++
++static inline void cs_activate(struct spi_device *spi)
++{
++ unsigned gpio = (unsigned) spi->controller_data;
++
++ dev_dbg(&spi->dev, "activate %u\n", gpio);
++ gpio_set_value(gpio, 0);
++}
++
++static inline void cs_deactivate(struct spi_device *spi)
++{
++ unsigned gpio = (unsigned) spi->controller_data;
++
++ dev_dbg(&spi->dev, "DEactivate %u\n", gpio);
++ gpio_set_value(gpio, 1);
++}
++
++/*
++ * Submit next transfer for DMA.
++ * lock is held, spi irq is blocked
++ */
++static void atmel_spi_next_xfer(struct spi_master *master,
++ struct spi_message *msg)
++{
++ struct atmel_spi *as = spi_master_get_devdata(master);
++ struct spi_transfer *xfer;
++ u32 imr = 0;
++ u32 len;
++ dma_addr_t tx_dma, rx_dma;
++
++ xfer = as->current_transfer;
++ if (!xfer || as->remaining_bytes == 0) {
++ if (xfer)
++ xfer = list_entry(xfer->transfer_list.next,
++ struct spi_transfer, transfer_list);
++ else
++ xfer = list_entry(msg->transfers.next, struct spi_transfer,
++ transfer_list);
++ as->remaining_bytes = xfer->len;
++ as->current_transfer = xfer;
++ }
++
++ len = as->remaining_bytes;
++
++ tx_dma = xfer->tx_dma;
++ rx_dma = xfer->rx_dma;
++
++ if (rx_dma == INVALID_DMA_ADDRESS) {
++ rx_dma = as->buffer_dma;
++ if (len > BUFFER_SIZE)
++ len = BUFFER_SIZE;
++ }
++ if (tx_dma == INVALID_DMA_ADDRESS) {
++ if (xfer->tx_buf) {
++ tx_dma = as->buffer_dma;
++ if (len > BUFFER_SIZE)
++ len = BUFFER_SIZE;
++ memcpy(as->buffer, xfer->tx_buf, len);
++ dma_sync_single_for_device(&as->pdev->dev,
++ as->buffer_dma, len,
++ DMA_TO_DEVICE);
++ } else {
++ /* Send undefined data; rx_dma is handy */
++ tx_dma = rx_dma;
++ }
++ }
++
++ spi_writel(as, AT91_PDC_RPR, rx_dma);
++ spi_writel(as, AT91_PDC_TPR, tx_dma);
++
++ as->remaining_bytes -= len;
++ if (msg->spi->bits_per_word > 8)
++ len >>= 1;
++
++ /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
++ * mechanism might help avoid the IRQ latency between transfers
++ *
++ * We're also waiting for ENDRX before we start the next
++ * transfer because we need to handle some difficult timing
++ * issues otherwise. If we wait for ENDTX in one transfer and
++ * then starts waiting for ENDRX in the next, it's difficult
++ * to tell the difference between the ENDRX interrupt we're
++ * actually waiting for and the ENDRX interrupt of the
++ * previous transfer.
++ *
++ * It should be doable, though. Just not now...
++ */
++ spi_writel(as, AT91_PDC_TNCR, 0);
++ spi_writel(as, AT91_PDC_RNCR, 0);
++ imr = ATMEL_SPI_ENDRX;
++
++ dev_dbg(&msg->spi->dev,
++ "start xfer %p: len %u tx %p/%08x rx %p/%08x imr %08x\n",
++ xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
++ xfer->rx_buf, xfer->rx_dma, imr);
++
++ wmb();
++ spi_writel(as, AT91_PDC_TCR, len);
++ spi_writel(as, AT91_PDC_RCR, len);
++ spi_writel(as, AT91_PDC_PTCR, AT91_PDC_TXTEN | AT91_PDC_RXTEN);
++ spi_writel(as, ATMEL_SPI_IER, imr);
++}
++
++static void atmel_spi_next_message(struct spi_master *master)
++{
++ struct atmel_spi *as = spi_master_get_devdata(master);
++ struct spi_message *msg;
++ u32 mr;
++
++ BUG_ON(as->current_transfer);
++
++ msg = list_entry(as->queue.next, struct spi_message, queue);
++
++ /* Select the chip */
++ mr = spi_readl(as, ATMEL_SPI_MR) & ~ATMEL_SPI_PCS;
++ spi_writel(as, ATMEL_SPI_MR, mr | ATMEL_SPI_PCS_(msg->spi->chip_select));
++ cs_activate(msg->spi);
++
++ atmel_spi_next_xfer(master, msg);
++}
++
++static void atmel_spi_dma_map_xfer(struct atmel_spi *as,
++ struct spi_transfer *xfer)
++{
++ xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
++ if (!(xfer->len & (L1_CACHE_BYTES - 1))) {
++ if (xfer->tx_buf
++ && !((unsigned long)xfer->tx_buf & (L1_CACHE_BYTES - 1)))
++ xfer->tx_dma = dma_map_single(&as->pdev->dev,
++ xfer->tx_buf,
++ xfer->len,
++ DMA_TO_DEVICE);
++ if (xfer->rx_buf
++ && !((unsigned long)xfer->rx_buf & (L1_CACHE_BYTES - 1)))
++ xfer->rx_dma = dma_map_single(&as->pdev->dev,
++ xfer->rx_buf,
++ xfer->len,
++ DMA_FROM_DEVICE);
++ }
++}
++
++static irqreturn_t
++atmel_spi_interrupt(int irq, void *dev_id)
++{
++ struct spi_master *master = dev_id;
++ struct atmel_spi *as = spi_master_get_devdata(master);
++ struct spi_message *msg;
++ struct spi_transfer *xfer;
++ u32 status, pending, imr;
++ int ret = IRQ_NONE;
++
++ imr = spi_readl(as, ATMEL_SPI_IMR);
++ status = spi_readl(as, ATMEL_SPI_SR);
++ pending = status & imr;
++ pr_debug("spi irq: stat %05x imr %05x pend %05x\n", status, imr, pending);
++
++ if (pending & (ATMEL_SPI_ENDTX | ATMEL_SPI_ENDRX)) {
++ ret = IRQ_HANDLED;
++
++ spi_writel(as, ATMEL_SPI_IDR, pending);
++ spin_lock(&as->lock);
++
++ xfer = as->current_transfer;
++ msg = list_entry(as->queue.next, struct spi_message, queue);
++
++ /*
++ * If the rx buffer wasn't aligned, we used a bounce
++ * buffer for the transfer. Copy the data back and
++ * make the bounce buffer ready for re-use.
++ */
++ if (xfer->rx_buf && xfer->rx_dma == INVALID_DMA_ADDRESS) {
++ unsigned int len = xfer->len;
++ if (len > BUFFER_SIZE)
++ len = BUFFER_SIZE;
++
++ dma_sync_single_for_cpu(&as->pdev->dev, as->buffer_dma,
++ len, DMA_FROM_DEVICE);
++ memcpy((xfer->rx_buf + xfer->len
++ - len - as->remaining_bytes),
++ as->buffer, len);
++ }
++
++
++ if (as->remaining_bytes == 0) {
++ msg->actual_length += xfer->len;
++
++ if (!msg->is_dma_mapped) {
++ if (xfer->tx_dma != INVALID_DMA_ADDRESS)
++ dma_unmap_single(master->cdev.dev,
++ xfer->tx_dma,
++ xfer->len,
++ DMA_TO_DEVICE);
++ if (xfer->rx_dma != INVALID_DMA_ADDRESS)
++ dma_unmap_single(master->cdev.dev,
++ xfer->rx_dma,
++ xfer->len,
++ DMA_FROM_DEVICE);
++ }
++
++ /* REVISIT: udelay in irq is unfriendly */
++ if (xfer->delay_usecs)
++ udelay(xfer->delay_usecs);
++
++ if (msg->transfers.prev == &xfer->transfer_list) {
++
++ /* report completed message */
++ cs_deactivate(msg->spi);
++ list_del(&msg->queue);
++ msg->status = 0;
++
++ dev_dbg(master->cdev.dev,
++ "xfer complete: %u bytes transferred\n",
++ msg->actual_length);
++
++ spin_unlock(&as->lock);
++ msg->complete(msg->context);
++ spin_lock(&as->lock);
++
++ as->current_transfer = NULL;
++
++ /* continue; complete() may have queued requests */
++ if (list_empty(&as->queue) || as->stopping)
++ spi_writel(as, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
++ else
++ atmel_spi_next_message(master);
++ } else {
++ if (xfer->cs_change) {
++ cs_deactivate(msg->spi);
++ udelay(1);
++ cs_activate(msg->spi);
++ }
++
++ /*
++ * Not done yet. Submit the next transfer.
++ *
++ * FIXME handle protocol options for xfer
++ */
++ atmel_spi_next_xfer(master, msg);
++ }
++ } else {
++ /*
++ * Keep going, we still have data to send in
++ * the current transfer.
++ */
++ atmel_spi_next_xfer(master, msg);
++ }
++ spin_unlock(&as->lock);
++ }
++
++ return ret;
++}
++
++#define MAX_SCBR 0xff
++
++static int atmel_spi_setup(struct spi_device *spi)
++{
++ struct atmel_spi *as;
++ u32 scbr, csr;
++ unsigned int bits = spi->bits_per_word;
++ unsigned long bus_hz, sck_hz;
++ unsigned int npcs_pin;
++ int ret;
++
++ as = spi_master_get_devdata(spi->master);
++
++ if (as->stopping)
++ return -ESHUTDOWN;
++
++ if (spi->chip_select > spi->master->num_chipselect) {
++ dev_dbg(&spi->dev,
++ "setup: invalid chipselect %u (%u defined)\n",
++ spi->chip_select, spi->master->num_chipselect);
++ return -EINVAL;
++ }
++
++ if (bits == 0)
++ bits = 8;
++ if (bits < 8 || bits > 16) {
++ dev_dbg(&spi->dev,
++ "setup: invalid bits_per_word %u (8 to 16)\n",
++ bits);
++ return -EINVAL;
++ }
++
++ if (spi->mode & (SPI_CS_HIGH | SPI_LSB_FIRST)) {
++ dev_dbg(&spi->dev, "setup: unsupported mode %u\n", spi->mode);
++ return -EINVAL;
++ }
++
++ /* speed zero convention is used by some upper layers */
++ bus_hz = clk_get_rate(as->clk);
++ if (spi->max_speed_hz) {
++ /* assume div32/fdiv/mbz == 0 */
++ if (!as->new_1)
++ bus_hz /= 2;
++ scbr = ((bus_hz + spi->max_speed_hz - 1)
++ / spi->max_speed_hz);
++ if (scbr > MAX_SCBR) {
++ dev_dbg(&spi->dev, "setup: %d Hz too slow, scbr %u\n",
++ spi->max_speed_hz, scbr);
++ return -EINVAL;
++ }
++ } else
++ scbr = 0xff;
++ sck_hz = bus_hz / scbr;
++
++ csr = ATMEL_SPI_SCBR_(scbr) | ATMEL_SPI_BITS_(bits);
++ if (spi->mode & SPI_CPOL)
++ csr |= ATMEL_SPI_CPOL;
++ if (!(spi->mode & SPI_CPHA))
++ csr |= ATMEL_SPI_NCPHA;
++
++ /* TODO: DLYBS and DLYBCT */
++ csr |= ATMEL_SPI_DLYBS_(10);
++ csr |= ATMEL_SPI_DLYBCT_(10);
++
++ npcs_pin = (unsigned int)spi->controller_data;
++ if (!spi->controller_state) {
++ ret = request_gpio(npcs_pin);
++ if (ret)
++ return ret;
++ spi->controller_state = (void *)npcs_pin;
++ }
++
++ gpio_set_value(npcs_pin, 1);
++ gpio_set_output_enable(npcs_pin, 1);
++ gpio_set_pullup_enable(npcs_pin, 0);
++
++ dev_dbg(&spi->dev,
++ "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
++ sck_hz, bits, spi->mode, spi->chip_select, csr);
++
++ spi_writel(as, ATMEL_SPI_CSR(spi->chip_select), csr);
++
++ return 0;
++}
++
++static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
++{
++ struct atmel_spi *as;
++ struct spi_transfer *xfer;
++ unsigned long flags;
++ struct device *controller = spi->master->cdev.dev;
++
++ as = spi_master_get_devdata(spi->master);
++
++ dev_dbg(controller, "new message %p submitted for %s\n",
++ msg, spi->dev.bus_id);
++
++ if (unlikely(list_empty(&msg->transfers)
++ || !spi->max_speed_hz))
++ return -EINVAL;
++
++ if (as->stopping)
++ return -ESHUTDOWN;
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ if (!(xfer->tx_buf || xfer->rx_buf)) {
++ dev_dbg(&spi->dev, "missing rx or tx buf\n");
++ return -EINVAL;
++ }
++
++ /* FIXME implement these protocol options!! */
++ if (xfer->bits_per_word || xfer->speed_hz) {
++ dev_dbg(&spi->dev, "no protocol options yet\n");
++ return -ENOPROTOOPT;
++ }
++ }
++
++ /* scrub dcache "early" */
++ if (!msg->is_dma_mapped) {
++ list_for_each_entry(xfer, &msg->transfers, transfer_list)
++ atmel_spi_dma_map_xfer(as, xfer);
++ }
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ dev_dbg(controller,
++ " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
++ xfer, xfer->len,
++ xfer->tx_buf, xfer->tx_dma,
++ xfer->rx_buf, xfer->rx_dma);
++ }
++
++ msg->status = -EINPROGRESS;
++ msg->actual_length = 0;
++
++ spin_lock_irqsave(&as->lock, flags);
++ list_add_tail(&msg->queue, &as->queue);
++ if (!as->current_transfer)
++ atmel_spi_next_message(spi->master);
++ spin_unlock_irqrestore(&as->lock, flags);
++
++ return 0;
++}
++
++static void atmel_spi_cleanup(const struct spi_device *spi)
++{
++ if (spi->controller_state)
++ free_gpio((unsigned int)spi->controller_data);
++}
++
++/*-------------------------------------------------------------------------*/
++
++static int __devinit atmel_spi_probe(struct platform_device *pdev)
++{
++ struct resource *regs;
++ int irq;
++ struct clk *clk;
++ int ret = -ENOMEM;
++ struct spi_master *master;
++ struct atmel_spi *as;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs)
++ return -ENXIO;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return irq;
++
++ clk = clk_get(&pdev->dev, "spi_clk");
++ if (IS_ERR(clk))
++ return PTR_ERR(clk);
++
++ /* setup spi core then atmel-specific driver state */
++ master = spi_alloc_master(&pdev->dev, sizeof *as);
++ if (!master)
++ goto out_free;
++
++ master->bus_num = pdev->id;
++ master->num_chipselect = 4;
++ master->setup = atmel_spi_setup;
++ master->transfer = atmel_spi_transfer;
++ master->cleanup = atmel_spi_cleanup;
++ platform_set_drvdata(pdev, master);
++
++ as = spi_master_get_devdata(master);
++
++ as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
++ &as->buffer_dma, GFP_KERNEL);
++ if (!as->buffer)
++ goto out_free;
++
++ spin_lock_init(&as->lock);
++ INIT_LIST_HEAD(&as->queue);
++ as->pdev = pdev;
++ as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
++ if (!as->regs)
++ goto out_free_buffer;
++ as->irq = irq;
++ as->clk = clk;
++#if !defined(CONFIG_ARCH_AT91RM9200)
++ /* if (!cpu_is_at91rm9200()) */
++ as->new_1 = 1;
++#endif
++
++ ret = request_irq(irq, atmel_spi_interrupt, 0,
++ pdev->dev.bus_id, master);
++ if (ret)
++ goto out_unmap_regs;
++
++ /* Initialize the hardware */
++ clk_enable(clk);
++ spi_writel(as, ATMEL_SPI_CR, ATMEL_SPI_SWRST);
++ spi_writel(as, ATMEL_SPI_MR, ATMEL_SPI_MSTR | ATMEL_SPI_MODFDIS);
++ spi_writel(as, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
++ spi_writel(as, ATMEL_SPI_CR, ATMEL_SPI_SPIEN);
++
++ /* go! */
++ dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
++ (unsigned long)regs->start, irq);
++
++ ret = spi_register_master(master);
++ if (ret)
++ goto out_reset_hw;
++
++ return 0;
++
++out_reset_hw:
++ spi_writel(as, ATMEL_SPI_CR, ATMEL_SPI_SWRST);
++ clk_disable(clk);
++ free_irq(irq, master);
++out_unmap_regs:
++ iounmap(as->regs);
++out_free_buffer:
++ dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
++ as->buffer_dma);
++out_free:
++ clk_put(clk);
++ spi_master_put(master);
++ return ret;
++}
++
++static int __devexit atmel_spi_remove(struct platform_device *pdev)
++{
++ struct spi_master *master = platform_get_drvdata(pdev);
++ struct atmel_spi *as = spi_master_get_devdata(master);
++ struct spi_message *msg;
++
++ /* reset the hardware and block queue progress */
++ spin_lock_irq(&as->lock);
++ as->stopping = 1;
++ spi_writel(as, ATMEL_SPI_CR, ATMEL_SPI_SWRST);
++ spi_readl(as, ATMEL_SPI_SR);
++ spin_unlock_irq(&as->lock);
++
++ /* Terminate remaining queued transfers */
++ list_for_each_entry(msg, &as->queue, queue) {
++ /* REVISIT unmapping the dma is sort of a NOP on ARM,
++ * but we shouldn't depend on that...
++ */
++ msg->status = -ESHUTDOWN;
++ msg->complete(msg->context);
++ }
++
++ dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
++ as->buffer_dma);
++
++ clk_disable(as->clk);
++ clk_put(as->clk);
++ free_irq(as->irq, master);
++ iounmap(as->regs);
++
++ spi_unregister_master(master);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++
++static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
++{
++ struct spi_master *master = platform_get_drvdata(pdev);
++ struct atmel_spi *as = spi_master_get_devdata(master);
++
++ clk_disable(as->clk);
++ return 0;
++}
++
++static int atmel_spi_resume(struct platform_device *pdev)
++{
++ struct spi_master *master = platform_get_drvdata(pdev);
++ struct atmel_spi *as = spi_master_get_devdata(master);
++
++ clk_enable(as->clk);
++ return 0;
++}
++
++#else
++#define atmel_spi_suspend NULL
++#define atmel_spi_resume NULL
++#endif
++
++
++static struct platform_driver atmel_spi_driver = {
++ .driver = {
++ .name = "atmel_spi",
++ .owner = THIS_MODULE,
++ },
++ .probe = atmel_spi_probe,
++ .suspend = atmel_spi_suspend,
++ .resume = atmel_spi_resume,
++ .remove = __devexit_p(atmel_spi_remove),
++};
++
++static int __init atmel_spi_init(void)
++{
++ return platform_driver_register(&atmel_spi_driver);
++}
++module_init(atmel_spi_init);
++
++static void __exit atmel_spi_exit(void)
++{
++ platform_driver_unregister(&atmel_spi_driver);
++}
++module_exit(atmel_spi_exit);
++
++MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
++MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
++MODULE_LICENSE("GPL");
+diff -urN -x CVS linux-2.6.19-final/drivers/spi/atmel_spi.h linux-2.6.19/drivers/spi/atmel_spi.h
+--- linux-2.6.19-final/drivers/spi/atmel_spi.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/spi/atmel_spi.h Wed Nov 15 16:40:00 2006
+@@ -0,0 +1,86 @@
++/*
++ * drivers/spi/atmel_spi.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Serial Peripheral Interface (SPI) registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef ATMEL_SPI_H
++#define ATMEL_SPI_H
++
++#define ATMEL_SPI_CR 0x00 /* Control Register */
++#define ATMEL_SPI_SPIEN (1 << 0) /* SPI Enable */
++#define ATMEL_SPI_SPIDIS (1 << 1) /* SPI Disable */
++#define ATMEL_SPI_SWRST (1 << 7) /* SPI Software Reset */
++#define ATMEL_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
++
++#define ATMEL_SPI_MR 0x04 /* Mode Register */
++#define ATMEL_SPI_MSTR (1 << 0) /* Master/Slave Mode */
++#define ATMEL_SPI_PS (1 << 1) /* Peripheral Select */
++#define ATMEL_SPI_PS_FIXED (0 << 1)
++#define ATMEL_SPI_PS_VARIABLE (1 << 1)
++#define ATMEL_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
++#define ATMEL_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
++#define ATMEL_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
++#define ATMEL_SPI_LLB (1 << 7) /* Local Loopback Enable */
++#define ATMEL_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
++#define ATMEL_SPI_PCS_(x) (~(1 << (x+16)) & ATMEL_SPI_PCS)
++#define ATMEL_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
++
++#define ATMEL_SPI_RDR 0x08 /* Receive Data Register */
++#define ATMEL_SPI_RD (0xffff << 0) /* Receive Data */
++#define ATMEL_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
++
++#define ATMEL_SPI_TDR 0x0c /* Transmit Data Register */
++#define ATMEL_SPI_TD (0xffff << 0) /* Transmit Data */
++#define ATMEL_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
++#define ATMEL_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
++
++#define ATMEL_SPI_SR 0x10 /* Status Register */
++#define ATMEL_SPI_RDRF (1 << 0) /* Receive Data Register Full */
++#define ATMEL_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
++#define ATMEL_SPI_MODF (1 << 2) /* Mode Fault Error */
++#define ATMEL_SPI_OVRES (1 << 3) /* Overrun Error Status */
++#define ATMEL_SPI_ENDRX (1 << 4) /* End of RX buffer */
++#define ATMEL_SPI_ENDTX (1 << 5) /* End of TX buffer */
++#define ATMEL_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
++#define ATMEL_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
++#define ATMEL_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
++#define ATMEL_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
++#define ATMEL_SPI_SPIENS (1 << 16) /* SPI Enable Status */
++
++#define ATMEL_SPI_IER 0x14 /* Interrupt Enable Register */
++#define ATMEL_SPI_IDR 0x18 /* Interrupt Disable Register */
++#define ATMEL_SPI_IMR 0x1c /* Interrupt Mask Register */
++
++#define ATMEL_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
++#define ATMEL_SPI_CPOL (1 << 0) /* Clock Polarity */
++#define ATMEL_SPI_NCPHA (1 << 1) /* Clock Phase */
++#define ATMEL_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
++#define ATMEL_SPI_BITS (0xf << 4) /* Bits Per Transfer */
++#define ATMEL_SPI_BITS_8 (0 << 4)
++#define ATMEL_SPI_BITS_9 (1 << 4)
++#define ATMEL_SPI_BITS_10 (2 << 4)
++#define ATMEL_SPI_BITS_11 (3 << 4)
++#define ATMEL_SPI_BITS_12 (4 << 4)
++#define ATMEL_SPI_BITS_13 (5 << 4)
++#define ATMEL_SPI_BITS_14 (6 << 4)
++#define ATMEL_SPI_BITS_15 (7 << 4)
++#define ATMEL_SPI_BITS_16 (8 << 4)
++#define ATMEL_SPI_BITS_(x) ((x - 8) << 4)
++#define ATMEL_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
++#define ATMEL_SPI_SCBR_(x) ((x) << 8)
++#define ATMEL_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
++#define ATMEL_SPI_DLYBS_(x) ((x) << 16)
++#define ATMEL_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
++#define ATMEL_SPI_DLYBCT_(x) ((x) << 24)
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/drivers/spi/spi_at91_bitbang.c linux-2.6.19/drivers/spi/spi_at91_bitbang.c
+--- linux-2.6.19-final/drivers/spi/spi_at91_bitbang.c Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/drivers/spi/spi_at91_bitbang.c Thu Oct 12 17:07:39 2006
+@@ -0,0 +1,207 @@
++/*
++ * at91_spi.c - at91 SPI driver (BOOTSTRAP/BITBANG VERSION)
++ *
++ * Copyright (C) 2006 David Brownell
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++
++#include <linux/spi/spi.h>
++#include <linux/spi/spi_bitbang.h>
++
++#include <asm/arch/gpio.h>
++
++
++/*
++ * FIXME this bitbanging version is just to help bootstrap systems until
++ * there's a native SPI+IRQ+DMA controller driver ... such a driver should
++ * be a drop-in replacement for this one, and much faster.
++ *
++ * remember:
++ *
++ * - other at91 parts (like at91sam9) have multiple controllers
++ * and different pin muxing; this version is at91rm9200 specfic.
++ *
++ * - at91sam9261 SPI0 pins are directly muxed with MMC/SD pins.
++ *
++ * - rm9200 spi chipselects drop wrongly, so the native driver
++ * will need to use gpios much like this does.
++ *
++ * - real hardware only allows 8..16 bits per word, while this
++ * bitbanger allows 1..32 (incompatible superset).
++ *
++ * - this disregards clock parameters. with inlined gpio calls,
++ * gcc 3.4.4 produces about 1.5 mbit/sec, more than 2x faster
++ * than using the subroutined veresion from txrx_word().
++ *
++ * - suspend/resume and <linux/clk.h> support is missing ...
++ */
++
++#define spi_miso_bit AT91_PIN_PA0
++#define spi_mosi_bit AT91_PIN_PA1
++#define spi_sck_bit AT91_PIN_PA2
++
++struct at91_spi {
++ struct spi_bitbang bitbang;
++ struct platform_device *pdev;
++};
++
++/*----------------------------------------------------------------------*/
++
++static inline void setsck(struct spi_device *spi, int is_on)
++{
++ at91_set_gpio_value(spi_sck_bit, is_on);
++}
++
++static inline void setmosi(struct spi_device *spi, int is_on)
++{
++ at91_set_gpio_value(spi_mosi_bit, is_on);
++}
++
++static inline int getmiso(struct spi_device *spi)
++{
++ return at91_get_gpio_value(spi_miso_bit);
++}
++
++static void at91_spi_chipselect(struct spi_device *spi, int is_active)
++{
++ unsigned long cs = (unsigned long) spi->controller_data;
++
++ /* set default clock polarity */
++ if (is_active)
++ setsck(spi, spi->mode & SPI_CPOL);
++
++ /* only support active-low (default) */
++ at91_set_gpio_value(cs, !is_active);
++}
++
++/*
++ * NOTE: this is "as fast as we can"; it should be a function of
++ * the device clock ...
++ */
++#define spidelay(X) do{} while(0)
++
++#define EXPAND_BITBANG_TXRX
++#include <linux/spi/spi_bitbang.h>
++
++static u32 at91_spi_txrx_word_mode0(struct spi_device *spi,
++ unsigned nsecs, u32 word, u8 bits)
++{
++ return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, 8);
++}
++
++static u32 at91_spi_txrx_word_mode1(struct spi_device *spi,
++ unsigned nsecs, u32 word, u8 bits)
++{
++ return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, 8);
++}
++
++static u32 at91_spi_txrx_word_mode2(struct spi_device *spi,
++ unsigned nsecs, u32 word, u8 bits)
++{
++ return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, 8);
++}
++
++static u32 at91_spi_txrx_word_mode3(struct spi_device *spi,
++ unsigned nsecs, u32 word, u8 bits)
++{
++ return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, 8);
++}
++
++/*----------------------------------------------------------------------*/
++
++static int __init at91_spi_probe(struct platform_device *pdev)
++{
++ int status;
++ struct spi_master *master;
++ struct at91_spi *at91_spi;
++
++ if (pdev->id != 0) /* SPI0 bus */
++ return -EINVAL;
++
++ master = spi_alloc_master(&pdev->dev, sizeof *at91_spi);
++ if (!master)
++ return -ENOMEM;
++
++ at91_spi = spi_master_get_devdata(master);
++ at91_spi->pdev = pdev;
++ platform_set_drvdata(pdev, at91_spi);
++
++ /* SPI and bitbang hookup */
++ master->bus_num = 0;
++ master->num_chipselect = 4;
++
++ at91_spi->bitbang.master = spi_master_get(master);
++ at91_spi->bitbang.chipselect = at91_spi_chipselect;
++ at91_spi->bitbang.txrx_word[SPI_MODE_0] = at91_spi_txrx_word_mode0;
++ at91_spi->bitbang.txrx_word[SPI_MODE_1] = at91_spi_txrx_word_mode1;
++ at91_spi->bitbang.txrx_word[SPI_MODE_2] = at91_spi_txrx_word_mode2;
++ at91_spi->bitbang.txrx_word[SPI_MODE_3] = at91_spi_txrx_word_mode3;
++
++ status = spi_bitbang_start(&at91_spi->bitbang);
++ if (status < 0)
++ (void) spi_master_put(at91_spi->bitbang.master);
++
++ return status;
++}
++
++static int __exit at91_spi_remove(struct platform_device *pdev)
++{
++ struct at91_spi *at91_spi = platform_get_drvdata(pdev);
++ int status;
++
++ /* stop() unregisters child devices too */
++ status = spi_bitbang_stop(&at91_spi->bitbang);
++ (void) spi_master_put(at91_spi->bitbang.master);
++
++ platform_set_drvdata(pdev, NULL);
++ return status;
++}
++
++static struct platform_driver at91_spi_driver = {
++ .probe = at91_spi_probe,
++ .remove = __exit_p(at91_spi_remove),
++ .driver = {
++ .name = "at91_spi",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init at91_spi_init(void)
++{
++ at91_set_gpio_output(spi_sck_bit, 0);
++ at91_set_gpio_output(spi_mosi_bit, 0);
++ at91_set_gpio_input(spi_miso_bit, 1 /* pullup */);
++
++ /* register driver */
++ return platform_driver_register(&at91_spi_driver);
++}
++
++static void __exit at91_spi_exit(void)
++{
++ platform_driver_unregister(&at91_spi_driver);
++}
++
++device_initcall(at91_spi_init);
++module_exit(at91_spi_exit);
++
++MODULE_ALIAS("at91_spi.0");
++
++MODULE_DESCRIPTION("AT91 SPI support (BOOTSTRAP/BITBANG VERSION)");
++MODULE_AUTHOR("David Brownell");
++MODULE_LICENSE("GPL");
+diff -urN -x CVS linux-2.6.19-final/drivers/usb/Kconfig linux-2.6.19/drivers/usb/Kconfig
+--- linux-2.6.19-final/drivers/usb/Kconfig Mon Dec 4 16:40:49 2006
++++ linux-2.6.19/drivers/usb/Kconfig Thu Oct 12 17:07:39 2006
+@@ -24,7 +24,7 @@
+ default y if ARCH_S3C2410
+ default y if PXA27x
+ default y if ARCH_EP93XX
+- default y if (ARCH_AT91RM9200 || ARCH_AT91SAM9261)
++ default y if ARCH_AT91
+ default y if ARCH_PNX4008
+ # PPC:
+ default y if STB03xxx
+diff -urN -x CVS linux-2.6.19-final/drivers/usb/gadget/Kconfig linux-2.6.19/drivers/usb/gadget/Kconfig
+--- linux-2.6.19-final/drivers/usb/gadget/Kconfig Mon Dec 4 16:40:49 2006
++++ linux-2.6.19/drivers/usb/gadget/Kconfig Thu Oct 12 17:07:39 2006
+@@ -189,7 +189,7 @@
+
+ config USB_GADGET_AT91
+ boolean "AT91 USB Device Port"
+- depends on ARCH_AT91RM9200
++ depends on ARCH_AT91
+ select USB_GADGET_SELECTED
+ help
+ Many Atmel AT91 processors (such as the AT91RM2000) have a
+diff -urN -x CVS linux-2.6.19-final/drivers/usb/gadget/at91_udc.c linux-2.6.19/drivers/usb/gadget/at91_udc.c
+--- linux-2.6.19-final/drivers/usb/gadget/at91_udc.c Mon Dec 4 16:40:49 2006
++++ linux-2.6.19/drivers/usb/gadget/at91_udc.c Wed Nov 15 11:33:30 2006
+@@ -43,14 +43,16 @@
+ #include <linux/usb_gadget.h>
+
+ #include <asm/byteorder.h>
++#include <asm/hardware.h>
+ #include <asm/io.h>
+ #include <asm/irq.h>
+ #include <asm/system.h>
+ #include <asm/mach-types.h>
+
+-#include <asm/arch/hardware.h>
+ #include <asm/arch/gpio.h>
+ #include <asm/arch/board.h>
++#include <asm/arch/cpu.h>
++#include <asm/arch/at91sam9261_matrix.h>
+
+ #include "at91_udc.h"
+
+@@ -78,27 +80,9 @@
+ static const char driver_name [] = "at91_udc";
+ static const char ep0name[] = "ep0";
+
+-/*-------------------------------------------------------------------------*/
+
+-/*
+- * Read from a UDP register.
+- */
+-static inline unsigned long at91_udp_read(unsigned int reg)
+-{
+- void __iomem *udp_base = (void __iomem *)AT91_VA_BASE_UDP;
+-
+- return __raw_readl(udp_base + reg);
+-}
+-
+-/*
+- * Write to a UDP register.
+- */
+-static inline void at91_udp_write(unsigned int reg, unsigned long value)
+-{
+- void __iomem *udp_base = (void __iomem *)AT91_VA_BASE_UDP;
+-
+- __raw_writel(value, udp_base + reg);
+-}
++#define at91_udp_read(dev, reg) __raw_readl((dev)->udp_baseaddr + (reg))
++#define at91_udp_write(dev, reg, val) __raw_writel((val), (dev)->udp_baseaddr + (reg))
+
+ /*-------------------------------------------------------------------------*/
+
+@@ -210,13 +194,13 @@
+ return 0;
+ }
+
+- tmp = at91_udp_read(AT91_UDP_FRM_NUM);
++ tmp = at91_udp_read(udc, AT91_UDP_FRM_NUM);
+ seq_printf(s, "frame %05x:%s%s frame=%d\n", tmp,
+ (tmp & AT91_UDP_FRM_OK) ? " ok" : "",
+ (tmp & AT91_UDP_FRM_ERR) ? " err" : "",
+ (tmp & AT91_UDP_NUM));
+
+- tmp = at91_udp_read(AT91_UDP_GLB_STAT);
++ tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
+ seq_printf(s, "glbstate %02x:%s" FOURBITS "\n", tmp,
+ (tmp & AT91_UDP_RMWUPE) ? " rmwupe" : "",
+ (tmp & AT91_UDP_RSMINPR) ? " rsminpr" : "",
+@@ -224,13 +208,13 @@
+ (tmp & AT91_UDP_CONFG) ? " confg" : "",
+ (tmp & AT91_UDP_FADDEN) ? " fadden" : "");
+
+- tmp = at91_udp_read(AT91_UDP_FADDR);
++ tmp = at91_udp_read(udc, AT91_UDP_FADDR);
+ seq_printf(s, "faddr %03x:%s fadd=%d\n", tmp,
+ (tmp & AT91_UDP_FEN) ? " fen" : "",
+ (tmp & AT91_UDP_FADD));
+
+- proc_irq_show(s, "imr ", at91_udp_read(AT91_UDP_IMR));
+- proc_irq_show(s, "isr ", at91_udp_read(AT91_UDP_ISR));
++ proc_irq_show(s, "imr ", at91_udp_read(udc, AT91_UDP_IMR));
++ proc_irq_show(s, "isr ", at91_udp_read(udc, AT91_UDP_ISR));
+
+ if (udc->enabled && udc->vbus) {
+ proc_ep_show(s, &udc->ep[0]);
+@@ -286,6 +270,7 @@
+ static void done(struct at91_ep *ep, struct at91_request *req, int status)
+ {
+ unsigned stopped = ep->stopped;
++ struct at91_udc *udc = ep->udc;
+
+ list_del_init(&req->queue);
+ if (req->req.status == -EINPROGRESS)
+@@ -300,8 +285,8 @@
+ ep->stopped = stopped;
+
+ /* ep0 is always ready; other endpoints need a non-empty queue */
+- if (list_empty(&ep->queue) && ep->int_mask != (1 << 0))
+- at91_udp_write(AT91_UDP_IDR, ep->int_mask);
++ if (list_empty(&ep->queue) && (ep->id != 0))
++ at91_udp_write(udc, AT91_UDP_IDR, 1 << ep->id);
+ }
+
+ /*-------------------------------------------------------------------------*/
+@@ -554,8 +539,8 @@
+ * reset/init endpoint fifo. NOTE: leaves fifo_bank alone,
+ * since endpoint resets don't reset hw pingpong state.
+ */
+- at91_udp_write(AT91_UDP_RST_EP, ep->int_mask);
+- at91_udp_write(AT91_UDP_RST_EP, 0);
++ at91_udp_write(dev, AT91_UDP_RST_EP, 1 << ep->id);
++ at91_udp_write(dev, AT91_UDP_RST_EP, 0);
+
+ local_irq_restore(flags);
+ return 0;
+@@ -564,6 +549,7 @@
+ static int at91_ep_disable (struct usb_ep * _ep)
+ {
+ struct at91_ep *ep = container_of(_ep, struct at91_ep, ep);
++ struct at91_udc *udc = ep->udc;
+ unsigned long flags;
+
+ if (ep == &ep->udc->ep[0])
+@@ -579,8 +565,8 @@
+
+ /* reset fifos and endpoint */
+ if (ep->udc->clocked) {
+- at91_udp_write(AT91_UDP_RST_EP, ep->int_mask);
+- at91_udp_write(AT91_UDP_RST_EP, 0);
++ at91_udp_write(udc, AT91_UDP_RST_EP, 1 << ep->id);
++ at91_udp_write(udc, AT91_UDP_RST_EP, 0);
+ __raw_writel(0, ep->creg);
+ }
+
+@@ -695,10 +681,10 @@
+ * reconfigures the endpoints.
+ */
+ if (dev->wait_for_config_ack) {
+- tmp = at91_udp_read(AT91_UDP_GLB_STAT);
++ tmp = at91_udp_read(dev, AT91_UDP_GLB_STAT);
+ tmp ^= AT91_UDP_CONFG;
+ VDBG("toggle config\n");
+- at91_udp_write(AT91_UDP_GLB_STAT, tmp);
++ at91_udp_write(dev, AT91_UDP_GLB_STAT, tmp);
+ }
+ if (req->req.length == 0) {
+ ep0_in_status:
+@@ -727,7 +713,7 @@
+
+ if (req && !status) {
+ list_add_tail (&req->queue, &ep->queue);
+- at91_udp_write(AT91_UDP_IER, ep->int_mask);
++ at91_udp_write(dev, AT91_UDP_IER, 1 << ep->id);
+ }
+ done:
+ local_irq_restore(flags);
+@@ -758,6 +744,7 @@
+ static int at91_ep_set_halt(struct usb_ep *_ep, int value)
+ {
+ struct at91_ep *ep = container_of(_ep, struct at91_ep, ep);
++ struct at91_udc *udc = ep->udc;
+ u32 __iomem *creg;
+ u32 csr;
+ unsigned long flags;
+@@ -785,8 +772,8 @@
+ csr |= AT91_UDP_FORCESTALL;
+ VDBG("halt %s\n", ep->ep.name);
+ } else {
+- at91_udp_write(AT91_UDP_RST_EP, ep->int_mask);
+- at91_udp_write(AT91_UDP_RST_EP, 0);
++ at91_udp_write(udc, AT91_UDP_RST_EP, 1 << ep->id);
++ at91_udp_write(udc, AT91_UDP_RST_EP, 0);
+ csr &= ~AT91_UDP_FORCESTALL;
+ }
+ __raw_writel(csr, creg);
+@@ -813,9 +800,11 @@
+
+ static int at91_get_frame(struct usb_gadget *gadget)
+ {
++ struct at91_udc *udc = to_udc(gadget);
++
+ if (!to_udc(gadget)->clocked)
+ return -EINVAL;
+- return at91_udp_read(AT91_UDP_FRM_NUM) & AT91_UDP_NUM;
++ return at91_udp_read(udc, AT91_UDP_FRM_NUM) & AT91_UDP_NUM;
+ }
+
+ static int at91_wakeup(struct usb_gadget *gadget)
+@@ -833,11 +822,11 @@
+
+ /* NOTE: some "early versions" handle ESR differently ... */
+
+- glbstate = at91_udp_read(AT91_UDP_GLB_STAT);
++ glbstate = at91_udp_read(udc, AT91_UDP_GLB_STAT);
+ if (!(glbstate & AT91_UDP_ESR))
+ goto done;
+ glbstate |= AT91_UDP_ESR;
+- at91_udp_write(AT91_UDP_GLB_STAT, glbstate);
++ at91_udp_write(udc, AT91_UDP_GLB_STAT, glbstate);
+
+ done:
+ local_irq_restore(flags);
+@@ -861,6 +850,7 @@
+ ep->stopped = 0;
+ ep->fifo_bank = 0;
+ ep->ep.maxpacket = ep->maxpacket;
++ ep->creg = (void __iomem *) udc->udp_baseaddr + AT91_UDP_CSR(i);
+ // initialiser une queue par endpoint
+ INIT_LIST_HEAD(&ep->queue);
+ }
+@@ -915,14 +905,25 @@
+ if (!udc->enabled || !udc->vbus)
+ is_on = 0;
+ DBG("%sactive\n", is_on ? "" : "in");
++
+ if (is_on) {
+ clk_on(udc);
+- at91_udp_write(AT91_UDP_TXVC, 0);
+- at91_set_gpio_value(udc->board.pullup_pin, 1);
+- } else {
++ at91_udp_write(udc, AT91_UDP_TXVC, 0);
++ if (cpu_is_at91rm9200())
++ at91_set_gpio_value(udc->board.pullup_pin, 1);
++ else if (cpu_is_at91sam9260())
++ at91_udp_write(udc, AT91_UDP_TXVC, (at91_udp_read(udc, AT91_UDP_TXVC) | AT91_UDP_TXVC_PUON));
++ else if (cpu_is_at91sam9261())
++ at91_sys_write(AT91_MATRIX_USBPUCR, (at91_sys_read(AT91_MATRIX_USBPUCR) | AT91_MATRIX_USBPUCR_PUON));
++ } else {
+ stop_activity(udc);
+- at91_udp_write(AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
+- at91_set_gpio_value(udc->board.pullup_pin, 0);
++ at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
++ if (cpu_is_at91rm9200())
++ at91_set_gpio_value(udc->board.pullup_pin, 0);
++ else if (cpu_is_at91sam9260())
++ at91_udp_write(udc, AT91_UDP_TXVC, (at91_udp_read(udc, AT91_UDP_TXVC) & ~AT91_UDP_TXVC_PUON));
++ else if (cpu_is_at91sam9261())
++ at91_sys_write(AT91_MATRIX_USBPUCR, (at91_sys_read(AT91_MATRIX_USBPUCR) & ~AT91_MATRIX_USBPUCR_PUON));
+ clk_off(udc);
+ }
+ }
+@@ -1086,7 +1087,7 @@
+
+ case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8)
+ | USB_REQ_SET_CONFIGURATION:
+- tmp = at91_udp_read(AT91_UDP_GLB_STAT) & AT91_UDP_CONFG;
++ tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_CONFG;
+ if (pkt.r.wValue)
+ udc->wait_for_config_ack = (tmp == 0);
+ else
+@@ -1103,7 +1104,7 @@
+ case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8)
+ | USB_REQ_GET_STATUS:
+ tmp = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
+- if (at91_udp_read(AT91_UDP_GLB_STAT) & AT91_UDP_ESR)
++ if (at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_ESR)
+ tmp |= (1 << USB_DEVICE_REMOTE_WAKEUP);
+ PACKET("get device status\n");
+ __raw_writeb(tmp, dreg);
+@@ -1114,17 +1115,17 @@
+ | USB_REQ_SET_FEATURE:
+ if (w_value != USB_DEVICE_REMOTE_WAKEUP)
+ goto stall;
+- tmp = at91_udp_read(AT91_UDP_GLB_STAT);
++ tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
+ tmp |= AT91_UDP_ESR;
+- at91_udp_write(AT91_UDP_GLB_STAT, tmp);
++ at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp);
+ goto succeed;
+ case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8)
+ | USB_REQ_CLEAR_FEATURE:
+ if (w_value != USB_DEVICE_REMOTE_WAKEUP)
+ goto stall;
+- tmp = at91_udp_read(AT91_UDP_GLB_STAT);
++ tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
+ tmp &= ~AT91_UDP_ESR;
+- at91_udp_write(AT91_UDP_GLB_STAT, tmp);
++ at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp);
+ goto succeed;
+
+ /*
+@@ -1206,8 +1207,8 @@
+ } else if (ep->is_in)
+ goto stall;
+
+- at91_udp_write(AT91_UDP_RST_EP, ep->int_mask);
+- at91_udp_write(AT91_UDP_RST_EP, 0);
++ at91_udp_write(udc, AT91_UDP_RST_EP, 1 << ep->id);
++ at91_udp_write(udc, AT91_UDP_RST_EP, 0);
+ tmp = __raw_readl(ep->creg);
+ tmp |= CLR_FX;
+ tmp &= ~(SET_FX | AT91_UDP_FORCESTALL);
+@@ -1300,13 +1301,13 @@
+ if (udc->wait_for_addr_ack) {
+ u32 tmp;
+
+- at91_udp_write(AT91_UDP_FADDR,
++ at91_udp_write(udc, AT91_UDP_FADDR,
+ AT91_UDP_FEN | udc->addr);
+- tmp = at91_udp_read(AT91_UDP_GLB_STAT);
++ tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
+ tmp &= ~AT91_UDP_FADDEN;
+ if (udc->addr)
+ tmp |= AT91_UDP_FADDEN;
+- at91_udp_write(AT91_UDP_GLB_STAT, tmp);
++ at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp);
+
+ udc->wait_for_addr_ack = 0;
+ VDBG("address %d\n", udc->addr);
+@@ -1374,28 +1375,28 @@
+ while (rescans--) {
+ u32 status;
+
+- status = at91_udp_read(AT91_UDP_ISR)
+- & at91_udp_read(AT91_UDP_IMR);
++ status = at91_udp_read(udc, AT91_UDP_ISR)
++ & at91_udp_read(udc, AT91_UDP_IMR);
+ if (!status)
+ break;
+
+ /* USB reset irq: not maskable */
+ if (status & AT91_UDP_ENDBUSRES) {
+- at91_udp_write(AT91_UDP_IDR, ~MINIMUS_INTERRUPTUS);
+- at91_udp_write(AT91_UDP_IER, MINIMUS_INTERRUPTUS);
++ at91_udp_write(udc, AT91_UDP_IDR, ~MINIMUS_INTERRUPTUS);
++ at91_udp_write(udc, AT91_UDP_IER, MINIMUS_INTERRUPTUS);
+ /* Atmel code clears this irq twice */
+- at91_udp_write(AT91_UDP_ICR, AT91_UDP_ENDBUSRES);
+- at91_udp_write(AT91_UDP_ICR, AT91_UDP_ENDBUSRES);
++ at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES);
++ at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES);
+ VDBG("end bus reset\n");
+ udc->addr = 0;
+ stop_activity(udc);
+
+ /* enable ep0 */
+- at91_udp_write(AT91_UDP_CSR(0),
++ at91_udp_write(udc, AT91_UDP_CSR(0),
+ AT91_UDP_EPEDS | AT91_UDP_EPTYPE_CTRL);
+ udc->gadget.speed = USB_SPEED_FULL;
+ udc->suspended = 0;
+- at91_udp_write(AT91_UDP_IER, AT91_UDP_EP(0));
++ at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_EP(0));
+
+ /*
+ * NOTE: this driver keeps clocks off unless the
+@@ -1406,9 +1407,9 @@
+
+ /* host initiated suspend (3+ms bus idle) */
+ } else if (status & AT91_UDP_RXSUSP) {
+- at91_udp_write(AT91_UDP_IDR, AT91_UDP_RXSUSP);
+- at91_udp_write(AT91_UDP_IER, AT91_UDP_RXRSM);
+- at91_udp_write(AT91_UDP_ICR, AT91_UDP_RXSUSP);
++ at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXSUSP);
++ at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXRSM);
++ at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXSUSP);
+ // VDBG("bus suspend\n");
+ if (udc->suspended)
+ continue;
+@@ -1425,9 +1426,9 @@
+
+ /* host initiated resume */
+ } else if (status & AT91_UDP_RXRSM) {
+- at91_udp_write(AT91_UDP_IDR, AT91_UDP_RXRSM);
+- at91_udp_write(AT91_UDP_IER, AT91_UDP_RXSUSP);
+- at91_udp_write(AT91_UDP_ICR, AT91_UDP_RXRSM);
++ at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXRSM);
++ at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXSUSP);
++ at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXRSM);
+ // VDBG("bus resume\n");
+ if (!udc->suspended)
+ continue;
+@@ -1479,17 +1480,16 @@
+ }
+ },
+ .ep[0] = {
++ .id = 0,
+ .ep = {
+ .name = ep0name,
+ .ops = &at91_ep_ops,
+ },
+ .udc = &controller,
+ .maxpacket = 8,
+- .creg = (void __iomem *)(AT91_VA_BASE_UDP
+- + AT91_UDP_CSR(0)),
+- .int_mask = 1 << 0,
+ },
+ .ep[1] = {
++ .id = 1,
+ .ep = {
+ .name = "ep1",
+ .ops = &at91_ep_ops,
+@@ -1497,11 +1497,9 @@
+ .udc = &controller,
+ .is_pingpong = 1,
+ .maxpacket = 64,
+- .creg = (void __iomem *)(AT91_VA_BASE_UDP
+- + AT91_UDP_CSR(1)),
+- .int_mask = 1 << 1,
+ },
+ .ep[2] = {
++ .id = 2,
+ .ep = {
+ .name = "ep2",
+ .ops = &at91_ep_ops,
+@@ -1509,11 +1507,9 @@
+ .udc = &controller,
+ .is_pingpong = 1,
+ .maxpacket = 64,
+- .creg = (void __iomem *)(AT91_VA_BASE_UDP
+- + AT91_UDP_CSR(2)),
+- .int_mask = 1 << 2,
+ },
+ .ep[3] = {
++ .id = 3,
+ .ep = {
+ /* could actually do bulk too */
+ .name = "ep3-int",
+@@ -1521,11 +1517,9 @@
+ },
+ .udc = &controller,
+ .maxpacket = 8,
+- .creg = (void __iomem *)(AT91_VA_BASE_UDP
+- + AT91_UDP_CSR(3)),
+- .int_mask = 1 << 3,
+ },
+ .ep[4] = {
++ .id = 4,
+ .ep = {
+ .name = "ep4",
+ .ops = &at91_ep_ops,
+@@ -1533,11 +1527,9 @@
+ .udc = &controller,
+ .is_pingpong = 1,
+ .maxpacket = 256,
+- .creg = (void __iomem *)(AT91_VA_BASE_UDP
+- + AT91_UDP_CSR(4)),
+- .int_mask = 1 << 4,
+ },
+ .ep[5] = {
++ .id = 5,
+ .ep = {
+ .name = "ep5",
+ .ops = &at91_ep_ops,
+@@ -1545,9 +1537,6 @@
+ .udc = &controller,
+ .is_pingpong = 1,
+ .maxpacket = 256,
+- .creg = (void __iomem *)(AT91_VA_BASE_UDP
+- + AT91_UDP_CSR(5)),
+- .int_mask = 1 << 5,
+ },
+ /* ep6 and ep7 are also reserved (custom silicon might use them) */
+ };
+@@ -1616,7 +1605,7 @@
+
+ local_irq_disable();
+ udc->enabled = 0;
+- at91_udp_write(AT91_UDP_IDR, ~0);
++ at91_udp_write(udc, AT91_UDP_IDR, ~0);
+ pullup(udc, 0);
+ local_irq_enable();
+
+@@ -1641,6 +1630,7 @@
+ struct device *dev = &pdev->dev;
+ struct at91_udc *udc;
+ int retval;
++ struct resource *res;
+
+ if (!dev->platform_data) {
+ /* small (so we copy it) but critical! */
+@@ -1658,7 +1648,11 @@
+ return -ENODEV;
+ }
+
+- if (!request_mem_region(AT91RM9200_BASE_UDP, SZ_16K, driver_name)) {
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENXIO;
++
++ if (!request_mem_region(res->start, res->end - res->start + 1, driver_name)) {
+ DBG("someone's using UDC memory\n");
+ return -EBUSY;
+ }
+@@ -1668,15 +1662,23 @@
+ udc->gadget.dev.parent = dev;
+ udc->board = *(struct at91_udc_data *) dev->platform_data;
+ udc->pdev = pdev;
+- udc_reinit(udc);
+ udc->enabled = 0;
+
++ udc->udp_baseaddr = ioremap(res->start, res->end - res->start + 1);
++ if (!udc->udp_baseaddr) {
++ release_mem_region(res->start, res->end - res->start + 1);
++ return -ENOMEM;
++ }
++
++ udc_reinit(udc);
++
+ /* get interface and function clocks */
+ udc->iclk = clk_get(dev, "udc_clk");
+ udc->fclk = clk_get(dev, "udpck");
+ if (IS_ERR(udc->iclk) || IS_ERR(udc->fclk)) {
+ DBG("clocks missing\n");
+- return -ENODEV;
++ retval = -ENODEV;
++ goto fail0;
+ }
+
+ retval = device_register(&udc->gadget.dev);
+@@ -1685,8 +1687,10 @@
+
+ /* don't do anything until we have both gadget driver and VBUS */
+ clk_enable(udc->iclk);
+- at91_udp_write(AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
+- at91_udp_write(AT91_UDP_IDR, 0xffffffff);
++ at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
++ at91_udp_write(udc, AT91_UDP_IDR, 0xffffffff);
++ /* Clear all pending interrupts - UDP may be used by bootloader. */
++ at91_udp_write(udc, AT91_UDP_ICR, 0xffffffff);
+ clk_disable(udc->iclk);
+
+ /* request UDC and maybe VBUS irqs */
+@@ -1698,6 +1702,11 @@
+ goto fail1;
+ }
+ if (udc->board.vbus_pin > 0) {
++ /*
++ * Get the initial state of VBUS - we cannot expect
++ * a pending interrupt.
++ */
++ udc->vbus = at91_get_gpio_value(udc->board.vbus_pin);
+ if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
+ IRQF_DISABLED, driver_name, udc)) {
+ DBG("request vbus irq %d failed\n",
+@@ -1720,7 +1729,7 @@
+ fail1:
+ device_unregister(&udc->gadget.dev);
+ fail0:
+- release_mem_region(AT91RM9200_BASE_UDP, SZ_16K);
++ release_mem_region(res->start, res->end - res->start + 1);
+ DBG("%s probe failed, %d\n", driver_name, retval);
+ return retval;
+ }
+@@ -1728,6 +1737,7 @@
+ static int __devexit at91udc_remove(struct platform_device *pdev)
+ {
+ struct at91_udc *udc = platform_get_drvdata(pdev);
++ struct resource *res;
+
+ DBG("remove\n");
+
+@@ -1742,7 +1752,10 @@
+ free_irq(udc->board.vbus_pin, udc);
+ free_irq(udc->udp_irq, udc);
+ device_unregister(&udc->gadget.dev);
+- release_mem_region(AT91RM9200_BASE_UDP, SZ_16K);
++
++ iounmap(udc->udp_baseaddr);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ release_mem_region(res->start, res->end - res->start + 1);
+
+ clk_put(udc->iclk);
+ clk_put(udc->fclk);
+diff -urN -x CVS linux-2.6.19-final/drivers/usb/gadget/at91_udc.h linux-2.6.19/drivers/usb/gadget/at91_udc.h
+--- linux-2.6.19-final/drivers/usb/gadget/at91_udc.h Mon Dec 4 16:34:04 2006
++++ linux-2.6.19/drivers/usb/gadget/at91_udc.h Thu Nov 16 17:30:01 2006
+@@ -51,10 +51,10 @@
+ #define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */
+ #define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
+ #define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */
+-#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status */
++#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status [AT91RM9200 only] */
+ #define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */
+ #define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrpt Status */
+-#define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status */
++#define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status [AT91RM9200 only] */
+
+ #define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */
+ #define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */
+@@ -84,7 +84,7 @@
+
+ #define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */
+ #define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */
+-
++#define AT91_UDP_TXVC_PUON (1 << 9) /* PullUp On [AT91SAM9260 only] */
+
+ /*-------------------------------------------------------------------------*/
+
+@@ -105,10 +105,10 @@
+ struct usb_ep ep;
+ struct list_head queue;
+ struct at91_udc *udc;
++ u8 id;
+ void __iomem *creg;
+
+ unsigned maxpacket:16;
+- u8 int_mask;
+ unsigned is_pingpong:1;
+
+ unsigned stopped:1;
+@@ -141,6 +141,7 @@
+ struct clk *iclk, *fclk;
+ struct platform_device *pdev;
+ struct proc_dir_entry *pde;
++ void __iomem *udp_baseaddr;
+ int udp_irq;
+ };
+
+diff -urN -x CVS linux-2.6.19-final/drivers/usb/host/ohci-at91.c linux-2.6.19/drivers/usb/host/ohci-at91.c
+--- linux-2.6.19-final/drivers/usb/host/ohci-at91.c Mon Dec 4 16:40:49 2006
++++ linux-2.6.19/drivers/usb/host/ohci-at91.c Mon Oct 16 17:19:45 2006
+@@ -187,7 +187,6 @@
+ {
+ struct at91_usbh_data *board = hcd->self.controller->platform_data;
+ struct ohci_hcd *ohci = hcd_to_ohci (hcd);
+- struct usb_device *root = hcd->self.root_hub;
+ int ret;
+
+ if ((ret = ohci_init(ohci)) < 0)
+diff -urN -x CVS linux-2.6.19-final/drivers/usb/host/ohci-hcd.c linux-2.6.19/drivers/usb/host/ohci-hcd.c
+--- linux-2.6.19-final/drivers/usb/host/ohci-hcd.c Mon Dec 4 16:40:49 2006
++++ linux-2.6.19/drivers/usb/host/ohci-hcd.c Thu Nov 30 09:08:25 2006
+@@ -935,7 +935,7 @@
+ #include "ohci-ppc-soc.c"
+ #endif
+
+-#if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261)
++#ifdef CONFIG_ARCH_AT91
+ #include "ohci-at91.c"
+ #endif
+
+@@ -952,8 +952,7 @@
+ || defined (CONFIG_ARCH_EP93XX) \
+ || defined (CONFIG_SOC_AU1X00) \
+ || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \
+- || defined (CONFIG_ARCH_AT91RM9200) \
+- || defined (CONFIG_ARCH_AT91SAM9261) \
++ || defined (CONFIG_ARCH_AT91) \
+ || defined (CONFIG_ARCH_PNX4008) \
+ )
+ #error "missing bus glue for ohci-hcd"
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_aic.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_aic.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_aic.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_aic.h Tue Oct 24 16:14:13 2006
+@@ -0,0 +1,53 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_aic.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Advanced Interrupt Controller (AIC) - System peripherals registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_AIC_H
++#define AT91_AIC_H
++
++#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
++#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
++#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
++#define AT91_AIC_SRCTYPE_LOW (0 << 5)
++#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
++#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
++#define AT91_AIC_SRCTYPE_RISING (3 << 5)
++
++#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
++#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
++#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
++#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
++#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
++
++#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
++#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
++#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
++#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
++#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
++
++#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
++#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
++#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
++#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
++#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
++#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
++#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
++#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
++#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
++
++#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
++#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
++#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_dbgu.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_dbgu.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_dbgu.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_dbgu.h Tue Oct 24 16:03:07 2006
+@@ -0,0 +1,45 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_dbgu.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Debug Unit (DBGU) - System peripherals registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_DBGU_H
++#define AT91_DBGU_H
++
++#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
++#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
++#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
++#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
++#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
++#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
++#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
++#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
++#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
++#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
++#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
++
++#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
++#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
++#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
++#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
++#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
++#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
++#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
++#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
++#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
++#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
++
++#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
++#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_ecc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_ecc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_ecc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_ecc.h Wed Nov 15 11:56:12 2006
+@@ -0,0 +1,38 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_ecc.h
++ *
++ * Error Corrected Code Controller (ECC) - System peripherals regsters.
++ * Based on AT91SAM9260 datasheet revision B.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#ifndef AT91_ECC_H
++#define AT91_ECC_H
++
++#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
++#define AT91_ECC_RST (1 << 0) /* Reset parity */
++
++#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
++#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
++#define AT91_ECC_PAGESIZE_528 (0)
++#define AT91_ECC_PAGESIZE_1056 (1)
++#define AT91_ECC_PAGESIZE_2112 (2)
++#define AT91_ECC_PAGESIZE_4224 (3)
++
++#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
++#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
++#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
++#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
++
++#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
++#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
++#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
++
++#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
++#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_lcdc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_lcdc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_lcdc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_lcdc.h Sat Nov 25 11:06:19 2006
+@@ -0,0 +1,148 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_lcdc.h
++ *
++ * LCD Controller (LCDC).
++ * Based on AT91SAM9261 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_LCDC_H
++#define AT91_LCDC_H
++
++#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */
++#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */
++#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */
++#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */
++#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */
++#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */
++
++#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */
++#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */
++#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */
++
++#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */
++#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */
++#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */
++#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */
++
++#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */
++#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */
++#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */
++#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */
++
++#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */
++#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */
++#define AT91_LCDC_DISTYPE_STNMONO (0 << 0)
++#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0)
++#define AT91_LCDC_DISTYPE_TFT (2 << 0)
++#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */
++#define AT91_LCDC_SCANMOD_SINGLE (0 << 2)
++#define AT91_LCDC_SCANMOD_DUAL (1 << 2)
++#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */
++#define AT91_LCDC_IFWIDTH_4 (0 << 3)
++#define AT91_LCDC_IFWIDTH_8 (1 << 3)
++#define AT91_LCDC_IFWIDTH_16 (2 << 3)
++#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */
++#define AT91_LCDC_PIXELSIZE_1 (0 << 5)
++#define AT91_LCDC_PIXELSIZE_2 (1 << 5)
++#define AT91_LCDC_PIXELSIZE_4 (2 << 5)
++#define AT91_LCDC_PIXELSIZE_8 (3 << 5)
++#define AT91_LCDC_PIXELSIZE_16 (4 << 5)
++#define AT91_LCDC_PIXELSIZE_24 (5 << 5)
++#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */
++#define AT91_LCDC_INVVD_NORMAL (0 << 8)
++#define AT91_LCDC_INVVD_INVERTED (1 << 8)
++#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */
++#define AT91_LCDC_INVFRAME_NORMAL (0 << 9)
++#define AT91_LCDC_INVFRAME_INVERTED (1 << 9)
++#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */
++#define AT91_LCDC_INVLINE_NORMAL (0 << 10)
++#define AT91_LCDC_INVLINE_INVERTED (1 << 10)
++#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */
++#define AT91_LCDC_INVCLK_NORMAL (0 << 11)
++#define AT91_LCDC_INVCLK_INVERTED (1 << 11)
++#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */
++#define AT91_LCDC_INVDVAL_NORMAL (0 << 12)
++#define AT91_LCDC_INVDVAL_INVERTED (1 << 12)
++#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */
++#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
++#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
++#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */
++#define AT91_LCDC_MEMOR_BIG (0 << 31)
++#define AT91_LCDC_MEMOR_LITTLE (1 << 31)
++
++#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */
++#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */
++#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */
++#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */
++#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */
++
++#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */
++#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */
++#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */
++#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */
++
++#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */
++#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */
++#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */
++
++#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */
++#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */
++
++#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */
++#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */
++#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */
++#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */
++#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */
++#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */
++#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */
++#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */
++#define AT91_LCDC_DP1_2_VAL (0xff)
++#define AT91_LCDC_DP4_7_VAL (0xfffffff)
++#define AT91_LCDC_DP3_5_VAL (0xfffff)
++#define AT91_LCDC_DP2_3_VAL (0xfff)
++#define AT91_LCDC_DP5_7_VAL (0xfffffff)
++#define AT91_LCDC_DP3_4_VAL (0xffff)
++#define AT91_LCDC_DP4_5_VAL (0xfffff)
++#define AT91_LCDC_DP6_7_VAL (0xfffffff)
++
++#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */
++#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */
++#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */
++#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */
++
++#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */
++#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */
++#define AT91_LCDC_PS_DIV1 (0 << 0)
++#define AT91_LCDC_PS_DIV2 (1 << 0)
++#define AT91_LCDC_PS_DIV4 (2 << 0)
++#define AT91_LCDC_PS_DIV8 (3 << 0)
++#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */
++#define AT91_LCDC_POL_NEGATIVE (0 << 2)
++#define AT91_LCDC_POL_POSITIVE (1 << 2)
++#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */
++#define AT91_LCDC_ENA_PWMDISABLE (0 << 3)
++#define AT91_LCDC_ENA_PWMENABLE (1 << 3)
++
++#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */
++#define AT91_LCDC_CVAL (0xff) /* PWM compare value */
++
++#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */
++#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */
++#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */
++#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */
++#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */
++#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */
++#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */
++#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */
++#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */
++#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */
++#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */
++
++#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_mci.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_mci.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_mci.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_mci.h Mon Nov 6 12:20:14 2006
+@@ -0,0 +1,106 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_mci.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * MultiMedia Card Interface (MCI) registers.
++ * Based on AT91RM9200 datasheet revision F.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_MCI_H
++#define AT91_MCI_H
++
++#define AT91_MCI_CR 0x00 /* Control Register */
++#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
++#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
++#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
++#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
++#define AT91_MCI_SWRST (1 << 7) /* Software Reset */
++
++#define AT91_MCI_MR 0x04 /* Mode Register */
++#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
++#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
++#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
++#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
++#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
++
++#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
++#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
++#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
++#define AT91_MCI_DTOMUL_1 (0 << 4)
++#define AT91_MCI_DTOMUL_16 (1 << 4)
++#define AT91_MCI_DTOMUL_128 (2 << 4)
++#define AT91_MCI_DTOMUL_256 (3 << 4)
++#define AT91_MCI_DTOMUL_1K (4 << 4)
++#define AT91_MCI_DTOMUL_4K (5 << 4)
++#define AT91_MCI_DTOMUL_64K (6 << 4)
++#define AT91_MCI_DTOMUL_1M (7 << 4)
++
++#define AT91_MCI_SDCR 0x0c /* SD Card Register */
++#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
++#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
++
++#define AT91_MCI_ARGR 0x10 /* Argument Register */
++
++#define AT91_MCI_CMDR 0x14 /* Command Register */
++#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
++#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
++#define AT91_MCI_RSPTYP_NONE (0 << 6)
++#define AT91_MCI_RSPTYP_48 (1 << 6)
++#define AT91_MCI_RSPTYP_136 (2 << 6)
++#define AT91_MCI_SPCMD (7 << 8) /* Special Command */
++#define AT91_MCI_SPCMD_NONE (0 << 8)
++#define AT91_MCI_SPCMD_INIT (1 << 8)
++#define AT91_MCI_SPCMD_SYNC (2 << 8)
++#define AT91_MCI_SPCMD_ICMD (4 << 8)
++#define AT91_MCI_SPCMD_IRESP (5 << 8)
++#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
++#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
++#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
++#define AT91_MCI_TRCMD_NONE (0 << 16)
++#define AT91_MCI_TRCMD_START (1 << 16)
++#define AT91_MCI_TRCMD_STOP (2 << 16)
++#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
++#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
++#define AT91_MCI_TRTYP_BLOCK (0 << 19)
++#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
++#define AT91_MCI_TRTYP_STREAM (2 << 19)
++
++#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
++#define AT91_MCR_RDR 0x30 /* Receive Data Register */
++#define AT91_MCR_TDR 0x34 /* Transmit Data Register */
++
++#define AT91_MCI_SR 0x40 /* Status Register */
++#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
++#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
++#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
++#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
++#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
++#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
++#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
++#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
++#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
++#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */
++#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
++#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
++#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
++#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
++#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
++#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
++#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
++#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
++#define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */
++#define AT91_MCI_OVRE (1 << 30) /* Overrun */
++#define AT91_MCI_UNRE (1 << 31) /* Underrun */
++
++#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
++#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
++#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pdc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pdc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pdc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pdc.h Tue Oct 24 14:28:55 2006
+@@ -0,0 +1,36 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_pdc.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Peripheral Data Controller (PDC) registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_PDC_H
++#define AT91_PDC_H
++
++#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
++#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
++#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
++#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
++#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
++#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
++#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
++#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
++
++#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
++#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
++#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
++#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
++#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
++
++#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pio.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pio.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pio.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pio.h Tue Oct 24 15:47:04 2006
+@@ -0,0 +1,49 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_pio.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Parallel I/O Controller (PIO) - System peripherals registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_PIO_H
++#define AT91_PIO_H
++
++#define PIO_PER 0x00 /* Enable Register */
++#define PIO_PDR 0x04 /* Disable Register */
++#define PIO_PSR 0x08 /* Status Register */
++#define PIO_OER 0x10 /* Output Enable Register */
++#define PIO_ODR 0x14 /* Output Disable Register */
++#define PIO_OSR 0x18 /* Output Status Register */
++#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
++#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
++#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
++#define PIO_SODR 0x30 /* Set Output Data Register */
++#define PIO_CODR 0x34 /* Clear Output Data Register */
++#define PIO_ODSR 0x38 /* Output Data Status Register */
++#define PIO_PDSR 0x3c /* Pin Data Status Register */
++#define PIO_IER 0x40 /* Interrupt Enable Register */
++#define PIO_IDR 0x44 /* Interrupt Disable Register */
++#define PIO_IMR 0x48 /* Interrupt Mask Register */
++#define PIO_ISR 0x4c /* Interrupt Status Register */
++#define PIO_MDER 0x50 /* Multi-driver Enable Register */
++#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
++#define PIO_MDSR 0x58 /* Multi-driver Status Register */
++#define PIO_PUDR 0x60 /* Pull-up Disable Register */
++#define PIO_PUER 0x64 /* Pull-up Enable Register */
++#define PIO_PUSR 0x68 /* Pull-up Status Register */
++#define PIO_ASR 0x70 /* Peripheral A Select Register */
++#define PIO_BSR 0x74 /* Peripheral B Select Register */
++#define PIO_ABSR 0x78 /* AB Status Register */
++#define PIO_OWER 0xa0 /* Output Write Enable Register */
++#define PIO_OWDR 0xa4 /* Output Write Disable Register */
++#define PIO_OWSR 0xa8 /* Output Write Status Register */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pit.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pit.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pit.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pit.h Thu Nov 9 15:09:54 2006
+@@ -0,0 +1,29 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_pit.h
++ *
++ * Periodic Interval Timer (PIT) - System peripherals regsters.
++ * Based on AT91SAM9261 datasheet revision D.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_PIT_H
++#define AT91_PIT_H
++
++#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
++#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
++#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
++#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
++
++#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
++#define AT91_PIT_PITS (1 << 0) /* Timer Status */
++
++#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
++#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
++#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
++#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pmc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pmc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_pmc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_pmc.h Thu Nov 9 09:03:41 2006
+@@ -0,0 +1,92 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_pmc.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Power Management Controller (PMC) - System peripherals registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_PMC_H
++#define AT91_PMC_H
++
++#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
++#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
++
++#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
++#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
++#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
++#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
++#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
++#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
++#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
++#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
++#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
++#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
++#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
++#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
++#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
++
++#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
++#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
++#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
++
++#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
++#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
++#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
++#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
++
++#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
++#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
++#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
++
++#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
++#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
++#define AT91_PMC_DIV (0xff << 0) /* Divider */
++#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
++#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
++#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
++#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
++
++#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
++#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
++#define AT91_PMC_CSS_SLOW (0 << 0)
++#define AT91_PMC_CSS_MAIN (1 << 0)
++#define AT91_PMC_CSS_PLLA (2 << 0)
++#define AT91_PMC_CSS_PLLB (3 << 0)
++#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
++#define AT91_PMC_PRES_1 (0 << 2)
++#define AT91_PMC_PRES_2 (1 << 2)
++#define AT91_PMC_PRES_4 (2 << 2)
++#define AT91_PMC_PRES_8 (3 << 2)
++#define AT91_PMC_PRES_16 (4 << 2)
++#define AT91_PMC_PRES_32 (5 << 2)
++#define AT91_PMC_PRES_64 (6 << 2)
++#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
++#define AT91_PMC_MDIV_1 (0 << 8)
++#define AT91_PMC_MDIV_2 (1 << 8)
++#define AT91_PMC_MDIV_3 (2 << 8)
++#define AT91_PMC_MDIV_4 (3 << 8)
++
++#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
++
++#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
++#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
++#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
++#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
++#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
++#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
++#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
++#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
++#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
++#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
++#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
++#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rstc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rstc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rstc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rstc.h Thu Nov 2 15:59:35 2006
+@@ -0,0 +1,39 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_rstc.h
++ *
++ * Reset Controller (RSTC) - System peripherals regsters.
++ * Based on AT91SAM9261 datasheet revision D.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_RSTC_H
++#define AT91_RSTC_H
++
++#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
++#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
++#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
++#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
++#define AT01_RSTC_KEY (0xff << 24) /* KEY Password */
++
++#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
++#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
++#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
++#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
++#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
++#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
++#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
++#define AT91_RSTC_RSTTYP_USER (4 << 8)
++#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
++#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
++
++#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
++#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
++#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
++#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
++#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rtc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rtc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rtc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rtc.h Tue Oct 24 15:41:59 2006
+@@ -0,0 +1,75 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_rtc.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Real Time Clock (RTC) - System peripheral registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_RTC_H
++#define AT91_RTC_H
++
++#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
++#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
++#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
++#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
++#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
++#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
++#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
++#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
++#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
++#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
++#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
++#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
++
++#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
++#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
++
++#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
++#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
++#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
++#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
++#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
++
++#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
++#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
++#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
++#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
++#define AT91_RTC_DAY (7 << 21) /* Current Day */
++#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
++
++#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
++#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
++#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
++#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
++
++#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
++#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
++#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
++
++#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
++#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
++#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
++#define AT91_RTC_SECEV (1 << 2) /* Second Event */
++#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
++#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
++
++#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
++#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
++#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
++#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
++
++#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
++#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
++#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
++#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
++#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rtt.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rtt.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_rtt.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_rtt.h Thu Nov 9 15:09:30 2006
+@@ -0,0 +1,32 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_rtt.h
++ *
++ * Real-time Timer (RTT) - System peripherals regsters.
++ * Based on AT91SAM9261 datasheet revision D.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_RTT_H
++#define AT91_RTT_H
++
++#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */
++#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
++#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
++#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
++#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
++
++#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */
++#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
++
++#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */
++#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
++
++#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */
++#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
++#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_shdwc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_shdwc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_shdwc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_shdwc.h Thu Nov 9 15:08:30 2006
+@@ -0,0 +1,33 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_shdwc.h
++ *
++ * Shutdown Controller (SHDWC) - System peripherals regsters.
++ * Based on AT91SAM9261 datasheet revision D.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_SHDWC_H
++#define AT91_SHDWC_H
++
++#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
++#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */
++#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */
++
++#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
++#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
++#define AT91_SHDW_WKMODE0_NONE 0
++#define AT91_SHDW_WKMODE0_HIGH 1
++#define AT91_SHDW_WKMODE0_LOW 2
++#define AT91_SHDW_WKMODE0_ANYLEVEL 3
++#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
++#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
++
++#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
++#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
++#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_spi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_spi.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_spi.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_spi.h Wed Nov 15 16:58:25 2006
+@@ -0,0 +1,81 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_spi.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Serial Peripheral Interface (SPI) registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_SPI_H
++#define AT91_SPI_H
++
++#define AT91_SPI_CR 0x00 /* Control Register */
++#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
++#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
++#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
++#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
++
++#define AT91_SPI_MR 0x04 /* Mode Register */
++#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
++#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
++#define AT91_SPI_PS_FIXED (0 << 1)
++#define AT91_SPI_PS_VARIABLE (1 << 1)
++#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
++#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
++#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
++#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
++#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
++#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
++
++#define AT91_SPI_RDR 0x08 /* Receive Data Register */
++#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
++#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
++
++#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
++#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
++#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
++#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
++
++#define AT91_SPI_SR 0x10 /* Status Register */
++#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
++#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
++#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
++#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
++#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
++#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
++#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
++#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
++#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
++#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
++#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
++
++#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
++#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
++#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
++
++#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
++#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
++#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
++#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
++#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
++#define AT91_SPI_BITS_8 (0 << 4)
++#define AT91_SPI_BITS_9 (1 << 4)
++#define AT91_SPI_BITS_10 (2 << 4)
++#define AT91_SPI_BITS_11 (3 << 4)
++#define AT91_SPI_BITS_12 (4 << 4)
++#define AT91_SPI_BITS_13 (5 << 4)
++#define AT91_SPI_BITS_14 (6 << 4)
++#define AT91_SPI_BITS_15 (7 << 4)
++#define AT91_SPI_BITS_16 (8 << 4)
++#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
++#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
++#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_ssc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_ssc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_ssc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_ssc.h Mon Nov 6 12:40:23 2006
+@@ -0,0 +1,106 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_ssc.h
++ *
++ * Copyright (C) SAN People
++ *
++ * Serial Synchronous Controller (SSC) registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_SSC_H
++#define AT91_SSC_H
++
++#define AT91_SSC_CR 0x00 /* Control Register */
++#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
++#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */
++#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */
++#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */
++#define AT91_SSC_SWRST (1 << 15) /* Software Reset */
++
++#define AT91_SSC_CMR 0x04 /* Clock Mode Register */
++#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */
++
++#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */
++#define AT91_SSC_CKS (3 << 0) /* Clock Selection */
++#define AT91_SSC_CKS_DIV (0 << 0)
++#define AT91_SSC_CKS_CLOCK (1 << 0)
++#define AT91_SSC_CKS_PIN (2 << 0)
++#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */
++#define AT91_SSC_CKO_NONE (0 << 2)
++#define AT91_SSC_CKO_CONTINUOUS (1 << 2)
++#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
++#define AT91_SSC_CKI_FALLING (0 << 5)
++#define AT91_SSC_CK_RISING (1 << 5)
++#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
++#define AT91_SSC_CKG_NONE (0 << 6)
++#define AT91_SSC_CKG_RFLOW (1 << 6)
++#define AT91_SSC_CKG_RFHIGH (2 << 6)
++#define AT91_SSC_START (0xf << 8) /* Start Selection */
++#define AT91_SSC_START_CONTINUOUS (0 << 8)
++#define AT91_SSC_START_TX_RX (1 << 8)
++#define AT91_SSC_START_LOW_RF (2 << 8)
++#define AT91_SSC_START_HIGH_RF (3 << 8)
++#define AT91_SSC_START_FALLING_RF (4 << 8)
++#define AT91_SSC_START_RISING_RF (5 << 8)
++#define AT91_SSC_START_LEVEL_RF (6 << 8)
++#define AT91_SSC_START_EDGE_RF (7 << 8)
++#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
++#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
++#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
++
++#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */
++#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */
++#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */
++#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */
++#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */
++#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */
++#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */
++#define AT91_SSC_FSOS_NONE (0 << 20)
++#define AT91_SSC_FSOS_NEGATIVE (1 << 20)
++#define AT91_SSC_FSOS_POSITIVE (2 << 20)
++#define AT91_SSC_FSOS_LOW (3 << 20)
++#define AT91_SSC_FSOS_HIGH (4 << 20)
++#define AT91_SSC_FSOS_TOGGLE (5 << 20)
++#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
++#define AT91_SSC_FSEDGE_POSITIVE (0 << 24)
++#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24)
++
++#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */
++#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */
++#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */
++#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */
++
++#define AT91_SSC_RHR 0x20 /* Receive Holding Register */
++#define AT91_SSC_THR 0x24 /* Transmit Holding Register */
++#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
++#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
++
++#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
++#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
++
++#define AT91_SSC_SR 0x40 /* Status Register */
++#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
++#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
++#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */
++#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */
++#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */
++#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
++#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
++#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
++#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
++#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
++#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
++#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
++#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
++#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */
++
++#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */
++#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */
++#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_st.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_st.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_st.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_st.h Tue Oct 24 17:15:02 2006
+@@ -0,0 +1,49 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_st.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * System Timer (ST) - System peripherals registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_ST_H
++#define AT91_ST_H
++
++#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
++#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
++
++#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
++#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
++
++#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
++#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
++#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
++#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
++
++#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
++#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
++
++#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
++#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
++#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
++#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
++#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
++
++#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
++#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
++#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
++
++#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
++#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
++
++#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
++#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_tc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_tc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_tc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_tc.h Tue Oct 24 15:21:53 2006
+@@ -0,0 +1,146 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_tc.h
++ *
++ * Copyright (C) SAN People
++ *
++ * Timer/Counter Unit (TC) registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_TC_H
++#define AT91_TC_H
++
++#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
++#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
++
++#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
++#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
++#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
++#define AT91_TC_TC0XC0S_NONE (1 << 0)
++#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
++#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
++#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
++#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
++#define AT91_TC_TC1XC1S_NONE (1 << 2)
++#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
++#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
++#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
++#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
++#define AT91_TC_TC2XC2S_NONE (1 << 4)
++#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
++#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
++
++
++#define AT91_TC_CCR 0x00 /* Channel Control Register */
++#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
++#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
++#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
++
++#define AT91_TC_CMR 0x04 /* Channel Mode Register */
++#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
++#define AT91_TC_TIMER_CLOCK1 (0 << 0)
++#define AT91_TC_TIMER_CLOCK2 (1 << 0)
++#define AT91_TC_TIMER_CLOCK3 (2 << 0)
++#define AT91_TC_TIMER_CLOCK4 (3 << 0)
++#define AT91_TC_TIMER_CLOCK5 (4 << 0)
++#define AT91_TC_XC0 (5 << 0)
++#define AT91_TC_XC1 (6 << 0)
++#define AT91_TC_XC2 (7 << 0)
++#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
++#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
++#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
++#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
++#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
++#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
++#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
++#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
++#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
++#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
++
++#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
++#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
++#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
++#define AT91_TC_EEVTEDG_NONE (0 << 8)
++#define AT91_TC_EEVTEDG_RISING (1 << 8)
++#define AT91_TC_EEVTEDG_FALLING (2 << 8)
++#define AT91_TC_EEVTEDG_BOTH (3 << 8)
++#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
++#define AT91_TC_EEVT_TIOB (0 << 10)
++#define AT91_TC_EEVT_XC0 (1 << 10)
++#define AT91_TC_EEVT_XC1 (2 << 10)
++#define AT91_TC_EEVT_XC2 (3 << 10)
++#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
++#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
++#define AT91_TC_WAVESEL_UP (0 << 13)
++#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
++#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
++#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
++#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
++#define AT91_TC_ACPA_NONE (0 << 16)
++#define AT91_TC_ACPA_SET (1 << 16)
++#define AT91_TC_ACPA_CLEAR (2 << 16)
++#define AT91_TC_ACPA_TOGGLE (3 << 16)
++#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
++#define AT91_TC_ACPC_NONE (0 << 18)
++#define AT91_TC_ACPC_SET (1 << 18)
++#define AT91_TC_ACPC_CLEAR (2 << 18)
++#define AT91_TC_ACPC_TOGGLE (3 << 18)
++#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
++#define AT91_TC_AEEVT_NONE (0 << 20)
++#define AT91_TC_AEEVT_SET (1 << 20)
++#define AT91_TC_AEEVT_CLEAR (2 << 20)
++#define AT91_TC_AEEVT_TOGGLE (3 << 20)
++#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
++#define AT91_TC_ASWTRG_NONE (0 << 22)
++#define AT91_TC_ASWTRG_SET (1 << 22)
++#define AT91_TC_ASWTRG_CLEAR (2 << 22)
++#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
++#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
++#define AT91_TC_BCPB_NONE (0 << 24)
++#define AT91_TC_BCPB_SET (1 << 24)
++#define AT91_TC_BCPB_CLEAR (2 << 24)
++#define AT91_TC_BCPB_TOGGLE (3 << 24)
++#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
++#define AT91_TC_BCPC_NONE (0 << 26)
++#define AT91_TC_BCPC_SET (1 << 26)
++#define AT91_TC_BCPC_CLEAR (2 << 26)
++#define AT91_TC_BCPC_TOGGLE (3 << 26)
++#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
++#define AT91_TC_BEEVT_NONE (0 << 28)
++#define AT91_TC_BEEVT_SET (1 << 28)
++#define AT91_TC_BEEVT_CLEAR (2 << 28)
++#define AT91_TC_BEEVT_TOGGLE (3 << 28)
++#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
++#define AT91_TC_BSWTRG_NONE (0 << 30)
++#define AT91_TC_BSWTRG_SET (1 << 30)
++#define AT91_TC_BSWTRG_CLEAR (2 << 30)
++#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
++
++#define AT91_TC_CV 0x10 /* Counter Value */
++#define AT91_TC_RA 0x14 /* Register A */
++#define AT91_TC_RB 0x18 /* Register B */
++#define AT91_TC_RC 0x1c /* Register C */
++
++#define AT91_TC_SR 0x20 /* Status Register */
++#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
++#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
++#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
++#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
++#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
++#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
++#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
++#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
++#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
++#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
++#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
++
++#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
++#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
++#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_twi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_twi.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_twi.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_twi.h Thu Nov 2 16:46:07 2006
+@@ -0,0 +1,57 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_twi.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Two-wire Interface (TWI) registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_TWI_H
++#define AT91_TWI_H
++
++#define AT91_TWI_CR 0x00 /* Control Register */
++#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
++#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
++#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
++#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
++#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
++
++#define AT91_TWI_MMR 0x04 /* Master Mode Register */
++#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
++#define AT91_TWI_IADRSZ_NO (0 << 8)
++#define AT91_TWI_IADRSZ_1 (1 << 8)
++#define AT91_TWI_IADRSZ_2 (2 << 8)
++#define AT91_TWI_IADRSZ_3 (3 << 8)
++#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
++#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
++
++#define AT91_TWI_IADR 0x0c /* Internal Address Register */
++
++#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
++#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
++#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
++#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
++
++#define AT91_TWI_SR 0x20 /* Status Register */
++#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
++#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
++#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
++#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
++#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
++#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
++
++#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
++#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
++#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
++#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
++#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
++
++#endif
++
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_wdt.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_wdt.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91_wdt.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91_wdt.h Thu Nov 9 15:10:16 2006
+@@ -0,0 +1,34 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_wdt.h
++ *
++ * Watchdog Timer (WDT) - System peripherals regsters.
++ * Based on AT91SAM9261 datasheet revision D.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_WDT_H
++#define AT91_WDT_H
++
++#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
++#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
++#define AT91_WDT_KEY (0xff << 24) /* KEY Password */
++
++#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
++#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
++#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
++#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
++#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
++#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
++#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
++#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
++#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
++
++#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
++#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
++#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200.h Mon Dec 4 16:41:04 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200.h Fri Nov 10 09:25:26 2006
+@@ -80,6 +80,22 @@
+
+
+ /*
++ * System Peripherals (offset from AT91_BASE_SYS)
++ */
++#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
++#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
++#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
++#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
++#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
++#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
++#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
++#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
++#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
++#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
++
++#define AT91_MATRIX 0 /* not supported */
++
++/*
+ * Internal Memory.
+ */
+ #define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h Thu Nov 2 16:54:12 2006
+@@ -0,0 +1,160 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91RM9200_MC_H
++#define AT91RM9200_MC_H
++
++/* Memory Controller */
++#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
++#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
++
++#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
++#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
++#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
++#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
++#define AT91_MC_ABTSZ_BYTE (0 << 8)
++#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
++#define AT91_MC_ABTSZ_WORD (2 << 8)
++#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
++#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
++#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
++#define AT91_MC_ABTTYP_FETCH (2 << 10)
++#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
++#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
++#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
++#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
++#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
++#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
++#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
++#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
++
++#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
++
++#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
++#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
++#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
++#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
++#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
++
++/* External Bus Interface (EBI) registers */
++#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
++#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
++#define AT91_EBI_CS0A_SMC (0 << 0)
++#define AT91_EBI_CS0A_BFC (1 << 0)
++#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
++#define AT91_EBI_CS1A_SMC (0 << 1)
++#define AT91_EBI_CS1A_SDRAMC (1 << 1)
++#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
++#define AT91_EBI_CS3A_SMC (0 << 3)
++#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
++#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
++#define AT91_EBI_CS4A_SMC (0 << 4)
++#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
++#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
++#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
++
++/* Static Memory Controller (SMC) registers */
++#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
++#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
++#define AT91_SMC_NWS_(x) ((x) << 0)
++#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
++#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
++#define AT91_SMC_TDF_(x) ((x) << 8)
++#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
++#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
++#define AT91_SMC_DBW_16 (1 << 13)
++#define AT91_SMC_DBW_8 (2 << 13)
++#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
++#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
++#define AT91_SMC_ACSS_STD (0 << 16)
++#define AT91_SMC_ACSS_1 (1 << 16)
++#define AT91_SMC_ACSS_2 (2 << 16)
++#define AT91_SMC_ACSS_3 (3 << 16)
++#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
++#define AT91_SMC_RWSETUP_(x) ((x) << 24)
++#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
++#define AT91_SMC_RWHOLD_(x) ((x) << 28)
++
++/* SDRAM Controller registers */
++#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
++#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
++#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
++#define AT91_SDRAMC_MODE_NOP (1 << 0)
++#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
++#define AT91_SDRAMC_MODE_LMR (3 << 0)
++#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
++#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
++#define AT91_SDRAMC_DBW_32 (0 << 4)
++#define AT91_SDRAMC_DBW_16 (1 << 4)
++
++#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
++#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
++
++#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
++#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
++#define AT91_SDRAMC_NC_8 (0 << 0)
++#define AT91_SDRAMC_NC_9 (1 << 0)
++#define AT91_SDRAMC_NC_10 (2 << 0)
++#define AT91_SDRAMC_NC_11 (3 << 0)
++#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
++#define AT91_SDRAMC_NR_11 (0 << 2)
++#define AT91_SDRAMC_NR_12 (1 << 2)
++#define AT91_SDRAMC_NR_13 (2 << 2)
++#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
++#define AT91_SDRAMC_NB_2 (0 << 4)
++#define AT91_SDRAMC_NB_4 (1 << 4)
++#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
++#define AT91_SDRAMC_CAS_2 (2 << 5)
++#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
++#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
++#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
++#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
++#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
++#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
++
++#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
++#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
++#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
++#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
++#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
++#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
++
++/* Burst Flash Controller register */
++#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
++#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
++#define AT91_BFC_BFCOM_DISABLED (0 << 0)
++#define AT91_BFC_BFCOM_ASYNC (1 << 0)
++#define AT91_BFC_BFCOM_BURST (2 << 0)
++#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
++#define AT91_BFC_BFCC_MCK (1 << 2)
++#define AT91_BFC_BFCC_DIV2 (2 << 2)
++#define AT91_BFC_BFCC_DIV4 (3 << 2)
++#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
++#define AT91_BFC_PAGES (7 << 8) /* Page Size */
++#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
++#define AT91_BFC_PAGES_16 (1 << 8)
++#define AT91_BFC_PAGES_32 (2 << 8)
++#define AT91_BFC_PAGES_64 (3 << 8)
++#define AT91_BFC_PAGES_128 (4 << 8)
++#define AT91_BFC_PAGES_256 (5 << 8)
++#define AT91_BFC_PAGES_512 (6 << 8)
++#define AT91_BFC_PAGES_1024 (7 << 8)
++#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
++#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
++#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
++#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
++#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h Mon Dec 4 16:29:13 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h Thu Jan 1 02:00:00 1970
+@@ -1,104 +0,0 @@
+-/*
+- * include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
+- *
+- * Copyright (C) 2005 Ivan Kokshaysky
+- * Copyright (C) SAN People
+- *
+- * MultiMedia Card Interface (MCI) registers.
+- * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef AT91RM9200_MCI_H
+-#define AT91RM9200_MCI_H
+-
+-#define AT91_MCI_CR 0x00 /* Control Register */
+-#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
+-#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
+-#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
+-#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
+-#define AT91_MCI_SWRST (1 << 7) /* Software Reset */
+-
+-#define AT91_MCI_MR 0x04 /* Mode Register */
+-#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
+-#define AT91_MCI_PWSDIV (3 << 8) /* Power Saving Divider */
+-#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
+-#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
+-#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
+-
+-#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
+-#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
+-#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
+-#define AT91_MCI_DTOMUL_1 (0 << 4)
+-#define AT91_MCI_DTOMUL_16 (1 << 4)
+-#define AT91_MCI_DTOMUL_128 (2 << 4)
+-#define AT91_MCI_DTOMUL_256 (3 << 4)
+-#define AT91_MCI_DTOMUL_1K (4 << 4)
+-#define AT91_MCI_DTOMUL_4K (5 << 4)
+-#define AT91_MCI_DTOMUL_64K (6 << 4)
+-#define AT91_MCI_DTOMUL_1M (7 << 4)
+-
+-#define AT91_MCI_SDCR 0x0c /* SD Card Register */
+-#define AT91_MCI_SDCSEL (0xf << 0) /* SD Card Selector */
+-#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
+-
+-#define AT91_MCI_ARGR 0x10 /* Argument Register */
+-
+-#define AT91_MCI_CMDR 0x14 /* Command Register */
+-#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
+-#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
+-#define AT91_MCI_RSPTYP_NONE (0 << 6)
+-#define AT91_MCI_RSPTYP_48 (1 << 6)
+-#define AT91_MCI_RSPTYP_136 (2 << 6)
+-#define AT91_MCI_SPCMD (7 << 8) /* Special Command */
+-#define AT91_MCI_SPCMD_NONE (0 << 8)
+-#define AT91_MCI_SPCMD_INIT (1 << 8)
+-#define AT91_MCI_SPCMD_SYNC (2 << 8)
+-#define AT91_MCI_SPCMD_ICMD (4 << 8)
+-#define AT91_MCI_SPCMD_IRESP (5 << 8)
+-#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
+-#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
+-#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
+-#define AT91_MCI_TRCMD_NONE (0 << 16)
+-#define AT91_MCI_TRCMD_START (1 << 16)
+-#define AT91_MCI_TRCMD_STOP (2 << 16)
+-#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
+-#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
+-#define AT91_MCI_TRTYP_BLOCK (0 << 19)
+-#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
+-#define AT91_MCI_TRTYP_STREAM (2 << 19)
+-
+-#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
+-#define AT91_MCR_RDR 0x30 /* Receive Data Register */
+-#define AT91_MCR_TDR 0x34 /* Transmit Data Register */
+-
+-#define AT91_MCI_SR 0x40 /* Status Register */
+-#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
+-#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
+-#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
+-#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
+-#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
+-#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
+-#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
+-#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
+-#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
+-#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
+-#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
+-#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
+-#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
+-#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
+-#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
+-#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
+-#define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */
+-#define AT91_MCI_OVRE (1 << 30) /* Overrun */
+-#define AT91_MCI_UNRE (1 << 31) /* Underrun */
+-
+-#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
+-#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
+-#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
+-
+-#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h Tue May 30 11:42:13 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h Thu Jan 1 02:00:00 1970
+@@ -1,36 +0,0 @@
+-/*
+- * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+- *
+- * Copyright (C) 2005 Ivan Kokshaysky
+- * Copyright (C) SAN People
+- *
+- * Peripheral Data Controller (PDC) registers.
+- * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef AT91RM9200_PDC_H
+-#define AT91RM9200_PDC_H
+-
+-#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
+-#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
+-#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
+-#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
+-#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
+-#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
+-#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
+-#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
+-
+-#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
+-#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
+-#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
+-#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
+-#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
+-
+-#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
+-
+-#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h Mon Dec 4 16:34:19 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h Thu Jan 1 02:00:00 1970
+@@ -1,81 +0,0 @@
+-/*
+- * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+- *
+- * Copyright (C) 2005 Ivan Kokshaysky
+- * Copyright (C) SAN People
+- *
+- * Serial Peripheral Interface (SPI) registers.
+- * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef AT91RM9200_SPI_H
+-#define AT91RM9200_SPI_H
+-
+-#define AT91_SPI_CR 0x00 /* Control Register */
+-#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
+-#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
+-#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
+-#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
+-
+-#define AT91_SPI_MR 0x04 /* Mode Register */
+-#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
+-#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
+-#define AT91_SPI_PS_FIXED (0 << 1)
+-#define AT91_SPI_PS_VARIABLE (1 << 1)
+-#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
+-#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */
+-#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
+-#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
+-#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
+-#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
+-
+-#define AT91_SPI_RDR 0x08 /* Receive Data Register */
+-#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
+-#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
+-
+-#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
+-#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
+-#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
+-#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
+-
+-#define AT91_SPI_SR 0x10 /* Status Register */
+-#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
+-#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
+-#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
+-#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
+-#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
+-#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
+-#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
+-#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
+-#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
+-#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
+-#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
+-
+-#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
+-#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
+-#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
+-
+-#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
+-#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
+-#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
+-#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
+-#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
+-#define AT91_SPI_BITS_8 (0 << 4)
+-#define AT91_SPI_BITS_9 (1 << 4)
+-#define AT91_SPI_BITS_10 (2 << 4)
+-#define AT91_SPI_BITS_11 (3 << 4)
+-#define AT91_SPI_BITS_12 (4 << 4)
+-#define AT91_SPI_BITS_13 (5 << 4)
+-#define AT91_SPI_BITS_14 (6 << 4)
+-#define AT91_SPI_BITS_15 (7 << 4)
+-#define AT91_SPI_BITS_16 (8 << 4)
+-#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
+-#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
+-#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
+-
+-#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h Mon Dec 4 16:34:19 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h Thu Jan 1 02:00:00 1970
+@@ -1,96 +0,0 @@
+-/*
+- * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+- *
+- * Copyright (C) SAN People
+- *
+- * Serial Synchronous Controller (SSC) registers.
+- * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef AT91RM9200_SSC_H
+-#define AT91RM9200_SSC_H
+-
+-#define AT91_SSC_CR 0x00 /* Control Register */
+-#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
+-#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */
+-#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */
+-#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */
+-#define AT91_SSC_SWRST (1 << 15) /* Software Reset */
+-
+-#define AT91_SSC_CMR 0x04 /* Clock Mode Register */
+-#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */
+-
+-#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */
+-#define AT91_SSC_CKS (3 << 0) /* Clock Selection */
+-#define AT91_SSC_CKS_DIV (0 << 0)
+-#define AT91_SSC_CKS_CLOCK (1 << 0)
+-#define AT91_SSC_CKS_PIN (2 << 0)
+-#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */
+-#define AT91_SSC_CKO_NONE (0 << 2)
+-#define AT91_SSC_CKO_CONTINUOUS (1 << 2)
+-#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
+-#define AT91_SSC_CKI_FALLING (0 << 5)
+-#define AT91_SSC_CK_RISING (1 << 5)
+-#define AT91_SSC_START (0xf << 8) /* Start Selection */
+-#define AT91_SSC_START_CONTINUOUS (0 << 8)
+-#define AT91_SSC_START_TX_RX (1 << 8)
+-#define AT91_SSC_START_LOW_RF (2 << 8)
+-#define AT91_SSC_START_HIGH_RF (3 << 8)
+-#define AT91_SSC_START_FALLING_RF (4 << 8)
+-#define AT91_SSC_START_RISING_RF (5 << 8)
+-#define AT91_SSC_START_LEVEL_RF (6 << 8)
+-#define AT91_SSC_START_EDGE_RF (7 << 8)
+-#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
+-#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
+-
+-#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */
+-#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */
+-#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */
+-#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */
+-#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */
+-#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */
+-#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */
+-#define AT91_SSC_FSOS_NONE (0 << 20)
+-#define AT91_SSC_FSOS_NEGATIVE (1 << 20)
+-#define AT91_SSC_FSOS_POSITIVE (2 << 20)
+-#define AT91_SSC_FSOS_LOW (3 << 20)
+-#define AT91_SSC_FSOS_HIGH (4 << 20)
+-#define AT91_SSC_FSOS_TOGGLE (5 << 20)
+-#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
+-#define AT91_SSC_FSEDGE_POSITIVE (0 << 24)
+-#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24)
+-
+-#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */
+-#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */
+-#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */
+-#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */
+-
+-#define AT91_SSC_RHR 0x20 /* Receive Holding Register */
+-#define AT91_SSC_THR 0x24 /* Transmit Holding Register */
+-#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
+-#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
+-
+-#define AT91_SSC_SR 0x40 /* Status Register */
+-#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
+-#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
+-#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */
+-#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */
+-#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */
+-#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
+-#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
+-#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
+-#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
+-#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
+-#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
+-#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */
+-
+-#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */
+-#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */
+-#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */
+-
+-#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h Mon Dec 4 16:41:04 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h Thu Jan 1 02:00:00 1970
+@@ -1,438 +0,0 @@
+-/*
+- * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+- *
+- * Copyright (C) 2005 Ivan Kokshaysky
+- * Copyright (C) SAN People
+- *
+- * System peripherals registers.
+- * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef AT91RM9200_SYS_H
+-#define AT91RM9200_SYS_H
+-
+-/*
+- * Advanced Interrupt Controller.
+- */
+-#define AT91_AIC 0x000
+-
+-#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
+-#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
+-#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
+-#define AT91_AIC_SRCTYPE_LOW (0 << 5)
+-#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
+-#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
+-#define AT91_AIC_SRCTYPE_RISING (3 << 5)
+-
+-#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
+-#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
+-#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
+-#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
+-#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
+-
+-#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
+-#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
+-#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
+-#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
+-#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
+-
+-#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
+-#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
+-#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
+-#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
+-#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
+-#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
+-#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
+-#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
+-#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
+-
+-
+-/*
+- * Debug Unit.
+- */
+-#define AT91_DBGU 0x200
+-
+-#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
+-#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
+-#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
+-#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
+-#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
+-#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
+-#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
+-#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
+-#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
+-#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
+-#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
+-
+-#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
+-#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
+-#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
+-#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
+-#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
+-#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
+-#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
+-#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
+-#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
+-#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
+-
+-#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
+-#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
+-#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
+-
+-/*
+- * PIO Controllers.
+- */
+-#define AT91_PIOA 0x400
+-#define AT91_PIOB 0x600
+-#define AT91_PIOC 0x800
+-#define AT91_PIOD 0xa00
+-
+-#define PIO_PER 0x00 /* Enable Register */
+-#define PIO_PDR 0x04 /* Disable Register */
+-#define PIO_PSR 0x08 /* Status Register */
+-#define PIO_OER 0x10 /* Output Enable Register */
+-#define PIO_ODR 0x14 /* Output Disable Register */
+-#define PIO_OSR 0x18 /* Output Status Register */
+-#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
+-#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
+-#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
+-#define PIO_SODR 0x30 /* Set Output Data Register */
+-#define PIO_CODR 0x34 /* Clear Output Data Register */
+-#define PIO_ODSR 0x38 /* Output Data Status Register */
+-#define PIO_PDSR 0x3c /* Pin Data Status Register */
+-#define PIO_IER 0x40 /* Interrupt Enable Register */
+-#define PIO_IDR 0x44 /* Interrupt Disable Register */
+-#define PIO_IMR 0x48 /* Interrupt Mask Register */
+-#define PIO_ISR 0x4c /* Interrupt Status Register */
+-#define PIO_MDER 0x50 /* Multi-driver Enable Register */
+-#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
+-#define PIO_MDSR 0x58 /* Multi-driver Status Register */
+-#define PIO_PUDR 0x60 /* Pull-up Disable Register */
+-#define PIO_PUER 0x64 /* Pull-up Enable Register */
+-#define PIO_PUSR 0x68 /* Pull-up Status Register */
+-#define PIO_ASR 0x70 /* Peripheral A Select Register */
+-#define PIO_BSR 0x74 /* Peripheral B Select Register */
+-#define PIO_ABSR 0x78 /* AB Status Register */
+-#define PIO_OWER 0xa0 /* Output Write Enable Register */
+-#define PIO_OWDR 0xa4 /* Output Write Disable Register */
+-#define PIO_OWSR 0xa8 /* Output Write Status Register */
+-
+-#define AT91_PIO_P(n) (1 << (n))
+-
+-
+-/*
+- * Power Management Controller.
+- */
+-#define AT91_PMC 0xc00
+-
+-#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
+-#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
+-
+-#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
+-#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
+-#define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */
+-#define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */
+-#define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */
+-#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
+-#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
+-#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
+-#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
+-
+-#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
+-#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
+-#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
+-
+-#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
+-#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
+-#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
+-
+-#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
+-#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
+-#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
+-
+-#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
+-#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
+-#define AT91_PMC_DIV (0xff << 0) /* Divider */
+-#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
+-#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
+-#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
+-#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
+-
+-#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
+-#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
+-#define AT91_PMC_CSS_SLOW (0 << 0)
+-#define AT91_PMC_CSS_MAIN (1 << 0)
+-#define AT91_PMC_CSS_PLLA (2 << 0)
+-#define AT91_PMC_CSS_PLLB (3 << 0)
+-#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
+-#define AT91_PMC_PRES_1 (0 << 2)
+-#define AT91_PMC_PRES_2 (1 << 2)
+-#define AT91_PMC_PRES_4 (2 << 2)
+-#define AT91_PMC_PRES_8 (3 << 2)
+-#define AT91_PMC_PRES_16 (4 << 2)
+-#define AT91_PMC_PRES_32 (5 << 2)
+-#define AT91_PMC_PRES_64 (6 << 2)
+-#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
+-#define AT91_PMC_MDIV_1 (0 << 8)
+-#define AT91_PMC_MDIV_2 (1 << 8)
+-#define AT91_PMC_MDIV_3 (2 << 8)
+-#define AT91_PMC_MDIV_4 (3 << 8)
+-
+-#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
+-
+-#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
+-#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
+-#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
+-#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
+-#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
+-#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
+-#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
+-#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
+-#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
+-#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
+-#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
+-#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
+-
+-
+-/*
+- * System Timer.
+- */
+-#define AT91_ST 0xd00
+-
+-#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
+-#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
+-#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
+-#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
+-#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
+-#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
+-#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
+-#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
+-#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
+-#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
+-#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
+-#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
+-#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
+-#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
+-#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
+-#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
+-#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
+-#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
+-#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
+-#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
+-#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
+-#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
+-
+-
+-/*
+- * Real-time Clock.
+- */
+-#define AT91_RTC 0xe00
+-
+-#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
+-#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
+-#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
+-#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
+-#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
+-#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
+-#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
+-#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
+-#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
+-#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
+-#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
+-#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
+-
+-#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
+-#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
+-
+-#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
+-#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
+-#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
+-#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
+-#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
+-
+-#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
+-#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
+-#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
+-#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
+-#define AT91_RTC_DAY (7 << 21) /* Current Day */
+-#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
+-
+-#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
+-#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
+-#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
+-#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
+-
+-#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
+-#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
+-#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
+-
+-#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
+-#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
+-#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
+-#define AT91_RTC_SECEV (1 << 2) /* Second Event */
+-#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
+-#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
+-
+-#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
+-#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
+-#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
+-#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
+-
+-#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
+-#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
+-#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
+-#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
+-#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
+-
+-
+-/*
+- * Memory Controller.
+- */
+-#define AT91_MC 0xf00
+-
+-#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
+-#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
+-
+-#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
+-#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
+-#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
+-#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
+-#define AT91_MC_ABTSZ_BYTE (0 << 8)
+-#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
+-#define AT91_MC_ABTSZ_WORD (2 << 8)
+-#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
+-#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
+-#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
+-#define AT91_MC_ABTTYP_FETCH (2 << 10)
+-#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
+-#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
+-#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
+-#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
+-#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
+-#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
+-#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
+-#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
+-
+-#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
+-
+-#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
+-#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
+-#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
+-#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
+-#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
+-
+-/* External Bus Interface (EBI) registers */
+-#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
+-#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
+-#define AT91_EBI_CS0A_SMC (0 << 0)
+-#define AT91_EBI_CS0A_BFC (1 << 0)
+-#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+-#define AT91_EBI_CS1A_SMC (0 << 1)
+-#define AT91_EBI_CS1A_SDRAMC (1 << 1)
+-#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
+-#define AT91_EBI_CS3A_SMC (0 << 3)
+-#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+-#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
+-#define AT91_EBI_CS4A_SMC (0 << 4)
+-#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
+-#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
+-#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
+-
+-/* Static Memory Controller (SMC) registers */
+-#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+-#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
+-#define AT91_SMC_NWS_(x) ((x) << 0)
+-#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
+-#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
+-#define AT91_SMC_TDF_(x) ((x) << 8)
+-#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
+-#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
+-#define AT91_SMC_DBW_16 (1 << 13)
+-#define AT91_SMC_DBW_8 (2 << 13)
+-#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
+-#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
+-#define AT91_SMC_ACSS_STD (0 << 16)
+-#define AT91_SMC_ACSS_1 (1 << 16)
+-#define AT91_SMC_ACSS_2 (2 << 16)
+-#define AT91_SMC_ACSS_3 (3 << 16)
+-#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
+-#define AT91_SMC_RWSETUP_(x) ((x) << 24)
+-#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
+-#define AT91_SMC_RWHOLD_(x) ((x) << 28)
+-
+-/* SDRAM Controller registers */
+-#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
+-#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
+-#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
+-#define AT91_SDRAMC_MODE_NOP (1 << 0)
+-#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
+-#define AT91_SDRAMC_MODE_LMR (3 << 0)
+-#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
+-#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
+-#define AT91_SDRAMC_DBW_32 (0 << 4)
+-#define AT91_SDRAMC_DBW_16 (1 << 4)
+-
+-#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
+-#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
+-
+-#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
+-#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
+-#define AT91_SDRAMC_NC_8 (0 << 0)
+-#define AT91_SDRAMC_NC_9 (1 << 0)
+-#define AT91_SDRAMC_NC_10 (2 << 0)
+-#define AT91_SDRAMC_NC_11 (3 << 0)
+-#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
+-#define AT91_SDRAMC_NR_11 (0 << 2)
+-#define AT91_SDRAMC_NR_12 (1 << 2)
+-#define AT91_SDRAMC_NR_13 (2 << 2)
+-#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
+-#define AT91_SDRAMC_NB_2 (0 << 4)
+-#define AT91_SDRAMC_NB_4 (1 << 4)
+-#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
+-#define AT91_SDRAMC_CAS_2 (2 << 5)
+-#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
+-#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
+-#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
+-#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
+-#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
+-#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
+-
+-#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
+-#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
+-#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
+-#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
+-#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
+-#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
+-
+-/* Burst Flash Controller register */
+-#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
+-#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
+-#define AT91_BFC_BFCOM_DISABLED (0 << 0)
+-#define AT91_BFC_BFCOM_ASYNC (1 << 0)
+-#define AT91_BFC_BFCOM_BURST (2 << 0)
+-#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
+-#define AT91_BFC_BFCC_MCK (1 << 2)
+-#define AT91_BFC_BFCC_DIV2 (2 << 2)
+-#define AT91_BFC_BFCC_DIV4 (3 << 2)
+-#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
+-#define AT91_BFC_PAGES (7 << 8) /* Page Size */
+-#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
+-#define AT91_BFC_PAGES_16 (1 << 8)
+-#define AT91_BFC_PAGES_32 (2 << 8)
+-#define AT91_BFC_PAGES_64 (3 << 8)
+-#define AT91_BFC_PAGES_128 (4 << 8)
+-#define AT91_BFC_PAGES_256 (5 << 8)
+-#define AT91_BFC_PAGES_512 (6 << 8)
+-#define AT91_BFC_PAGES_1024 (7 << 8)
+-#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
+-#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
+-#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
+-#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
+-#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
+-
+-#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h Mon Dec 4 16:34:19 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h Thu Jan 1 02:00:00 1970
+@@ -1,146 +0,0 @@
+-/*
+- * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+- *
+- * Copyright (C) SAN People
+- *
+- * Timer/Counter Unit (TC) registers.
+- * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef AT91RM9200_TC_H
+-#define AT91RM9200_TC_H
+-
+-#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
+-#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
+-
+-#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
+-#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
+-#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
+-#define AT91_TC_TC0XC0S_NONE (1 << 0)
+-#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
+-#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
+-#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
+-#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
+-#define AT91_TC_TC1XC1S_NONE (1 << 2)
+-#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
+-#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
+-#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
+-#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
+-#define AT91_TC_TC2XC2S_NONE (1 << 4)
+-#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
+-#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
+-
+-
+-#define AT91_TC_CCR 0x00 /* Channel Control Register */
+-#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
+-#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
+-#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
+-
+-#define AT91_TC_CMR 0x04 /* Channel Mode Register */
+-#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
+-#define AT91_TC_TIMER_CLOCK1 (0 << 0)
+-#define AT91_TC_TIMER_CLOCK2 (1 << 0)
+-#define AT91_TC_TIMER_CLOCK3 (2 << 0)
+-#define AT91_TC_TIMER_CLOCK4 (3 << 0)
+-#define AT91_TC_TIMER_CLOCK5 (4 << 0)
+-#define AT91_TC_XC0 (5 << 0)
+-#define AT91_TC_XC1 (6 << 0)
+-#define AT91_TC_XC2 (7 << 0)
+-#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
+-#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
+-#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
+-#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
+-#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
+-#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
+-#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
+-#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
+-#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
+-#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
+-
+-#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
+-#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
+-#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
+-#define AT91_TC_EEVTEDG_NONE (0 << 8)
+-#define AT91_TC_EEVTEDG_RISING (1 << 8)
+-#define AT91_TC_EEVTEDG_FALLING (2 << 8)
+-#define AT91_TC_EEVTEDG_BOTH (3 << 8)
+-#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
+-#define AT91_TC_EEVT_TIOB (0 << 10)
+-#define AT91_TC_EEVT_XC0 (1 << 10)
+-#define AT91_TC_EEVT_XC1 (2 << 10)
+-#define AT91_TC_EEVT_XC2 (3 << 10)
+-#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
+-#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
+-#define AT91_TC_WAVESEL_UP (0 << 13)
+-#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
+-#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
+-#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
+-#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
+-#define AT91_TC_ACPA_NONE (0 << 16)
+-#define AT91_TC_ACPA_SET (1 << 16)
+-#define AT91_TC_ACPA_CLEAR (2 << 16)
+-#define AT91_TC_ACPA_TOGGLE (3 << 16)
+-#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
+-#define AT91_TC_ACPC_NONE (0 << 18)
+-#define AT91_TC_ACPC_SET (1 << 18)
+-#define AT91_TC_ACPC_CLEAR (2 << 18)
+-#define AT91_TC_ACPC_TOGGLE (3 << 18)
+-#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
+-#define AT91_TC_AEEVT_NONE (0 << 20)
+-#define AT91_TC_AEEVT_SET (1 << 20)
+-#define AT91_TC_AEEVT_CLEAR (2 << 20)
+-#define AT91_TC_AEEVT_TOGGLE (3 << 20)
+-#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
+-#define AT91_TC_ASWTRG_NONE (0 << 22)
+-#define AT91_TC_ASWTRG_SET (1 << 22)
+-#define AT91_TC_ASWTRG_CLEAR (2 << 22)
+-#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
+-#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
+-#define AT91_TC_BCPB_NONE (0 << 24)
+-#define AT91_TC_BCPB_SET (1 << 24)
+-#define AT91_TC_BCPB_CLEAR (2 << 24)
+-#define AT91_TC_BCPB_TOGGLE (3 << 24)
+-#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
+-#define AT91_TC_BCPC_NONE (0 << 26)
+-#define AT91_TC_BCPC_SET (1 << 26)
+-#define AT91_TC_BCPC_CLEAR (2 << 26)
+-#define AT91_TC_BCPC_TOGGLE (3 << 26)
+-#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
+-#define AT91_TC_BEEVT_NONE (0 << 28)
+-#define AT91_TC_BEEVT_SET (1 << 28)
+-#define AT91_TC_BEEVT_CLEAR (2 << 28)
+-#define AT91_TC_BEEVT_TOGGLE (3 << 28)
+-#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
+-#define AT91_TC_BSWTRG_NONE (0 << 30)
+-#define AT91_TC_BSWTRG_SET (1 << 30)
+-#define AT91_TC_BSWTRG_CLEAR (2 << 30)
+-#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
+-
+-#define AT91_TC_CV 0x10 /* Counter Value */
+-#define AT91_TC_RA 0x14 /* Register A */
+-#define AT91_TC_RB 0x18 /* Register B */
+-#define AT91_TC_RC 0x1c /* Register C */
+-
+-#define AT91_TC_SR 0x20 /* Status Register */
+-#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
+-#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
+-#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
+-#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
+-#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
+-#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
+-#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
+-#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
+-#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
+-#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
+-#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
+-
+-#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
+-#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
+-#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
+-
+-#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h Mon Dec 4 16:41:04 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h Thu Jan 1 02:00:00 1970
+@@ -1,57 +0,0 @@
+-/*
+- * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+- *
+- * Copyright (C) 2005 Ivan Kokshaysky
+- * Copyright (C) SAN People
+- *
+- * Two-wire Interface (TWI) registers.
+- * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef AT91RM9200_TWI_H
+-#define AT91RM9200_TWI_H
+-
+-#define AT91_TWI_CR 0x00 /* Control Register */
+-#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
+-#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
+-#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
+-#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
+-#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
+-
+-#define AT91_TWI_MMR 0x04 /* Master Mode Register */
+-#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
+-#define AT91_TWI_IADRSZ_NO (0 << 8)
+-#define AT91_TWI_IADRSZ_1 (1 << 8)
+-#define AT91_TWI_IADRSZ_2 (2 << 8)
+-#define AT91_TWI_IADRSZ_3 (3 << 8)
+-#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
+-#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
+-
+-#define AT91_TWI_IADR 0x0c /* Internal Address Register */
+-
+-#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
+-#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
+-#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
+-#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
+-
+-#define AT91_TWI_SR 0x20 /* Status Register */
+-#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
+-#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
+-#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
+-#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */
+-#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */
+-#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
+-
+-#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
+-#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
+-#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
+-#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
+-#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
+-
+-#endif
+-
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h Mon Dec 4 16:34:19 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h Thu Jan 1 02:00:00 1970
+@@ -1,77 +0,0 @@
+-/*
+- * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
+- *
+- * Copyright (C) 2005 Ivan Kokshaysky
+- * Copyright (C) SAN People
+- *
+- * USB Device Port (UDP) registers.
+- * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef AT91RM9200_UDP_H
+-#define AT91RM9200_UDP_H
+-
+-#define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */
+-#define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */
+-#define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */
+-#define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */
+-
+-#define AT91_UDP_GLB_STAT 0x04 /* Global State Register */
+-#define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */
+-#define AT91_UDP_CONFG (1 << 1) /* Configured */
+-#define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */
+-#define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */
+-#define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */
+-
+-#define AT91_UDP_FADDR 0x08 /* Function Address Register */
+-#define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */
+-#define AT91_UDP_FEN (1 << 8) /* Function Enable */
+-
+-#define AT91_UDP_IER 0x10 /* Interrupt Enable Register */
+-#define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */
+-#define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */
+-
+-#define AT91_UDP_ISR 0x1c /* Interrupt Status Register */
+-#define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */
+-#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
+-#define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */
+-#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status */
+-#define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */
+-#define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrpt Status */
+-#define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status */
+-
+-#define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */
+-#define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */
+-
+-#define AT91_UDP_CSR(n) (0x30 + ((n) * 4)) /* Endpoint Control/Status Registers 0-7 */
+-#define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */
+-#define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */
+-#define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */
+-#define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */
+-#define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */
+-#define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */
+-#define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */
+-#define AT91_UDP_DIR (1 << 7) /* Transfer Direction */
+-#define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */
+-#define AT91_UDP_EPTYPE_CTRL (0 << 8)
+-#define AT91_UDP_EPTYPE_ISO_OUT (1 << 8)
+-#define AT91_UDP_EPTYPE_BULK_OUT (2 << 8)
+-#define AT91_UDP_EPTYPE_INT_OUT (3 << 8)
+-#define AT91_UDP_EPTYPE_ISO_IN (5 << 8)
+-#define AT91_UDP_EPTYPE_BULK_IN (6 << 8)
+-#define AT91_UDP_EPTYPE_INT_IN (7 << 8)
+-#define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */
+-#define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */
+-#define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */
+-
+-#define AT91_UDP_FDR(n) (0x50 + ((n) * 4)) /* Endpoint FIFO Data Registers 0-7 */
+-
+-#define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */
+-#define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */
+-
+-#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9260.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9260.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9260.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9260.h Wed Nov 15 08:54:30 2006
+@@ -0,0 +1,125 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91sam9260.h
++ *
++ * (C) 2006 Andrew Victor
++ *
++ * Common definitions.
++ * Based on AT91SAM9260 datasheet revision A (Preliminary).
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91SAM9260_H
++#define AT91SAM9260_H
++
++/*
++ * Peripheral identifiers/interrupts.
++ */
++#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
++#define AT91_ID_SYS 1 /* System Peripherals */
++#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
++#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
++#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
++#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
++#define AT91SAM9260_ID_US0 6 /* USART 0 */
++#define AT91SAM9260_ID_US1 7 /* USART 1 */
++#define AT91SAM9260_ID_US2 8 /* USART 2 */
++#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
++#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
++#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
++#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
++#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
++#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
++#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
++#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
++#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
++#define AT91SAM9260_ID_UHP 20 /* USB Host port */
++#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
++#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
++#define AT91SAM9260_ID_US3 23 /* USART 3 */
++#define AT91SAM9260_ID_US4 24 /* USART 4 */
++#define AT91SAM9260_ID_US5 25 /* USART 5 */
++#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
++#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
++#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
++#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
++#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
++#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
++
++
++/*
++ * User Peripheral physical base addresses.
++ */
++#define AT91SAM9260_BASE_TCB0 0xfffa0000
++#define AT91SAM9260_BASE_TC0 0xfffa0000
++#define AT91SAM9260_BASE_TC1 0xfffa0040
++#define AT91SAM9260_BASE_TC2 0xfffa0080
++#define AT91SAM9260_BASE_UDP 0xfffa4000
++#define AT91SAM9260_BASE_MCI 0xfffa8000
++#define AT91SAM9260_BASE_TWI 0xfffac000
++#define AT91SAM9260_BASE_US0 0xfffb0000
++#define AT91SAM9260_BASE_US1 0xfffb4000
++#define AT91SAM9260_BASE_US2 0xfffb8000
++#define AT91SAM9260_BASE_SSC 0xfffbc000
++#define AT91SAM9260_BASE_ISI 0xfffc0000
++#define AT91SAM9260_BASE_EMAC 0xfffc4000
++#define AT91SAM9260_BASE_SPI0 0xfffc8000
++#define AT91SAM9260_BASE_SPI1 0xfffcc000
++#define AT91SAM9260_BASE_US3 0xfffd0000
++#define AT91SAM9260_BASE_US4 0xfffd4000
++#define AT91SAM9260_BASE_US5 0xfffd8000
++#define AT91SAM9260_BASE_TCB1 0xfffdc000
++#define AT91SAM9260_BASE_TC3 0xfffdc000
++#define AT91SAM9260_BASE_TC4 0xfffdc040
++#define AT91SAM9260_BASE_TC5 0xfffdc080
++#define AT91SAM9260_BASE_ADC 0xfffe0000
++#define AT91_BASE_SYS 0xffffe800
++
++/*
++ * System Peripherals (offset from AT91_BASE_SYS)
++ */
++#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
++#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
++#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
++#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
++#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
++#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
++#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
++#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
++#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
++#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
++#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
++#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
++#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
++#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
++#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
++#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
++#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
++
++
++/*
++ * Internal Memory.
++ */
++#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
++#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
++
++#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
++#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
++#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
++#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
++
++#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
++
++#if 0
++/*
++ * PIO pin definitions (peripheral A/B multiplexing).
++ */
++
++// TODO: Add
++
++#endif
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h Thu Nov 23 17:05:07 2006
+@@ -0,0 +1,78 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
++ *
++ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
++ * Based on AT91SAM9260 datasheet revision B.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91SAM9260_MATRIX_H
++#define AT91SAM9260_MATRIX_H
++
++#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
++#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
++#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
++#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
++#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
++#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */
++#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
++#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
++#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
++#define AT91_MATRIX_ULBT_FOUR (2 << 0)
++#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
++#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
++
++#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
++#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
++#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
++#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
++#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
++#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
++#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
++#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
++#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
++#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
++#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
++#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
++#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
++#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
++
++#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
++#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
++#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
++#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
++#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
++#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
++#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
++#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
++#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
++#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
++#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
++
++#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
++#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
++#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
++
++#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
++#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
++#define AT91_MATRIX_CS1A_SMC (0 << 1)
++#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
++#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
++#define AT91_MATRIX_CS3A_SMC (0 << 3)
++#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
++#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
++#define AT91_MATRIX_CS4A_SMC (0 << 4)
++#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
++#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
++#define AT91_MATRIX_CS5A_SMC (0 << 5)
++#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
++#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
++#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
++#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
++#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9261.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9261.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9261.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9261.h Fri Nov 10 10:08:55 2006
+@@ -0,0 +1,292 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91sam9261.h
++ *
++ * Copyright (C) SAN People
++ *
++ * Common definitions.
++ * Based on AT91SAM9261 datasheet revision E. (Preliminary)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91SAM9261_H
++#define AT91SAM9261_H
++
++/*
++ * Peripheral identifiers/interrupts.
++ */
++#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
++#define AT91_ID_SYS 1 /* System Peripherals */
++#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
++#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
++#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
++#define AT91SAM9261_ID_US0 6 /* USART 0 */
++#define AT91SAM9261_ID_US1 7 /* USART 1 */
++#define AT91SAM9261_ID_US2 8 /* USART 2 */
++#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
++#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
++#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
++#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
++#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
++#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
++#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
++#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
++#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
++#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
++#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
++#define AT91SAM9261_ID_UHP 20 /* USB Host port */
++#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
++#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
++#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
++#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
++
++
++/*
++ * User Peripheral physical base addresses.
++ */
++#define AT91SAM9261_BASE_TCB0 0xfffa0000
++#define AT91SAM9261_BASE_TC0 0xfffa0000
++#define AT91SAM9261_BASE_TC1 0xfffa0040
++#define AT91SAM9261_BASE_TC2 0xfffa0080
++#define AT91SAM9261_BASE_UDP 0xfffa4000
++#define AT91SAM9261_BASE_MCI 0xfffa8000
++#define AT91SAM9261_BASE_TWI 0xfffac000
++#define AT91SAM9261_BASE_US0 0xfffb0000
++#define AT91SAM9261_BASE_US1 0xfffb4000
++#define AT91SAM9261_BASE_US2 0xfffb8000
++#define AT91SAM9261_BASE_SSC0 0xfffbc000
++#define AT91SAM9261_BASE_SSC1 0xfffc0000
++#define AT91SAM9261_BASE_SSC2 0xfffc4000
++#define AT91SAM9261_BASE_SPI0 0xfffc8000
++#define AT91SAM9261_BASE_SPI1 0xfffcc000
++#define AT91_BASE_SYS 0xffffea00
++
++
++/*
++ * System Peripherals (offset from AT91_BASE_SYS)
++ */
++#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
++#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
++#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
++#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
++#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
++#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
++#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
++#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
++#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
++#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
++#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
++#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
++#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
++#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
++#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
++
++
++/*
++ * Internal Memory.
++ */
++#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
++#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
++
++#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
++#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
++
++#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
++#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
++
++
++#if 0
++/*
++ * PIO pin definitions (peripheral A/B multiplexing).
++ */
++#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */
++#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */
++#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */
++#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */
++#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */
++#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */
++#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */
++#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */
++#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */
++#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */
++#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */
++#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */
++#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */
++#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */
++#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */
++#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */
++#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */
++#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */
++#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */
++#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */
++#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */
++#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */
++#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */
++#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */
++#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */
++#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */
++#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */
++#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */
++#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */
++#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */
++#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */
++#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */
++#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */
++#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */
++#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */
++#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */
++#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */
++#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */
++#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */
++#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */
++#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */
++#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */
++#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */
++#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */
++#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */
++#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */
++#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */
++#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */
++#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */
++#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */
++#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */
++#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */
++#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */
++#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */
++#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */
++#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */
++#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */
++#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */
++#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */
++#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */
++#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */
++#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */
++#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */
++
++#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */
++#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */
++#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */
++#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */
++#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */
++#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */
++#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */
++#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */
++#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */
++#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */
++#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */
++#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */
++#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */
++#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */
++#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */
++#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */
++#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */
++#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */
++#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */
++#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */
++#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */
++#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */
++#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */
++#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */
++#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */
++#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */
++#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */
++#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */
++#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */
++#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */
++#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */
++#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */
++#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */
++#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */
++#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */
++#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */
++#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */
++#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */
++#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */
++#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */
++#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */
++#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */
++#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */
++#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */
++#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */
++#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */
++#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */
++#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */
++#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */
++#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */
++#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */
++#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */
++#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */
++#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */
++#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */
++#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */
++#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */
++#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */
++#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */
++#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */
++#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */
++
++#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */
++#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */
++#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */
++#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */
++#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */
++#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */
++#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */
++#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */
++#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */
++#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */
++#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */
++#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */
++#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */
++#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */
++#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */
++#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */
++#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */
++#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */
++#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */
++#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */
++#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */
++#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */
++#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */
++#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */
++#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */
++#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */
++#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */
++#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */
++#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */
++#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */
++#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */
++#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */
++#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */
++#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */
++#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
++#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */
++#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
++#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */
++#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
++#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */
++#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
++#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */
++#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
++#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */
++#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
++#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */
++#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */
++#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */
++#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */
++#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */
++#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */
++#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */
++#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */
++#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */
++#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */
++#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */
++#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */
++#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */
++#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */
++#endif
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h Thu Nov 23 17:08:24 2006
+@@ -0,0 +1,62 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
++ *
++ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
++ * Based on AT91SAM9261 datasheet revision D.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91SAM9261_MATRIX_H
++#define AT91SAM9261_MATRIX_H
++
++#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
++#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
++#define AT01_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
++
++#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
++#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
++#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
++#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
++#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
++#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
++#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
++#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
++#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
++#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
++#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
++
++#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
++#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
++#define AT91_MATRIX_ITCM_0 (0 << 0)
++#define AT91_MATRIX_ITCM_16 (5 << 0)
++#define AT91_MATRIX_ITCM_32 (6 << 0)
++#define AT91_MATRIX_ITCM_64 (7 << 0)
++#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
++#define AT91_MATRIX_DTCM_0 (0 << 4)
++#define AT91_MATRIX_DTCM_16 (5 << 4)
++#define AT91_MATRIX_DTCM_32 (6 << 4)
++#define AT91_MATRIX_DTCM_64 (7 << 4)
++
++#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
++#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
++#define AT91_MATRIX_CS1A_SMC (0 << 1)
++#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
++#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
++#define AT91_MATRIX_CS3A_SMC (0 << 3)
++#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
++#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
++#define AT91_MATRIX_CS4A_SMC (0 << 4)
++#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
++#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
++#define AT91_MATRIX_CS5A_SMC (0 << 5)
++#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
++#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
++
++#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
++#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h Mon Nov 13 12:27:30 2006
+@@ -0,0 +1,134 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
++ *
++ * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
++ * Based on AT91SAM9261 datasheet revision D.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91SAM926x_MC_H
++#define AT91SAM926x_MC_H
++
++/* SDRAM Controller (SDRAMC) registers */
++#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
++#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
++#define AT91_SDRAMC_MODE_NORMAL 0
++#define AT91_SDRAMC_MODE_NOP 1
++#define AT91_SDRAMC_MODE_PRECHARGE 2
++#define AT91_SDRAMC_MODE_LMR 3
++#define AT91_SDRAMC_MODE_REFRESH 4
++#define AT91_SDRAMC_MODE_EXT_LMR 5
++#define AT91_SDRAMC_MODE_DEEP 6
++
++#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
++#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
++
++#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
++#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
++#define AT91_SDRAMC_NC_8 (0 << 0)
++#define AT91_SDRAMC_NC_9 (1 << 0)
++#define AT91_SDRAMC_NC_10 (2 << 0)
++#define AT91_SDRAMC_NC_11 (3 << 0)
++#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
++#define AT91_SDRAMC_NR_11 (0 << 2)
++#define AT91_SDRAMC_NR_12 (1 << 2)
++#define AT91_SDRAMC_NR_13 (2 << 2)
++#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
++#define AT91_SDRAMC_NB_2 (0 << 4)
++#define AT91_SDRAMC_NB_4 (1 << 4)
++#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
++#define AT91_SDRAMC_CAS_1 (1 << 5)
++#define AT91_SDRAMC_CAS_2 (2 << 5)
++#define AT91_SDRAMC_CAS_3 (3 << 5)
++#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
++#define AT91_SDRAMC_DBW_32 (0 << 7)
++#define AT91_SDRAMC_DBW_16 (1 << 7)
++#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
++#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
++#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
++#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
++#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
++#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
++
++#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
++#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
++#define AT91_SDRAMC_LPCB_DISABLE 0
++#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
++#define AT91_SDRAMC_LPCB_POWER_DOWN 2
++#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
++#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
++#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
++#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
++#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
++#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
++#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
++#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
++
++#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
++#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
++#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
++#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
++#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
++
++#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
++#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
++#define AT91_SDRAMC_MD_SDRAM 0
++#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
++
++
++/* Static Memory Controller (SMC) registers */
++#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
++#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
++#define AT91_SMC_NWESETUP_(x) ((x) << 0)
++#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
++#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
++#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
++#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
++#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
++#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
++
++#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
++#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
++#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
++#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
++#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
++#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
++#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
++#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
++#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
++
++#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
++#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
++#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
++#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
++#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
++
++#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
++#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
++#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
++#define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */
++#define AT91_SMC_EXNWMODE_DISABLE (0 << 5)
++#define AT91_SMC_EXNWMODE_FROZEN (2 << 5)
++#define AT91_SMC_EXNWMODE_READY (3 << 5)
++#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
++#define AT91_SMC_BAT_SELECT (0 << 8)
++#define AT91_SMC_BAT_WRITE (1 << 8)
++#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
++#define AT91_SMC_DBW_8 (0 << 12)
++#define AT91_SMC_DBW_16 (1 << 12)
++#define AT91_SMC_DBW_32 (2 << 12)
++#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
++#define AT91_SMC_TDF_(x) ((x) << 16)
++#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
++#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
++#define AT91_SMC_PS (3 << 28) /* Page Size */
++#define AT91_SMC_PS_4 (0 << 28)
++#define AT91_SMC_PS_8 (1 << 28)
++#define AT91_SMC_PS_16 (2 << 28)
++#define AT91_SMC_PS_32 (3 << 28)
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/board.h linux-2.6.19/include/asm-arm/arch-at91rm9200/board.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/board.h Mon Dec 4 16:41:04 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/board.h Sat Nov 25 11:06:32 2006
+@@ -48,25 +48,26 @@
+ u8 det_pin; /* Card detect */
+ u8 vcc_pin; /* power switching */
+ u8 rst_pin; /* card reset */
++ u8 chipselect; /* EBI Chip Select number */
+ };
+ extern void __init at91_add_device_cf(struct at91_cf_data *data);
+
+ /* MMC / SD */
+ struct at91_mmc_data {
+ u8 det_pin; /* card detect IRQ */
+- unsigned is_b:1; /* uses B side (vs A) */
++ unsigned slot_b:1; /* uses Slot B */
+ unsigned wire4:1; /* (SD) supports DAT0..DAT3 */
+ u8 wp_pin; /* (SD) writeprotect detect */
+ u8 vcc_pin; /* power switching (high == on) */
+ };
+ extern void __init at91_add_device_mmc(struct at91_mmc_data *data);
+
+- /* Ethernet */
+-struct at91_eth_data {
++/* Ethernet (EMAC & MACB) */
++struct eth_platform_data {
+ u8 phy_irq_pin; /* PHY IRQ */
+ u8 is_rmii; /* using RMII interface? */
+ };
+-extern void __init at91_add_device_eth(struct at91_eth_data *data);
++extern void __init at91_add_device_eth(struct eth_platform_data *data);
+
+ /* USB Host */
+ struct at91_usbh_data {
+@@ -81,7 +82,8 @@
+ u8 rdy_pin; /* ready/busy */
+ u8 ale; /* address line number connected to ALE */
+ u8 cle; /* address line number connected to CLE */
+- struct mtd_partition* (*partition_info)(int, int*);
++ u8 bus_width_16; /* buswidth is 16 bit */
++ struct mtd_partition* (*partition_info)(int, int*);
+ };
+ extern void __init at91_add_device_nand(struct at91_nand_data *data);
+
+@@ -112,4 +114,13 @@
+ extern u8 at91_leds_timer;
+ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
+
++struct at91_gpio_led {
++ u8 index; /* index of LED */
++ char* name; /* name of LED */
++ u8 gpio; /* AT91_PIN_xx */
++ u8 flags; /* 1=active-high */
++ char* trigger; /* default trigger */
++};
++extern void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr);
++
+ #endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/cpu.h linux-2.6.19/include/asm-arm/arch-at91rm9200/cpu.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/cpu.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/cpu.h Wed Nov 15 11:59:16 2006
+@@ -0,0 +1,49 @@
++/*
++ * include/asm-arm/arch-at91rm9200/cpu.h
++ *
++ * Copyright (C) 2006 SAN People
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#ifndef __ASM_ARCH_CPU_H
++#define __ASM_ARCH_CPU_H
++
++#include <asm/hardware.h>
++#include <asm/arch/at91_dbgu.h>
++
++
++#define ARCH_ID_AT91RM9200 0x09290780
++#define ARCH_ID_AT91SAM9260 0x019803a0
++#define ARCH_ID_AT91SAM9261 0x019703a0
++
++
++static inline unsigned long at91_cpu_identify(void)
++{
++ return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
++}
++
++
++#ifdef CONFIG_ARCH_AT91RM9200
++#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
++#else
++#define cpu_is_at91rm9200() (0)
++#endif
++
++#ifdef CONFIG_ARCH_AT91SAM9260
++#define cpu_is_at91sam9260() (at91_cpu_identify() == ARCH_ID_AT91SAM9260)
++#else
++#define cpu_is_at91sam9260() (0)
++#endif
++
++#ifdef CONFIG_ARCH_AT91SAM9261
++#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
++#else
++#define cpu_is_at91sam9261() (0)
++#endif
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/debug-macro.S linux-2.6.19/include/asm-arm/arch-at91rm9200/debug-macro.S
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/debug-macro.S Tue May 30 11:42:13 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/debug-macro.S Tue Oct 24 16:04:30 2006
+@@ -12,6 +12,7 @@
+ */
+
+ #include <asm/hardware.h>
++#include <asm/arch/at91_dbgu.h>
+
+ .macro addruart,rx
+ mrc p15, 0, \rx, c1, c0
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/entry-macro.S linux-2.6.19/include/asm-arm/arch-at91rm9200/entry-macro.S
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/entry-macro.S Tue May 30 11:42:13 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/entry-macro.S Tue Oct 24 16:15:21 2006
+@@ -11,6 +11,7 @@
+ */
+
+ #include <asm/hardware.h>
++#include <asm/arch/at91_aic.h>
+
+ .macro disable_fiq
+ .endm
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/hardware.h linux-2.6.19/include/asm-arm/arch-at91rm9200/hardware.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/hardware.h Mon Dec 4 16:41:04 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/hardware.h Wed Nov 15 09:21:41 2006
+@@ -16,8 +16,16 @@
+
+ #include <asm/sizes.h>
+
++#if defined(CONFIG_ARCH_AT91RM9200)
+ #include <asm/arch/at91rm9200.h>
+-#include <asm/arch/at91rm9200_sys.h>
++#elif defined(CONFIG_ARCH_AT91SAM9260)
++#include <asm/arch/at91sam9260.h>
++#elif defined(CONFIG_ARCH_AT91SAM9261)
++#include <asm/arch/at91sam9261.h>
++#else
++#error "Unsupported AT91 processor"
++#endif
++
+
+ /*
+ * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
+@@ -34,29 +42,27 @@
+ * Virtual to Physical Address mapping for IO devices.
+ */
+ #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
+-#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI)
+ #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
+-#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI)
+-#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI)
+-#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP)
+
+ /* Internal SRAM is mapped below the IO devices */
+-#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
++#define AT91_SRAM_MAX SZ_1M
++#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
+
+ /* Serial ports */
+-#define ATMEL_MAX_UART 5 /* 4 USART3's and one DBGU port */
++#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */
+
+-/* FLASH */
+-#define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */
++/* External Memory Map */
++#define AT91_CHIPSELECT_0 0x10000000
++#define AT91_CHIPSELECT_1 0x20000000
++#define AT91_CHIPSELECT_2 0x30000000
++#define AT91_CHIPSELECT_3 0x40000000
++#define AT91_CHIPSELECT_4 0x50000000
++#define AT91_CHIPSELECT_5 0x60000000
++#define AT91_CHIPSELECT_6 0x70000000
++#define AT91_CHIPSELECT_7 0x80000000
+
+ /* SDRAM */
+-#define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */
+-
+-/* SmartMedia */
+-#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */
+-
+-/* Compact Flash */
+-#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */
++#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
+
+ /* Clocks */
+ #define AT91_SLOW_CLOCK 32768 /* slow clock */
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/ics1523.h linux-2.6.19/include/asm-arm/arch-at91rm9200/ics1523.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/ics1523.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/ics1523.h Tue Oct 17 08:29:21 2006
+@@ -0,0 +1,162 @@
++//*----------------------------------------------------------------------------
++//* ATMEL Microcontroller Software Support - ROUSSET -
++//*----------------------------------------------------------------------------
++//* The software is delivered "AS IS" without warranty or condition of any
++//* kind, either express, implied or statutory. This includes without
++//* limitation any warranty or condition with respect to merchantability or
++//* fitness for any particular purpose, or against the infringements of
++//* intellectual property rights of others.
++//*----------------------------------------------------------------------------
++//* File Name : ics1523.h
++//* Object : Clock Generator Prototyping File.
++//*
++//* 1.0 08/28/02 ED : Creation
++//* 1.2 13/01/03 FB : Update on lib V3
++//*----------------------------------------------------------------------------
++
++#ifndef ics1523_h
++#define ics1523_h
++
++/* Standard configurations definitions */
++#define Clock_Conf 0x0
++
++/*-------------------------------------------*/
++/* ICS1523 TWI Serial Clock Definition */
++/*-------------------------------------------*/
++
++#define ICS_MIN_CLOCK 100 /* Min Frequency Access Clock KHz */
++#define ICS_MAX_CLOCK 400 /* Max Frequency Access Clock KHz */
++#define ICS_TRANSFER_RATE ICS_MAX_CLOCK /* Transfer speed to apply */
++
++#define ICS_WRITE_CLK_PNB 30 /* TWCK Clock Periods required to write */
++#define ICS_READ_CLK_PNB 40 /* TWCK Clock Periods required to read */
++
++/*-------------------------------------------*/
++/* ICS1523 Write Operation Definition */
++/*-------------------------------------------*/
++
++#define ICS1523_ACCESS_OK 0 /* OK */
++#define ICS1523_ACCESS_ERROR -1 /* NOK */
++
++/*-------------------------------------------*/
++/* ICS1523 Device Addresses Definition */
++/*-------------------------------------------*/
++
++#define ICS_ADD 0x26 /* Device Address */
++
++/*--------------------------------------------------*/
++/* ICS1523 Registers Internal Addresses Definition */
++/*--------------------------------------------------*/
++
++#define ICS_ICR 0x0 /* Input Control Register */
++#define ICS_LCR 0x1 /* Loop Control Register */
++#define ICS_FD0 0x2 /* PLL FeedBack Divider LSBs */
++#define ICS_FD1 0x3 /* PLL FeedBack Divider MSBs */
++#define ICS_DPAO 0x4 /* Dynamic Phase Aligner Offset */
++#define ICS_DPAC 0x5 /* Dynamic Phase Aligner Resolution */
++#define ICS_OE 0x6 /* Output Enables Register */
++#define ICS_OD 0x7 /* Osc Divider Register */
++#define ICS_SWRST 0x8 /* DPA & PLL Reset Register */
++#define ICS_VID 0x10 /* Chip Version Register */
++#define ICS_RID 0x11 /* Chip Revision Register */
++#define ICS_SR 0x12 /* Status Register */
++
++/*------------------------------------------------------*/
++/* ICS1523 Input Control Register Bits Definition */
++/*------------------------------------------------------*/
++
++#define ICS_PDEN 0x1 /* Phase Detector Enable */
++#define ICS_PDPOL 0x2 /* Phase Detector Enable Polarity */
++#define ICS_REFPOL 0x4 /* External Reference Polarity */
++#define ICS_FBKPOL 0x8 /* External Feedback Polarity */
++#define ICS_FBKSEL 0x10 /* External Feedback Select */
++#define ICS_FUNCSEL 0x20 /* Function Out Select */
++#define ICS_ENPLS 0x40 /* Enable PLL Lock/Ref Status Output */
++#define ICS_ENDLS 0x80 /* Enable DPA Lock/Ref Status Output */
++
++/*-----------------------------------------------------*/
++/* ICS1523 Loop Control Register Bits Definition */
++/*-----------------------------------------------------*/
++
++#define ICS_PFD 0x7 /* Phase Detector Gain */
++#define ICS_PSD 0x30 /* Post-Scaler Divider */
++
++/*----------------------------------------------------*/
++/* ICS1523 PLL FeedBack Divider LSBs Definition */
++/*----------------------------------------------------*/
++
++#define ICS_FBDL 0xFF /* PLL FeedBack Divider LSBs */
++
++/*----------------------------------------------------*/
++/* ICS1523 PLL FeedBack Divider MSBs Definition */
++/*----------------------------------------------------*/
++
++#define ICS_FBDM 0xF /* PLL FeedBack Divider MSBs */
++
++/*------------------------------------------------------------*/
++/* ICS1523 Dynamic Phase Aligner Offset Bits Definition */
++/*------------------------------------------------------------*/
++
++#define ICS_DPAOS 0x2F /* Dynamic Phase Aligner Offset */
++#define ICS_FILSEL 0x80 /* Loop Filter Select */
++
++/*----------------------------------------------------------------*/
++/* ICS1523 Dynamic Phase Aligner Resolution Bits Definition */
++/*----------------------------------------------------------------*/
++
++#define ICS_DPARES 0x3 /* Dynamic Phase Aligner Resolution */
++#define ICS_MMREV 0xFC /* Metal Mask Revision Number */
++
++/*-------------------------------------------------------*/
++/* ICS1523 Output Enables Register Bits Definition */
++/*-------------------------------------------------------*/
++
++#define ICS_OEPCK 0x1 /* Output Enable for PECL PCLK Outputs */
++#define ICS_OETCK 0x2 /* Output Enable for STTL CLK Output */
++#define ICS_OEP2 0x4 /* Output Enable for PECL CLK/2 Outputs */
++#define ICS_OET2 0x8 /* Output Enable for STTL CLK/2 Output */
++#define ICS_OEF 0x10 /* Output Enable for STTL FUNC Output */
++#define ICS_CLK2INV 0x20 /* CLK/2 Invert */
++#define ICS_OSCL 0xC0 /* SSTL Clock Scaler */
++
++/*----------------------------------------------------*/
++/* ICS1523 Osc Divider Register Bits Definition */
++/*----------------------------------------------------*/
++
++#define ICS_OSCDIV 0x7F /* Oscillator Divider Modulus */
++#define ICS_INSEL 0x80 /* Input Select */
++
++/*---------------------------------------------------*/
++/* ICS1523 DPA & PLL Reset Register Definition */
++/*---------------------------------------------------*/
++
++#define ICS_DPAR 0x0A /* DPA Reset Command */
++#define ICS_PLLR 0x50 /* PLL Reset Command */
++
++/*------------------------------------------------*/
++/* ICS1523 Chip Version Register Definition */
++/*------------------------------------------------*/
++
++#define ICS_CHIPV 0xFF /* Chip Version */
++
++/*-------------------------------------------------*/
++/* ICS1523 Chip Revision Register Definition */
++/*-------------------------------------------------*/
++
++#define ICS_CHIPR 0xFF /* Chip Revision */
++
++/*------------------------------------------*/
++/* ICS1523 Status Register Definition */
++/*------------------------------------------*/
++
++#define ICS_DPALOCK 0x1 /* DPA Lock Status */
++#define ICS_PLLLOCK 0x2 /* PLL Lock Status */
++
++/* Time constants definition */
++#define TIMEOUT_OF_300us 3 // (10*100)us
++#define TIMEOUT_OF_1000us 10 // (10*100)us
++
++/* Function Prototyping ics1523.c */
++int AT91F_ICS1523_clockinit(void);
++
++#endif /* ics1523_h */
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/irqs.h linux-2.6.19/include/asm-arm/arch-at91rm9200/irqs.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/irqs.h Mon Dec 4 16:41:04 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/irqs.h Tue Oct 24 16:15:59 2006
+@@ -21,6 +21,8 @@
+ #ifndef __ASM_ARCH_IRQS_H
+ #define __ASM_ARCH_IRQS_H
+
++#include <asm/arch/at91_aic.h>
++
+ #define NR_AIC_IRQS 32
+
+
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/spi.h linux-2.6.19/include/asm-arm/arch-at91rm9200/spi.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/spi.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/spi.h Tue Oct 24 14:26:47 2006
+@@ -0,0 +1,54 @@
++/*
++ * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200
++ *
++ * (c) SAN People (Pty) Ltd
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ */
++
++#ifndef AT91_LEGACY_SPI_H
++#define AT91_LEGACY_SPI_H
++
++#define SPI_MAJOR 153 /* registered device number */
++
++#define DEFAULT_SPI_CLK 6000000
++
++
++/* Maximum number of buffers in a single SPI transfer.
++ * DataFlash uses maximum of 2
++ * spidev interface supports up to 8.
++ */
++#define MAX_SPI_TRANSFERS 8
++#define NR_SPI_DEVICES 4 /* number of devices on SPI bus */
++
++/*
++ * Describes the buffers for a SPI transfer.
++ * A transmit & receive buffer must be specified for each transfer
++ */
++struct spi_transfer_list {
++ void* tx[MAX_SPI_TRANSFERS]; /* transmit */
++ int txlen[MAX_SPI_TRANSFERS];
++ void* rx[MAX_SPI_TRANSFERS]; /* receive */
++ int rxlen[MAX_SPI_TRANSFERS];
++ int nr_transfers; /* number of transfers */
++ int curr; /* current transfer */
++};
++
++struct spi_local {
++ unsigned int pcs; /* Peripheral Chip Select value */
++
++ struct spi_transfer_list *xfers; /* current transfer list */
++ dma_addr_t tx, rx; /* DMA address for current transfer */
++ dma_addr_t txnext, rxnext; /* DMA address for next transfer */
++};
++
++
++/* Exported functions */
++extern void spi_access_bus(short device);
++extern void spi_release_bus(short device);
++extern int spi_transfer(struct spi_transfer_list* list);
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/system.h linux-2.6.19/include/asm-arm/arch-at91rm9200/system.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/system.h Mon Dec 4 16:34:19 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/system.h Mon Dec 4 16:00:33 2006
+@@ -22,6 +22,8 @@
+ #define __ASM_ARCH_SYSTEM_H
+
+ #include <asm/hardware.h>
++#include <asm/arch/at91_st.h>
++#include <asm/arch/at91_dbgu.h>
+
+ static inline void arch_idle(void)
+ {
+@@ -39,21 +41,13 @@
+ cpu_do_idle();
+ }
+
+-static inline void arch_reset(char mode)
+-{
+- /*
+- * Perform a hardware reset with the use of the Watchdog timer.
+- */
+- at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+- at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
+-}
+-
+-#define ARCH_ID_AT91RM9200 0x09200080
+-#define ARCH_ID_AT91SAM9261 0x019000a0
++void (*at91_arch_reset)(void);
+
+-static inline unsigned long arch_identify(void)
++static inline void arch_reset(char mode)
+ {
+- return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH);
++ /* call the CPU-specific reset function */
++ if (at91_arch_reset)
++ (at91_arch_reset)();
+ }
+
+ #endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/timex.h linux-2.6.19/include/asm-arm/arch-at91rm9200/timex.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/timex.h Mon Dec 4 16:34:19 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/timex.h Wed Nov 15 08:55:07 2006
+@@ -23,6 +23,15 @@
+
+ #include <asm/hardware.h>
+
++#if defined(CONFIG_ARCH_AT91RM9200)
++
+ #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
+
++#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
++
++#define AT91SAM9_MASTER_CLOCK 99300000
++#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
++
++#endif
++
+ #endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/uncompress.h linux-2.6.19/include/asm-arm/arch-at91rm9200/uncompress.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/uncompress.h Mon Dec 4 16:34:19 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/uncompress.h Tue Oct 24 16:11:39 2006
+@@ -22,11 +22,11 @@
+ #define __ASM_ARCH_UNCOMPRESS_H
+
+ #include <asm/hardware.h>
++#include <asm/arch/at91_dbgu.h>
+
+ /*
+ * The following code assumes the serial port has already been
+- * initialized by the bootloader. We search for the first enabled
+- * port in the most probable order. If you didn't setup a port in
++ * initialized by the bootloader. If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+diff -urN -x CVS linux-2.6.19-final/include/asm-arm/arch-at91rm9200/vmalloc.h linux-2.6.19/include/asm-arm/arch-at91rm9200/vmalloc.h
+--- linux-2.6.19-final/include/asm-arm/arch-at91rm9200/vmalloc.h Mon Dec 4 16:34:19 2006
++++ linux-2.6.19/include/asm-arm/arch-at91rm9200/vmalloc.h Wed Nov 1 15:26:48 2006
+@@ -21,6 +21,6 @@
+ #ifndef __ASM_ARCH_VMALLOC_H
+ #define __ASM_ARCH_VMALLOC_H
+
+-#define VMALLOC_END (AT91_SRAM_VIRT_BASE & PGDIR_MASK)
++#define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK)
+
+ #endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-avr32/arch-at32ap/at91_pdc.h linux-2.6.19/include/asm-avr32/arch-at32ap/at91_pdc.h
+--- linux-2.6.19-final/include/asm-avr32/arch-at32ap/at91_pdc.h Thu Jan 1 02:00:00 1970
++++ linux-2.6.19/include/asm-avr32/arch-at32ap/at91_pdc.h Tue Oct 24 15:32:59 2006
+@@ -0,0 +1,36 @@
++/*
++ * include/asm-arm/arch-at91rm9200/at91_pdc.h
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Peripheral Data Controller (PDC) registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_PDC_H
++#define AT91_PDC_H
++
++#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
++#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
++#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
++#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
++#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
++#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
++#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
++#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
++
++#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
++#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
++#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
++#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
++#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
++
++#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
++
++#endif
+diff -urN -x CVS linux-2.6.19-final/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h linux-2.6.19/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h
+--- linux-2.6.19-final/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h Mon Dec 4 16:41:06 2006
++++ linux-2.6.19/include/asm-avr32/arch-at32ap/at91rm9200_pdc.h Thu Jan 1 02:00:00 1970
+@@ -1,36 +0,0 @@
+-/*
+- * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+- *
+- * Copyright (C) 2005 Ivan Kokshaysky
+- * Copyright (C) SAN People
+- *
+- * Peripheral Data Controller (PDC) registers.
+- * Based on AT91RM9200 datasheet revision E.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef AT91RM9200_PDC_H
+-#define AT91RM9200_PDC_H
+-
+-#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
+-#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
+-#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
+-#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
+-#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
+-#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
+-#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
+-#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
+-
+-#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
+-#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
+-#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
+-#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
+-#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
+-
+-#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
+-
+-#endif
+diff -urN -x CVS linux-2.6.19-final/include/linux/i2c-id.h linux-2.6.19/include/linux/i2c-id.h
+--- linux-2.6.19-final/include/linux/i2c-id.h Mon Dec 4 16:41:13 2006
++++ linux-2.6.19/include/linux/i2c-id.h Thu Oct 12 17:07:39 2006
+@@ -202,6 +202,7 @@
+
+ /* --- PCA 9564 based algorithms */
+ #define I2C_HW_A_ISA 0x1a0000 /* generic ISA Bus interface card */
++#define I2C_HW_A_PLAT 0x1a0001 /* generic platform_bus interface */
+
+ /* --- ACPI Embedded controller algorithms */
+ #define I2C_HW_ACPI_EC 0x1f0000
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