clk: Convert __clk_get_flags() to clk_hw_get_flags()
authorStephen Boyd <sboyd@codeaurora.org>
Mon, 29 Jun 2015 23:56:30 +0000 (16:56 -0700)
committerMichael Turquette <mturquette@baylibre.com>
Mon, 24 Aug 2015 23:48:44 +0000 (16:48 -0700)
Mostly converted with the following snippet:

@@
struct clk_hw *E;
@@

-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)

Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
17 files changed:
drivers/clk/clk-cdce706.c
drivers/clk/clk-composite.c
drivers/clk/clk-divider.c
drivers/clk/clk-fixed-factor.c
drivers/clk/clk-si5351.c
drivers/clk/clk-stm32f4.c
drivers/clk/qcom/clk-rcg.c
drivers/clk/qcom/clk-rcg2.c
drivers/clk/st/clk-flexgen.c
drivers/clk/sunxi/clk-factors.c
drivers/clk/sunxi/clk-sunxi.c
drivers/clk/ti/clk.c
drivers/clk/ti/clockdomain.c
drivers/clk/ti/divider.c
drivers/clk/ti/dpll.c
drivers/clk/ti/dpll3xxx.c
drivers/clk/ti/interface.c

index 21830526fd8e98310f9f2e836a24e4634586fb77..01877f64eff6a764ec2fcc2e5e3ff1f88d8f3514 100644 (file)
@@ -310,7 +310,7 @@ static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,
        if (!mul)
                div = CDCE706_DIVIDER_DIVIDER_MAX;
 
-       if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                unsigned long best_diff = rate;
                unsigned long best_div = 0;
                struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];
index 7835cc4d1cf94b9a52a353fdabdcfad942ef9bec..15bbe7e96e104476b94430f02e8503da21ab966c 100644 (file)
@@ -78,7 +78,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
                   mux_hw && mux_ops && mux_ops->set_parent) {
                req->best_parent_hw = NULL;
 
-               if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {
+               if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
                        parent = clk_get_parent(mux_hw->clk);
                        req->best_parent_hw = __clk_get_hw(parent);
                        req->best_parent_rate = __clk_get_rate(parent);
index a417162537b8039e3e2377daf5087e40edb9a3d4..79003042aabb3c9b2ab284a0f08818ac4cc4a711 100644 (file)
@@ -290,7 +290,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
 
        maxdiv = _get_maxdiv(table, width, flags);
 
-       if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+       if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
                parent_rate = *best_parent_rate;
                bestdiv = _div_round(table, parent_rate, rate, flags);
                bestdiv = bestdiv == 0 ? 1 : bestdiv;
index fccabe497f6e5db42f6585acd9ecb1c4440bcb4e..4a8ebfd82734e5460811a8e5e7a80033eaad5cbb 100644 (file)
@@ -41,7 +41,7 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
 {
        struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
 
-       if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                unsigned long best_parent;
 
                best_parent = (rate / fix->mult) * fix->div;
index 9e6de57eae3b4c3c6e2ffd455bfdb4593be9df02..4b2ee39f05fd0f7cfda30e95ea50fb8694892e13 100644 (file)
@@ -663,7 +663,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
                divby4 = 1;
 
        /* multisync can set pll */
-       if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                /*
                 * find largest integer divider for max
                 * vco frequency and given target rate
@@ -1013,7 +1013,7 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
                rate = SI5351_CLKOUT_MIN_FREQ;
 
        /* request frequency if multisync master */
-       if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                /* use r divider for frequencies below 1MHz */
                rdiv = SI5351_OUTPUT_CLK_DIV_1;
                while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
index 3f6f7ad39490458a6e9cdcf4d944665abd34df86..5cfe50717536670ea7c2bb97cb5458f634ae5b7a 100644 (file)
@@ -175,7 +175,7 @@ static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
        if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
                mult = 2;
 
-       if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                unsigned long best_parent = rate / mult;
 
                *prate =
index e5c60826b7a940ce1321e26e28f14b2738e19800..070162abc2b64a7e842ba083dfb25bef3e0984be 100644 (file)
@@ -420,7 +420,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
        if (index < 0)
                return index;
 
-       clk_flags = __clk_get_flags(hw->clk);
+       clk_flags = clk_hw_get_flags(hw);
        p = clk_get_parent_by_index(hw->clk, index);
        if (clk_flags & CLK_SET_RATE_PARENT) {
                rate = rate * f->pre_div;
index d1d24917c531cdbc8c74782c9c53747d386a4006..98cf7192a61d12ff7349be2361cde3e06baa981a 100644 (file)
@@ -192,7 +192,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw,
        if (index < 0)
                return index;
 
-       clk_flags = __clk_get_flags(hw->clk);
+       clk_flags = clk_hw_get_flags(hw);
        p = clk_get_parent_by_index(hw->clk, index);
        if (clk_flags & CLK_SET_RATE_PARENT) {
                if (f->pre_div) {
index ec20a2c6f9f3219f17f7b3c89f266bf566b32a0b..965b13ba35153b9fec65a131b99da39f31b4d4e5 100644 (file)
@@ -109,7 +109,7 @@ static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
        /* Round div according to exact prate and wished rate */
        div = clk_best_div(*prate, rate);
 
-       if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                *prate = rate * div;
                return rate;
        }
index 574a3da33b5859d7b0c5413fe09e8745f13e9a22..b8c3ee5688f4b9f9abd3d262c511be18a3c22e8e 100644 (file)
@@ -92,7 +92,7 @@ static int clk_factors_determine_rate(struct clk_hw *hw,
                parent = clk_get_parent_by_index(clk, i);
                if (!parent)
                        continue;
-               if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
+               if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
                        parent_rate = __clk_round_rate(parent, req->rate);
                else
                        parent_rate = __clk_get_rate(parent);
index 4821231748a1eccf5533070f042cdf8ac69402d7..5911df9dcf13510ef14be84b0915e01831629897 100644 (file)
@@ -133,7 +133,7 @@ static int sun6i_ahb1_clk_determine_rate(struct clk_hw *hw,
                parent = clk_get_parent_by_index(clk, i);
                if (!parent)
                        continue;
-               if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
+               if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
                        parent_rate = __clk_round_rate(parent, req->rate);
                else
                        parent_rate = __clk_get_rate(parent);
index ace35047783ba99a84b95884294a8d0414c64285..b5bcd77e8d0f5e31b3887ebdd3a4f441c7909a46 100644 (file)
@@ -339,11 +339,11 @@ struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
        if (!IS_ERR(clk)) {
                setup->clk = clk;
                if (setup->clkdm_name) {
-                       if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+                       clk_hw = __clk_get_hw(clk);
+                       if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) {
                                pr_warn("can't setup clkdm for basic clk %s\n",
                                        setup->name);
                        } else {
-                               clk_hw = __clk_get_hw(clk);
                                to_clk_hw_omap(clk_hw)->clkdm_name =
                                        setup->clkdm_name;
                                omap2_init_clk_clkdm(clk_hw);
index 08a38c954510b7b8eea332ae30eb82eba2b83057..362a62c103115e2debdb38098e91f7c669b16ba7 100644 (file)
@@ -120,12 +120,12 @@ static void __init of_ti_clockdomain_setup(struct device_node *node)
                               __func__, node->full_name, i, PTR_ERR(clk));
                        continue;
                }
-               if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+               clk_hw = __clk_get_hw(clk);
+               if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) {
                        pr_warn("can't setup clkdm for basic clk %s\n",
                                __clk_get_name(clk));
                        continue;
                }
-               clk_hw = __clk_get_hw(clk);
                to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
                omap2_init_clk_clkdm(clk_hw);
        }
index ff5f117950a933b354c3bf5ba339e3e1a5b2dcd3..b6b2ac37dfadc1b43bb6348ac7732307e84ad89b 100644 (file)
@@ -155,7 +155,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
 
        maxdiv = _get_maxdiv(divider);
 
-       if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+       if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
                parent_rate = *best_parent_rate;
                bestdiv = DIV_ROUND_UP(parent_rate, rate);
                bestdiv = bestdiv == 0 ? 1 : bestdiv;
index 3999894149a97f045195d0f144944b169b4f2376..5519b386edc02f74992620d99d8d32921523b5b0 100644 (file)
@@ -163,7 +163,7 @@ static void __init _register_dpll(struct clk_hw *hw,
        clk = clk_register(NULL, &clk_hw->hw);
 
        if (!IS_ERR(clk)) {
-               omap2_init_clk_hw_omap_clocks(clk);
+               omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
                of_clk_add_provider(node, of_clk_src_simple_get, clk);
                kfree(clk_hw->hw.init->parent_names);
                kfree(clk_hw->hw.init);
@@ -320,7 +320,7 @@ static void _register_dpll_x2(struct device_node *node,
        if (IS_ERR(clk)) {
                kfree(clk_hw);
        } else {
-               omap2_init_clk_hw_omap_clocks(clk);
+               omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
                of_clk_add_provider(node, of_clk_src_simple_get, clk);
        }
 }
index b0aa87b35f243095eb2ebc4ce0b65e2153b38f5e..353a9b7720253eb0fec57e8f6d45d56e68c84fe4 100644 (file)
@@ -711,7 +711,7 @@ static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
                do {
                        parent = __clk_get_parent(hw->clk);
                        hw = __clk_get_hw(parent);
-               } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
+               } while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC));
                if (!hw)
                        break;
                pclk = to_clk_hw_omap(hw);
index c76230d8dd0464a073097cb70c4303cdf0e06056..e505e6f8228da6ada5ccb4beffd7aa0de78f1f1d 100644 (file)
@@ -63,7 +63,7 @@ static struct clk *_register_interface(struct device *dev, const char *name,
        if (IS_ERR(clk))
                kfree(clk_hw);
        else
-               omap2_init_clk_hw_omap_clocks(clk);
+               omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
 
        return clk;
 }