dt-bindings: phy: dp83867: Add documentation for disabling clock output
authorTrent Piepho <tpiepho@impinj.com>
Wed, 22 May 2019 18:43:21 +0000 (18:43 +0000)
committerDavid S. Miller <davem@davemloft.net>
Thu, 23 May 2019 00:40:17 +0000 (17:40 -0700)
The clock output is generally only used for testing and development and
not used to daisy-chain PHYs.  It's just a source of RF noise afterward.

Add a mux value for "off".  I've added it as another enumeration to the
output property.  In the actual PHY, the mux and the output enable are
independently controllable.  However, it doesn't seem useful to be able
to describe the mux setting when the output is disabled.

Document that PHY's default setting will be left as is if the property
is omitted.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Documentation/devicetree/bindings/net/ti,dp83867.txt
include/dt-bindings/net/ti-dp83867.h

index 99b8681bde49a66d5733dfaeb0fba669ae0d9dd2..db6aa3f2215be1ca6ca09966bdb399236fe2b269 100644 (file)
@@ -33,8 +33,10 @@ Optional property:
                                    software needs to take when this pin is
                                    strapped in these modes. See data manual
                                    for details.
-       - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h
-                                   for applicable values.
+       - ti,clk-output-sel - Muxing option for CLK_OUT pin.  See dt-bindings/net/ti-dp83867.h
+                             for applicable values.  The CLK_OUT pin can also
+                             be disabled by this property.  When omitted, the
+                             PHY's default will be left as is.
 
 Note: ti,min-output-impedance and ti,max-output-impedance are mutually
       exclusive. When both properties are present ti,max-output-impedance
index 7b1656427cbe428fd5796d51afe534cd86505918..192b79439eb743325f99a38950e716b9e9652f7e 100644 (file)
@@ -56,4 +56,6 @@
 #define DP83867_CLK_O_SEL_CHN_C_TCLK           0xA
 #define DP83867_CLK_O_SEL_CHN_D_TCLK           0xB
 #define DP83867_CLK_O_SEL_REF_CLK              0xC
+/* Special flag to indicate clock should be off */
+#define DP83867_CLK_O_SEL_OFF                  0xFFFFFFFF
 #endif