drm/amdgpu: drop support for untouched registers

I couldn't figure out what this was original good for, but we
don't use it any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index eb2240ce5fa826261eab2e090775ad7ba294d331..3608f165a705a38fedd86b5b7575fd0dbb16f3cf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1298,7 +1298,6 @@ struct amdgpu_smumgr {
  */
 struct amdgpu_allowed_register_entry {
        uint32_t reg_offset;
-       bool untouched;
        bool grbm_indexed;
 };
 

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 9d33e56414194d4fc22d378c26140adae0d25c6a..581d432765d4beb6bb5fa5d74f3e1a818810105b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -964,62 +964,62 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
 }
 
 static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
-       {mmGRBM_STATUS, false},
-       {mmGB_ADDR_CONFIG, false},
-       {mmMC_ARB_RAMCFG, false},
-       {mmGB_TILE_MODE0, false},
-       {mmGB_TILE_MODE1, false},
-       {mmGB_TILE_MODE2, false},
-       {mmGB_TILE_MODE3, false},
-       {mmGB_TILE_MODE4, false},
-       {mmGB_TILE_MODE5, false},
-       {mmGB_TILE_MODE6, false},
-       {mmGB_TILE_MODE7, false},
-       {mmGB_TILE_MODE8, false},
-       {mmGB_TILE_MODE9, false},
-       {mmGB_TILE_MODE10, false},
-       {mmGB_TILE_MODE11, false},
-       {mmGB_TILE_MODE12, false},
-       {mmGB_TILE_MODE13, false},
-       {mmGB_TILE_MODE14, false},
-       {mmGB_TILE_MODE15, false},
-       {mmGB_TILE_MODE16, false},
-       {mmGB_TILE_MODE17, false},
-       {mmGB_TILE_MODE18, false},
-       {mmGB_TILE_MODE19, false},
-       {mmGB_TILE_MODE20, false},
-       {mmGB_TILE_MODE21, false},
-       {mmGB_TILE_MODE22, false},
-       {mmGB_TILE_MODE23, false},
-       {mmGB_TILE_MODE24, false},
-       {mmGB_TILE_MODE25, false},
-       {mmGB_TILE_MODE26, false},
-       {mmGB_TILE_MODE27, false},
-       {mmGB_TILE_MODE28, false},
-       {mmGB_TILE_MODE29, false},
-       {mmGB_TILE_MODE30, false},
-       {mmGB_TILE_MODE31, false},
-       {mmGB_MACROTILE_MODE0, false},
-       {mmGB_MACROTILE_MODE1, false},
-       {mmGB_MACROTILE_MODE2, false},
-       {mmGB_MACROTILE_MODE3, false},
-       {mmGB_MACROTILE_MODE4, false},
-       {mmGB_MACROTILE_MODE5, false},
-       {mmGB_MACROTILE_MODE6, false},
-       {mmGB_MACROTILE_MODE7, false},
-       {mmGB_MACROTILE_MODE8, false},
-       {mmGB_MACROTILE_MODE9, false},
-       {mmGB_MACROTILE_MODE10, false},
-       {mmGB_MACROTILE_MODE11, false},
-       {mmGB_MACROTILE_MODE12, false},
-       {mmGB_MACROTILE_MODE13, false},
-       {mmGB_MACROTILE_MODE14, false},
-       {mmGB_MACROTILE_MODE15, false},
-       {mmCC_RB_BACKEND_DISABLE, false, true},
-       {mmGC_USER_RB_BACKEND_DISABLE, false, true},
-       {mmGB_BACKEND_MAP, false, false},
-       {mmPA_SC_RASTER_CONFIG, false, true},
-       {mmPA_SC_RASTER_CONFIG_1, false, true},
+       {mmGRBM_STATUS},
+       {mmGB_ADDR_CONFIG},
+       {mmMC_ARB_RAMCFG},
+       {mmGB_TILE_MODE0},
+       {mmGB_TILE_MODE1},
+       {mmGB_TILE_MODE2},
+       {mmGB_TILE_MODE3},
+       {mmGB_TILE_MODE4},
+       {mmGB_TILE_MODE5},
+       {mmGB_TILE_MODE6},
+       {mmGB_TILE_MODE7},
+       {mmGB_TILE_MODE8},
+       {mmGB_TILE_MODE9},
+       {mmGB_TILE_MODE10},
+       {mmGB_TILE_MODE11},
+       {mmGB_TILE_MODE12},
+       {mmGB_TILE_MODE13},
+       {mmGB_TILE_MODE14},
+       {mmGB_TILE_MODE15},
+       {mmGB_TILE_MODE16},
+       {mmGB_TILE_MODE17},
+       {mmGB_TILE_MODE18},
+       {mmGB_TILE_MODE19},
+       {mmGB_TILE_MODE20},
+       {mmGB_TILE_MODE21},
+       {mmGB_TILE_MODE22},
+       {mmGB_TILE_MODE23},
+       {mmGB_TILE_MODE24},
+       {mmGB_TILE_MODE25},
+       {mmGB_TILE_MODE26},
+       {mmGB_TILE_MODE27},
+       {mmGB_TILE_MODE28},
+       {mmGB_TILE_MODE29},
+       {mmGB_TILE_MODE30},
+       {mmGB_TILE_MODE31},
+       {mmGB_MACROTILE_MODE0},
+       {mmGB_MACROTILE_MODE1},
+       {mmGB_MACROTILE_MODE2},
+       {mmGB_MACROTILE_MODE3},
+       {mmGB_MACROTILE_MODE4},
+       {mmGB_MACROTILE_MODE5},
+       {mmGB_MACROTILE_MODE6},
+       {mmGB_MACROTILE_MODE7},
+       {mmGB_MACROTILE_MODE8},
+       {mmGB_MACROTILE_MODE9},
+       {mmGB_MACROTILE_MODE10},
+       {mmGB_MACROTILE_MODE11},
+       {mmGB_MACROTILE_MODE12},
+       {mmGB_MACROTILE_MODE13},
+       {mmGB_MACROTILE_MODE14},
+       {mmGB_MACROTILE_MODE15},
+       {mmCC_RB_BACKEND_DISABLE, true},
+       {mmGC_USER_RB_BACKEND_DISABLE, true},
+       {mmGB_BACKEND_MAP, false},
+       {mmPA_SC_RASTER_CONFIG, true},
+       {mmPA_SC_RASTER_CONFIG_1, true},
 };
 
 static uint32_t cik_read_indexed_register(struct amdgpu_device *adev,
@@ -1050,11 +1050,10 @@ static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
                if (reg_offset != cik_allowed_read_registers[i].reg_offset)
                        continue;
 
-               if (!cik_allowed_read_registers[i].untouched)
-                       *value = cik_allowed_read_registers[i].grbm_indexed ?
-                                cik_read_indexed_register(adev, se_num,
-                                                          sh_num, reg_offset) :
-                                RREG32(reg_offset);
+               *value = cik_allowed_read_registers[i].grbm_indexed ?
+                        cik_read_indexed_register(adev, se_num,
+                                                  sh_num, reg_offset) :
+                        RREG32(reg_offset);
                return 0;
        }
        return -EINVAL;

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index c0b1aabf282f5a7a2eaf3e0d3fcfe30da84e0d5f..3bd633226eceb46ec80358e7b52abba4896d935b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -971,44 +971,44 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 }
 
 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
-       {GRBM_STATUS, false},
-       {GB_ADDR_CONFIG, false},
-       {MC_ARB_RAMCFG, false},
-       {GB_TILE_MODE0, false},
-       {GB_TILE_MODE1, false},
-       {GB_TILE_MODE2, false},
-       {GB_TILE_MODE3, false},
-       {GB_TILE_MODE4, false},
-       {GB_TILE_MODE5, false},
-       {GB_TILE_MODE6, false},
-       {GB_TILE_MODE7, false},
-       {GB_TILE_MODE8, false},
-       {GB_TILE_MODE9, false},
-       {GB_TILE_MODE10, false},
-       {GB_TILE_MODE11, false},
-       {GB_TILE_MODE12, false},
-       {GB_TILE_MODE13, false},
-       {GB_TILE_MODE14, false},
-       {GB_TILE_MODE15, false},
-       {GB_TILE_MODE16, false},
-       {GB_TILE_MODE17, false},
-       {GB_TILE_MODE18, false},
-       {GB_TILE_MODE19, false},
-       {GB_TILE_MODE20, false},
-       {GB_TILE_MODE21, false},
-       {GB_TILE_MODE22, false},
-       {GB_TILE_MODE23, false},
-       {GB_TILE_MODE24, false},
-       {GB_TILE_MODE25, false},
-       {GB_TILE_MODE26, false},
-       {GB_TILE_MODE27, false},
-       {GB_TILE_MODE28, false},
-       {GB_TILE_MODE29, false},
-       {GB_TILE_MODE30, false},
-       {GB_TILE_MODE31, false},
-       {CC_RB_BACKEND_DISABLE, false, true},
-       {GC_USER_RB_BACKEND_DISABLE, false, true},
-       {PA_SC_RASTER_CONFIG, false, true},
+       {GRBM_STATUS},
+       {GB_ADDR_CONFIG},
+       {MC_ARB_RAMCFG},
+       {GB_TILE_MODE0},
+       {GB_TILE_MODE1},
+       {GB_TILE_MODE2},
+       {GB_TILE_MODE3},
+       {GB_TILE_MODE4},
+       {GB_TILE_MODE5},
+       {GB_TILE_MODE6},
+       {GB_TILE_MODE7},
+       {GB_TILE_MODE8},
+       {GB_TILE_MODE9},
+       {GB_TILE_MODE10},
+       {GB_TILE_MODE11},
+       {GB_TILE_MODE12},
+       {GB_TILE_MODE13},
+       {GB_TILE_MODE14},
+       {GB_TILE_MODE15},
+       {GB_TILE_MODE16},
+       {GB_TILE_MODE17},
+       {GB_TILE_MODE18},
+       {GB_TILE_MODE19},
+       {GB_TILE_MODE20},
+       {GB_TILE_MODE21},
+       {GB_TILE_MODE22},
+       {GB_TILE_MODE23},
+       {GB_TILE_MODE24},
+       {GB_TILE_MODE25},
+       {GB_TILE_MODE26},
+       {GB_TILE_MODE27},
+       {GB_TILE_MODE28},
+       {GB_TILE_MODE29},
+       {GB_TILE_MODE30},
+       {GB_TILE_MODE31},
+       {CC_RB_BACKEND_DISABLE, true},
+       {GC_USER_RB_BACKEND_DISABLE, true},
+       {PA_SC_RASTER_CONFIG, true},
 };
 
 static uint32_t si_get_register_value(struct amdgpu_device *adev,
@@ -1093,13 +1093,13 @@ static int si_read_register(struct amdgpu_device *adev, u32 se_num,
 
        *value = 0;
        for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
+               bool indexed = si_allowed_read_registers[i].grbm_indexed;
+
                if (reg_offset != si_allowed_read_registers[i].reg_offset)
                        continue;
 
-               if (!si_allowed_read_registers[i].untouched)
-                       *value = si_get_register_value(adev,
-                                               si_allowed_read_registers[i].grbm_indexed,
-                                               se_num, sh_num, reg_offset);
+               *value = si_get_register_value(adev, indexed, se_num, sh_num,
+                                              reg_offset);
                return 0;
        }
        return -EINVAL;

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 6b55d451ae7f94cd1c3342bc87f1cb37edac76e8..68ce1e8e9b64a8f96e85026b036324cead3913fe 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -285,24 +285,24 @@ static struct amdgpu_allowed_register_entry vega10_allowed_read_registers[] = {
 };
 
 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
-       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS), false},
-       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2), false},
-       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0), false},
-       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1), false},
-       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2), false},
-       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3), false},
-       { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG), false},
-       { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_STAT), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
-       { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
-       { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
+       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)},
+       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)},
+       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)},
+       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)},
+       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)},
+       { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)},
+       { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG)},
+       { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG)},
+       { SOC15_REG_OFFSET(GC, 0, mmCP_STAT)},
+       { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)},
+       { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)},
+       { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)},
+       { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)},
+       { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)},
+       { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)},
+       { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)},
+       { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)},
+       { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)},
 };
 
 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
@@ -360,10 +360,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
                        asic_register_entry = asic_register_table + i;
                        if (reg_offset != asic_register_entry->reg_offset)
                                continue;
-                       if (!asic_register_entry->untouched)
-                               *value = soc15_get_register_value(adev,
-                                                                 asic_register_entry->grbm_indexed,
-                                                                 se_num, sh_num, reg_offset);
+                       *value = soc15_get_register_value(adev,
+                                                         asic_register_entry->grbm_indexed,
+                                                         se_num, sh_num, reg_offset);
                        return 0;
                }
        }
@@ -372,10 +371,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
                if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
                        continue;
 
-               if (!soc15_allowed_read_registers[i].untouched)
-                       *value = soc15_get_register_value(adev,
-                                                         soc15_allowed_read_registers[i].grbm_indexed,
-                                                         se_num, sh_num, reg_offset);
+               *value = soc15_get_register_value(adev,
+                                                 soc15_allowed_read_registers[i].grbm_indexed,
+                                                 se_num, sh_num, reg_offset);
                return 0;
        }
        return -EINVAL;

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index c3b767dd82ef5916ae939bca6b52f9f406a1c591..0decc44ae4e1039e1b6d8d25393533b1621ea8a5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -470,82 +470,82 @@ static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] =
 };
 
 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
-       {mmGRBM_STATUS, false},
-       {mmGRBM_STATUS2, false},
-       {mmGRBM_STATUS_SE0, false},
-       {mmGRBM_STATUS_SE1, false},
-       {mmGRBM_STATUS_SE2, false},
-       {mmGRBM_STATUS_SE3, false},
-       {mmSRBM_STATUS, false},
-       {mmSRBM_STATUS2, false},
-       {mmSRBM_STATUS3, false},
-       {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
-       {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
-       {mmCP_STAT, false},
-       {mmCP_STALLED_STAT1, false},
-       {mmCP_STALLED_STAT2, false},
-       {mmCP_STALLED_STAT3, false},
-       {mmCP_CPF_BUSY_STAT, false},
-       {mmCP_CPF_STALLED_STAT1, false},
-       {mmCP_CPF_STATUS, false},
-       {mmCP_CPC_BUSY_STAT, false},
-       {mmCP_CPC_STALLED_STAT1, false},
-       {mmCP_CPC_STATUS, false},
-       {mmGB_ADDR_CONFIG, false},
-       {mmMC_ARB_RAMCFG, false},
-       {mmGB_TILE_MODE0, false},
-       {mmGB_TILE_MODE1, false},
-       {mmGB_TILE_MODE2, false},
-       {mmGB_TILE_MODE3, false},
-       {mmGB_TILE_MODE4, false},
-       {mmGB_TILE_MODE5, false},
-       {mmGB_TILE_MODE6, false},
-       {mmGB_TILE_MODE7, false},
-       {mmGB_TILE_MODE8, false},
-       {mmGB_TILE_MODE9, false},
-       {mmGB_TILE_MODE10, false},
-       {mmGB_TILE_MODE11, false},
-       {mmGB_TILE_MODE12, false},
-       {mmGB_TILE_MODE13, false},
-       {mmGB_TILE_MODE14, false},
-       {mmGB_TILE_MODE15, false},
-       {mmGB_TILE_MODE16, false},
-       {mmGB_TILE_MODE17, false},
-       {mmGB_TILE_MODE18, false},
-       {mmGB_TILE_MODE19, false},
-       {mmGB_TILE_MODE20, false},
-       {mmGB_TILE_MODE21, false},
-       {mmGB_TILE_MODE22, false},
-       {mmGB_TILE_MODE23, false},
-       {mmGB_TILE_MODE24, false},
-       {mmGB_TILE_MODE25, false},
-       {mmGB_TILE_MODE26, false},
-       {mmGB_TILE_MODE27, false},
-       {mmGB_TILE_MODE28, false},
-       {mmGB_TILE_MODE29, false},
-       {mmGB_TILE_MODE30, false},
-       {mmGB_TILE_MODE31, false},
-       {mmGB_MACROTILE_MODE0, false},
-       {mmGB_MACROTILE_MODE1, false},
-       {mmGB_MACROTILE_MODE2, false},
-       {mmGB_MACROTILE_MODE3, false},
-       {mmGB_MACROTILE_MODE4, false},
-       {mmGB_MACROTILE_MODE5, false},
-       {mmGB_MACROTILE_MODE6, false},
-       {mmGB_MACROTILE_MODE7, false},
-       {mmGB_MACROTILE_MODE8, false},
-       {mmGB_MACROTILE_MODE9, false},
-       {mmGB_MACROTILE_MODE10, false},
-       {mmGB_MACROTILE_MODE11, false},
-       {mmGB_MACROTILE_MODE12, false},
-       {mmGB_MACROTILE_MODE13, false},
-       {mmGB_MACROTILE_MODE14, false},
-       {mmGB_MACROTILE_MODE15, false},
-       {mmCC_RB_BACKEND_DISABLE, false, true},
-       {mmGC_USER_RB_BACKEND_DISABLE, false, true},
-       {mmGB_BACKEND_MAP, false, false},
-       {mmPA_SC_RASTER_CONFIG, false, true},
-       {mmPA_SC_RASTER_CONFIG_1, false, true},
+       {mmGRBM_STATUS},
+       {mmGRBM_STATUS2},
+       {mmGRBM_STATUS_SE0},
+       {mmGRBM_STATUS_SE1},
+       {mmGRBM_STATUS_SE2},
+       {mmGRBM_STATUS_SE3},
+       {mmSRBM_STATUS},
+       {mmSRBM_STATUS2},
+       {mmSRBM_STATUS3},
+       {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
+       {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
+       {mmCP_STAT},
+       {mmCP_STALLED_STAT1},
+       {mmCP_STALLED_STAT2},
+       {mmCP_STALLED_STAT3},
+       {mmCP_CPF_BUSY_STAT},
+       {mmCP_CPF_STALLED_STAT1},
+       {mmCP_CPF_STATUS},
+       {mmCP_CPC_BUSY_STAT},
+       {mmCP_CPC_STALLED_STAT1},
+       {mmCP_CPC_STATUS},
+       {mmGB_ADDR_CONFIG},
+       {mmMC_ARB_RAMCFG},
+       {mmGB_TILE_MODE0},
+       {mmGB_TILE_MODE1},
+       {mmGB_TILE_MODE2},
+       {mmGB_TILE_MODE3},
+       {mmGB_TILE_MODE4},
+       {mmGB_TILE_MODE5},
+       {mmGB_TILE_MODE6},
+       {mmGB_TILE_MODE7},
+       {mmGB_TILE_MODE8},
+       {mmGB_TILE_MODE9},
+       {mmGB_TILE_MODE10},
+       {mmGB_TILE_MODE11},
+       {mmGB_TILE_MODE12},
+       {mmGB_TILE_MODE13},
+       {mmGB_TILE_MODE14},
+       {mmGB_TILE_MODE15},
+       {mmGB_TILE_MODE16},
+       {mmGB_TILE_MODE17},
+       {mmGB_TILE_MODE18},
+       {mmGB_TILE_MODE19},
+       {mmGB_TILE_MODE20},
+       {mmGB_TILE_MODE21},
+       {mmGB_TILE_MODE22},
+       {mmGB_TILE_MODE23},
+       {mmGB_TILE_MODE24},
+       {mmGB_TILE_MODE25},
+       {mmGB_TILE_MODE26},
+       {mmGB_TILE_MODE27},
+       {mmGB_TILE_MODE28},
+       {mmGB_TILE_MODE29},
+       {mmGB_TILE_MODE30},
+       {mmGB_TILE_MODE31},
+       {mmGB_MACROTILE_MODE0},
+       {mmGB_MACROTILE_MODE1},
+       {mmGB_MACROTILE_MODE2},
+       {mmGB_MACROTILE_MODE3},
+       {mmGB_MACROTILE_MODE4},
+       {mmGB_MACROTILE_MODE5},
+       {mmGB_MACROTILE_MODE6},
+       {mmGB_MACROTILE_MODE7},
+       {mmGB_MACROTILE_MODE8},
+       {mmGB_MACROTILE_MODE9},
+       {mmGB_MACROTILE_MODE10},
+       {mmGB_MACROTILE_MODE11},
+       {mmGB_MACROTILE_MODE12},
+       {mmGB_MACROTILE_MODE13},
+       {mmGB_MACROTILE_MODE14},
+       {mmGB_MACROTILE_MODE15},
+       {mmCC_RB_BACKEND_DISABLE, true},
+       {mmGC_USER_RB_BACKEND_DISABLE, true},
+       {mmGB_BACKEND_MAP, false},
+       {mmPA_SC_RASTER_CONFIG, true},
+       {mmPA_SC_RASTER_CONFIG_1, true},
 };
 
 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
@@ -673,25 +673,25 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
 
        if (asic_register_table) {
                for (i = 0; i < size; i++) {
+                       bool indexed = asic_register_entry->grbm_indexed;
+
                        asic_register_entry = asic_register_table + i;
                        if (reg_offset != asic_register_entry->reg_offset)
                                continue;
-                       if (!asic_register_entry->untouched)
-                               *value = vi_get_register_value(adev,
-                                                              asic_register_entry->grbm_indexed,
-                                                              se_num, sh_num, reg_offset);
+                       *value = vi_get_register_value(adev, indexed, se_num,
+                                                      sh_num, reg_offset);
                        return 0;
                }
        }
 
        for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
+               bool indexed = vi_allowed_read_registers[i].grbm_indexed;
+
                if (reg_offset != vi_allowed_read_registers[i].reg_offset)
                        continue;
 
-               if (!vi_allowed_read_registers[i].untouched)
-                       *value = vi_get_register_value(adev,
-                                                      vi_allowed_read_registers[i].grbm_indexed,
-                                                      se_num, sh_num, reg_offset);
+               *value = vi_get_register_value(adev, indexed, se_num, sh_num,
+                                              reg_offset);
                return 0;
        }
        return -EINVAL;