drm/i915/glk: limit pixel clock to 99% of cdclk workaround

As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
Practically we can achive only 99% of these cdclk values (HW team
checking on this). So cdclk should be calculated for the given pixclk as
per that otherwise it may lead to screen corruption, explained below:
1. For DSI AUO panel(1920x1200 @60) required pixclk is 157100 KHZ
2. glk_calc_cdclk returns 79200 KHZ for this pixclk, For 2PPC it
   will be 158400 KHZ
3. Practically 100% of the cdclk can’t be achieved, so 99% of 158400
   KHZ  = 156816 which is less than the desired pixlclk and causes
   panel corruption.

v2: Rebased to new CDLCK code framework
v3: Addressed review comments from Ander/Jani
    - Add comment in code about 99% usage of CDCLK
    - Calculate max dot clock as well with 99% limit
v4 by Jani:
    - drop superfluous whitespace change
    - rewrite code comments to clarify
v5: Added details of non-working scenario in commit message

Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1491397463-13637-1-git-send-email-madhav.chauhan@intel.com

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index dd3ad52b7dfeac5e7d6f8eb59ee18b372f20a77f..763010f8ad8968e6f226e0f94a704069b4418b94 100644 (file)
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1071,9 +1071,15 @@ static int bxt_calc_cdclk(int max_pixclk)
 
 static int glk_calc_cdclk(int max_pixclk)
 {
-       if (max_pixclk > 2 * 158400)
+       /*
+        * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
+        * as a temporary workaround. Use a higher cdclk instead. (Note that
+        * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
+        * cdclk.)
+        */
+       if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
                return 316800;
-       else if (max_pixclk > 2 * 79200)
+       else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
                return 158400;
        else
                return 79200;
@@ -1664,7 +1670,11 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
        int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
        if (IS_GEMINILAKE(dev_priv))
-               return 2 * max_cdclk_freq;
+               /*
+                * FIXME: Limiting to 99% as a temporary workaround. See
+                * glk_calc_cdclk() for details.
+                */
+               return 2 * max_cdclk_freq * 99 / 100;
        else if (INTEL_INFO(dev_priv)->gen >= 9 ||
                 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                return max_cdclk_freq;