i40e/i40evf: fix accidental write to ITR registers
authorJesse Brandeburg <jesse.brandeburg@intel.com>
Fri, 27 Feb 2015 09:18:32 +0000 (09:18 +0000)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Mon, 9 Mar 2015 12:20:46 +0000 (05:20 -0700)
Fix a bug introduced in the force writeback code, where the interrupt
rate was set to 0 (maximum) by accident.

The driver must correctly set the NOITR fields to avoid ITR update
as a side effect of triggering the software interrupt.

Change-ID: I290851ae04ef3811c43aab5ee33242029f26c1a3
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/i40e/i40e_txrx.c
drivers/net/ethernet/intel/i40evf/i40e_txrx.c
drivers/net/ethernet/intel/i40evf/i40evf_main.c

index f5a50b9366cbe6fe7b368e6f3255ff08f4099147..6beab943e93a920e1bb01b2769c7305a2611b635 100644 (file)
@@ -859,6 +859,7 @@ static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 {
        u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
+                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
                  I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
                  I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
                  /* allow 00 to be written to the index */
index d9f3db542c5f272290ebd10df36ab8fe7d92ab12..f41da5d8047bd84da79a295ae1543f0703fc658a 100644 (file)
@@ -371,6 +371,7 @@ static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 {
        u32 val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
+                 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
                  I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
                  I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
                  /* allow 00 to be written to the index */
index 32d0a99ad2a9989e889863b819824cb07408b27c..5ac777b99ede75512371a3ac519eccdeea4c7c4c 100644 (file)
@@ -244,6 +244,7 @@ void i40evf_irq_enable_queues(struct i40evf_adapter *adapter, u32 mask)
                if (mask & (1 << (i - 1))) {
                        wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1),
                             I40E_VFINT_DYN_CTLN1_INTENA_MASK |
+                            I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |
                             I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
                }
        }
@@ -263,6 +264,7 @@ static void i40evf_fire_sw_int(struct i40evf_adapter *adapter, u32 mask)
        if (mask & 1) {
                dyn_ctl = rd32(hw, I40E_VFINT_DYN_CTL01);
                dyn_ctl |= I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
+                          I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |
                           I40E_VFINT_DYN_CTLN_CLEARPBA_MASK;
                wr32(hw, I40E_VFINT_DYN_CTL01, dyn_ctl);
        }
@@ -270,6 +272,7 @@ static void i40evf_fire_sw_int(struct i40evf_adapter *adapter, u32 mask)
                if (mask & (1 << i)) {
                        dyn_ctl = rd32(hw, I40E_VFINT_DYN_CTLN1(i - 1));
                        dyn_ctl |= I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
+                                  I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |
                                   I40E_VFINT_DYN_CTLN_CLEARPBA_MASK;
                        wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), dyn_ctl);
                }