drm/i915: switch intel_wait_for_register to uncore

The intel_uncore structure is the owner of register access, so
subclass the function to it.

While at it, use a local uncore var and switch to the new read/write
functions where it makes sense.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-9-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 622b175b05fdd2e5b62a0309a40c51c179ef65dd..ca8a8891b7b3ef91b19eed3bef0f1c2ee1dde29e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2687,7 +2687,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
        if (!force_on)
                return 0;
 
-       err = intel_wait_for_register(dev_priv,
+       err = intel_wait_for_register(&dev_priv->uncore,
                                      VLV_GTLC_SURVIVABILITY_REG,
                                      VLV_GFX_CLK_STATUS_BIT,
                                      VLV_GFX_CLK_STATUS_BIT,

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 85c5cb779297d102ccf0e3a74fdfb6b156e24b9d..39a4804091d70d61a5fd63e7dfcb60d3edde4060 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1920,10 +1920,10 @@ static void i915_oa_stream_enable(struct i915_perf_stream *stream)
 
 static void gen7_oa_disable(struct i915_perf_stream *stream)
 {
-       struct drm_i915_private *dev_priv = stream->dev_priv;
+       struct intel_uncore *uncore = &stream->dev_priv->uncore;
 
-       I915_WRITE(GEN7_OACONTROL, 0);
-       if (intel_wait_for_register(dev_priv,
+       intel_uncore_write(uncore, GEN7_OACONTROL, 0);
+       if (intel_wait_for_register(uncore,
                                    GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
                                    50))
                DRM_ERROR("wait for OA to be disabled timed out\n");
@@ -1931,10 +1931,10 @@ static void gen7_oa_disable(struct i915_perf_stream *stream)
 
 static void gen8_oa_disable(struct i915_perf_stream *stream)
 {
-       struct drm_i915_private *dev_priv = stream->dev_priv;
+       struct intel_uncore *uncore = &stream->dev_priv->uncore;
 
-       I915_WRITE(GEN8_OACONTROL, 0);
-       if (intel_wait_for_register(dev_priv,
+       intel_uncore_write(uncore, GEN8_OACONTROL, 0);
+       if (intel_wait_for_register(uncore,
                                    GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
                                    50))
                DRM_ERROR("wait for OA to be disabled timed out\n");

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 1395338c6772cead5601e1aa15bf05c07ef2ce31..b67ffaa283dc45f1072312d3140c08bd22368148 100644 (file)
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -861,7 +861,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
                I915_WRITE(PIPECONF(dsi_trans), tmp);
 
                /* wait for transcoder to be enabled */
-               if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+               if (intel_wait_for_register(&dev_priv->uncore,
+                                           PIPECONF(dsi_trans),
                                            I965_PIPECONF_ACTIVE,
                                            I965_PIPECONF_ACTIVE, 10))
                        DRM_ERROR("DSI transcoder not enabled\n");
@@ -1039,7 +1040,8 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
                I915_WRITE(PIPECONF(dsi_trans), tmp);
 
                /* wait for transcoder to be disabled */
-               if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+               if (intel_wait_for_register(&dev_priv->uncore,
+                                           PIPECONF(dsi_trans),
                                            I965_PIPECONF_ACTIVE, 0, 50))
                        DRM_ERROR("DSI trancoder not disabled\n");
        }

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index d27ccd23d753a9d5ebbd37ad7dfd5a5914169939..d40f8793718cd721f7e0181c06ca3af25d119ed2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -965,7 +965,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 
        I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
                                    5))
                DRM_ERROR("DPLL0 not locked\n");
@@ -979,9 +979,9 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 {
        I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
-       if (intel_wait_for_register(dev_priv,
-                                  LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
-                                  1))
+       if (intel_wait_for_register(&dev_priv->uncore,
+                                   LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
+                                   1))
                DRM_ERROR("Couldn't disable DPLL0\n");
 
        dev_priv->cdclk.hw.vco = 0;
@@ -1324,7 +1324,7 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
        I915_WRITE(BXT_DE_PLL_ENABLE, 0);
 
        /* Timeout 200us */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
                                    1))
                DRM_ERROR("timeout waiting for DE PLL unlock\n");
@@ -1345,7 +1345,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
        I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
 
        /* Timeout 200us */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    BXT_DE_PLL_ENABLE,
                                    BXT_DE_PLL_LOCK,
                                    BXT_DE_PLL_LOCK,

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 3716b2ee362fde71b3d908ba489e91c569c9a6b3..50530e49982c5e80bd4da4a5c2e2d3caacc33c35 100644 (file)
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -435,7 +435,7 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 
                I915_WRITE(crt->adpa_reg, adpa);
 
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            crt->adpa_reg,
                                            ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
                                            1000))
@@ -489,7 +489,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 
        I915_WRITE(crt->adpa_reg, adpa);
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    crt->adpa_reg,
                                    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
                                    1000)) {
@@ -542,7 +542,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
                                              CRT_HOTPLUG_FORCE_DETECT,
                                              CRT_HOTPLUG_FORCE_DETECT);
                /* wait for FORCE_DETECT to go off */
-               if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
+               if (intel_wait_for_register(&dev_priv->uncore, PORT_HOTPLUG_EN,
                                            CRT_HOTPLUG_FORCE_DETECT, 0,
                                            1000))
                        DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ba3de1079e63a557363576ce46efcb8bd5c108b8..d33fe2952be3a4cf43e7f398dd5dcfe71777832e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3046,7 +3046,7 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
        val |= DP_TP_CTL_FEC_ENABLE;
        I915_WRITE(DP_TP_CTL(port), val);
 
-       if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+       if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
                                    DP_TP_STATUS_FEC_ENABLE_LIVE,
                                    DP_TP_STATUS_FEC_ENABLE_LIVE,
                                    1))

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 61c7bbd066e31bb73a1c0cd03c9373efcda71211..3371bf96dabdd7c85a96a47a37be03b9ded66a02 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1040,7 +1040,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
                i915_reg_t reg = PIPECONF(cpu_transcoder);
 
                /* Wait for the Pipe State to go off */
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            reg, I965_PIPECONF_ACTIVE, 0,
                                            100))
                        WARN(1, "pipe_off wait timed out\n");
@@ -1346,7 +1346,7 @@ static void _vlv_enable_pll(struct intel_crtc *crtc,
        POSTING_READ(DPLL(pipe));
        udelay(150);
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    DPLL(pipe),
                                    DPLL_LOCK_VLV,
                                    DPLL_LOCK_VLV,
@@ -1399,7 +1399,7 @@ static void _chv_enable_pll(struct intel_crtc *crtc,
        I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
 
        /* Check PLL is locked */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
                                    1))
                DRM_ERROR("PLL %d failed to lock\n", pipe);
@@ -1580,7 +1580,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
                BUG();
        }
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    dpll_reg, port_mask, expected_mask,
                                    1000))
                WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
@@ -1641,7 +1641,7 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
        }
 
        I915_WRITE(reg, val | TRANS_ENABLE);
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
                                    100))
                DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
@@ -1671,7 +1671,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
                val |= TRANS_PROGRESSIVE;
 
        I915_WRITE(LPT_TRANSCONF, val);
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    LPT_TRANSCONF,
                                    TRANS_STATE_ENABLE,
                                    TRANS_STATE_ENABLE,
@@ -1697,7 +1697,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
        val &= ~TRANS_ENABLE;
        I915_WRITE(reg, val);
        /* wait for PCH transcoder off, transcoder state */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    reg, TRANS_STATE_ENABLE, 0,
                                    50))
                DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
@@ -1719,7 +1719,7 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
        val &= ~TRANS_ENABLE;
        I915_WRITE(LPT_TRANSCONF, val);
        /* wait for PCH transcoder off, transcoder state */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
                                    50))
                DRM_ERROR("Failed to disable PCH transcoder\n");
@@ -5299,7 +5299,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
                 * and don't wait for vblanks until the end of crtc_enable, then
                 * the HW state readout code will complain that the expected
                 * IPS_CTL value is not the one we read. */
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            IPS_CTL, IPS_ENABLE, IPS_ENABLE,
                                            50))
                        DRM_ERROR("Timed out waiting for IPS enable\n");
@@ -5324,7 +5324,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
                 * 42ms timeout value leads to occasional timeouts so use 100ms
                 * instead.
                 */
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            IPS_CTL, IPS_ENABLE, 0,
                                            100))
                        DRM_ERROR("Timed out waiting for IPS disable\n");
@@ -9481,7 +9481,8 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
        I915_WRITE(LCPLL_CTL, val);
        POSTING_READ(LCPLL_CTL);
 
-       if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
+       if (intel_wait_for_register(&dev_priv->uncore,
+                                   LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
                DRM_ERROR("LCPLL still locked\n");
 
        val = hsw_read_dcomp(dev_priv);
@@ -9536,7 +9537,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
        val &= ~LCPLL_PLL_DISABLE;
        I915_WRITE(LCPLL_CTL, val);
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
                                    5))
                DRM_ERROR("LCPLL not locked yet\n");

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 326de12c3f44ae5c4204c8d16c55b4b854394e5a..74fe14103459aabcb0ec1149b5fb18c0721beee7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2348,7 +2348,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
                        I915_READ(pp_stat_reg),
                        I915_READ(pp_ctrl_reg));
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    pp_stat_reg, mask, value,
                                    5000))
                DRM_ERROR("Panel status timeout: status %08x control %08x\n",
@@ -3937,7 +3937,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
        if (port == PORT_A)
                return;
 
-       if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
+       if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
                                    DP_TP_STATUS_IDLE_DONE,
                                    DP_TP_STATUS_IDLE_DONE,
                                    1))

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index fb67cd93111789ca8c2a271e2ba758993ba49e60..ecad1f58ebf8cfbc038c4ee4be0e0567f1bdebcb 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -289,7 +289,7 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
 
        DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    DP_TP_STATUS(port),
                                    DP_TP_STATUS_ACT_SENT,
                                    DP_TP_STATUS_ACT_SENT,

diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index a0591b64070b75d910c747891dd882463e5236f7..db295c77ff0ddf1fbf4bde4c006b0b27625bb270 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -341,7 +341,7 @@ static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
                                  enum dpio_phy phy)
 {
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    BXT_PORT_REF_DW3(phy),
                                    GRC_DONE, GRC_DONE,
                                    10))

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index eeb659946203cde3517eb432c8e2cf76e62830c6..e01c057ce50bee7a30d83f1858ee5858c6932954 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -960,7 +960,7 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
        I915_WRITE(regs[id].ctl,
                   I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    DPLL_STATUS,
                                    DPLL_LOCK(id),
                                    DPLL_LOCK(id),
@@ -1977,7 +1977,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
        I915_WRITE(CNL_DPLL_ENABLE(id), val);
 
        /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    CNL_DPLL_ENABLE(id),
                                    PLL_POWER_STATE,
                                    PLL_POWER_STATE,
@@ -2018,7 +2018,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
        I915_WRITE(CNL_DPLL_ENABLE(id), val);
 
        /* 7. Wait for PLL lock status in DPLL_ENABLE. */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    CNL_DPLL_ENABLE(id),
                                    PLL_LOCK,
                                    PLL_LOCK,
@@ -2066,7 +2066,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
        I915_WRITE(CNL_DPLL_ENABLE(id), val);
 
        /* 4. Wait for PLL not locked status in DPLL_ENABLE. */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    CNL_DPLL_ENABLE(id),
                                    PLL_LOCK,
                                    0,
@@ -2088,7 +2088,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
        I915_WRITE(CNL_DPLL_ENABLE(id), val);
 
        /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    CNL_DPLL_ENABLE(id),
                                    PLL_POWER_STATE,
                                    0,
@@ -3050,8 +3050,8 @@ static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
         * The spec says we need to "wait" but it also says it should be
         * immediate.
         */
-       if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE,
-                                   PLL_POWER_STATE, 1))
+       if (intel_wait_for_register(&dev_priv->uncore, enable_reg,
+                                   PLL_POWER_STATE, PLL_POWER_STATE, 1))
                DRM_ERROR("PLL %d Power not enabled\n", pll->info->id);
 }
 
@@ -3066,8 +3066,8 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
        I915_WRITE(enable_reg, val);
 
        /* Timeout is actually 600us. */
-       if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK,
-                                   1))
+       if (intel_wait_for_register(&dev_priv->uncore, enable_reg,
+                                   PLL_LOCK, PLL_LOCK, 1))
                DRM_ERROR("PLL %d not locked\n", pll->info->id);
 }
 
@@ -3149,7 +3149,8 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
        I915_WRITE(enable_reg, val);
 
        /* Timeout is actually 1us. */
-       if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, 0, 1))
+       if (intel_wait_for_register(&dev_priv->uncore,
+                                   enable_reg, PLL_LOCK, 0, 1))
                DRM_ERROR("PLL %d locked\n", pll->info->id);
 
        /* DVFS post sequence would be here. See the comment above. */
@@ -3162,8 +3163,8 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
         * The spec says we need to "wait" but it also says it should be
         * immediate.
         */
-       if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE, 0,
-                                   1))
+       if (intel_wait_for_register(&dev_priv->uncore,
+                                   enable_reg, PLL_POWER_STATE, 0, 1))
                DRM_ERROR("PLL %d Power not disabled\n", pll->info->id);
 }
 

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 656e684e7c9a3a01009a044f05da6fffbe1d1a4c..43fe08be3b7d83acaa10a58e7f983c78f2bd63ba 100644 (file)
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -108,7 +108,7 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
        I915_WRITE(FBC_CONTROL, fbc_ctl);
 
        /* Wait for compressing bit to clear */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    FBC_STATUS, FBC_STAT_COMPRESSING, 0,
                                    10)) {
                DRM_DEBUG_KMS("FBC idle timed out\n");

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index fb9af193dbfc710837943a7bc8358601b3890e5c..3aabfa2d9198e74921f51a7d3b9e937527ce7f81 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -565,7 +565,7 @@ static int guc_sleep_state_action(struct intel_guc *guc,
        if (ret)
                return ret;
 
-       ret = __intel_wait_for_register(dev_priv, SOFT_SCRATCH(14),
+       ret = __intel_wait_for_register(&dev_priv->uncore, SOFT_SCRATCH(14),
                                        INTEL_GUC_SLEEP_STATE_INVALID_MASK,
                                        0, 0, 10, &status);
        if (ret)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 9ce09f67776d1f3c2a3dd0ec95316c8d3c02f7a1..86965fa377390a998ad9d40c79247d6e7d29678a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -225,7 +225,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
        }
 
        /* Wait for the keys to load (500us) */
-       ret = __intel_wait_for_register(dev_priv, HDCP_KEY_STATUS,
+       ret = __intel_wait_for_register(&dev_priv->uncore, HDCP_KEY_STATUS,
                                        HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
                                        10, 1, &val);
        if (ret)
@@ -243,7 +243,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
 static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
 {
        I915_WRITE(HDCP_SHA_TEXT, sha_text);
-       if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
+       if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL,
                                    HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) {
                DRM_ERROR("Timed out waiting for SHA1 ready\n");
                return -ETIMEDOUT;
@@ -474,7 +474,7 @@ int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
 
        /* Tell the HW we're done with the hash and wait for it to ACK */
        I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH);
-       if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
+       if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL,
                                    HDCP_SHA1_COMPLETE,
                                    HDCP_SHA1_COMPLETE, 1)) {
                DRM_ERROR("Timed out waiting for SHA1 complete\n");
@@ -604,7 +604,7 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
        I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
 
        /* Wait for An to be acquired */
-       if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
+       if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
                                    HDCP_STATUS_AN_READY,
                                    HDCP_STATUS_AN_READY, 1)) {
                DRM_ERROR("Timed out waiting for An\n");
@@ -685,7 +685,7 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
        }
 
        /* Wait for encryption confirmation */
-       if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
+       if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
                                    HDCP_STATUS_ENC, HDCP_STATUS_ENC,
                                    ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
                DRM_ERROR("Timed out waiting for encryption\n");
@@ -717,7 +717,8 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
 
        hdcp->hdcp_encrypted = false;
        I915_WRITE(PORT_HDCP_CONF(port), 0);
-       if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), ~0, 0,
+       if (intel_wait_for_register(&dev_priv->uncore,
+                                   PORT_HDCP_STATUS(port), ~0, 0,
                                    ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
                DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
                return -ETIMEDOUT;
@@ -1477,7 +1478,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
                           CTL_LINK_ENCRYPTION_REQ);
        }
 
-       ret = intel_wait_for_register(dev_priv, HDCP2_STATUS_DDI(port),
+       ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
                                      LINK_ENCRYPTION_STATUS,
                                      LINK_ENCRYPTION_STATUS,
                                      ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
@@ -1498,7 +1499,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
        I915_WRITE(HDCP2_CTL_DDI(port),
                   I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
 
-       ret = intel_wait_for_register(dev_priv, HDCP2_STATUS_DDI(port),
+       ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
                                      LINK_ENCRYPTION_STATUS, 0x0,
                                      ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
        if (ret == -ETIMEDOUT)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 9bd1c9002c2ad9095cf6d457308df63ef20787b8..94c04f16a2addd3a4eb83dc29bfe379db6e3796b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -79,7 +79,7 @@ int intel_huc_auth(struct intel_huc *huc)
        }
 
        /* Check authentication status, it should be done by now */
-       ret = __intel_wait_for_register(i915,
+       ret = __intel_wait_for_register(&i915->uncore,
                                        HUC_STATUS2,
                                        HUC_FW_VERIFIED,
                                        HUC_FW_VERIFIED,

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index ccd5ac6d3fcd592d2b80b2b17f461811242b49f4..34dd2d71814bbb64dca0a13fc26ff680a0829c19 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -311,7 +311,8 @@ static void intel_enable_lvds(struct intel_encoder *encoder,
        I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
        POSTING_READ(lvds_encoder->reg);
 
-       if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
+       if (intel_wait_for_register(&dev_priv->uncore,
+                                   PP_STATUS(0), PP_ON, PP_ON, 5000))
                DRM_ERROR("timed out waiting for panel to power on\n");
 
        intel_panel_enable_backlight(pipe_config, conn_state);
@@ -325,7 +326,8 @@ static void intel_disable_lvds(struct intel_encoder *encoder,
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
        I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
-       if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
+       if (intel_wait_for_register(&dev_priv->uncore,
+                                   PP_STATUS(0), PP_ON, 0, 1000))
                DRM_ERROR("timed out waiting for panel to power off\n");
 
        I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 605fe8fc85cca18f774d4e0a42e20f55b2d6f18c..ec874d802d48b23455232584a17d47eddcda80d5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -834,8 +834,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
        }
 
        /* Wait till PSR is idle */
-       if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,
-                                   2000))
+       if (intel_wait_for_register(&dev_priv->uncore,
+                                   psr_status, psr_status_mask, 0, 2000))
                DRM_ERROR("Timed out waiting PSR idle state\n");
 
        /* Disable PSR on Sink */
@@ -956,7 +956,7 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
         * defensive enough to cover everything.
         */
 
-       return __intel_wait_for_register(dev_priv, EDP_PSR_STATUS,
+       return __intel_wait_for_register(&dev_priv->uncore, EDP_PSR_STATUS,
                                         EDP_PSR_STATUS_STATE_MASK,
                                         EDP_PSR_STATUS_STATE_IDLE, 2, 50,
                                         out_value);
@@ -981,7 +981,7 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
 
        mutex_unlock(&dev_priv->psr.lock);
 
-       err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
+       err = intel_wait_for_register(&dev_priv->uncore, reg, mask, 0, 50);
        if (err)
                DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5103bada89002f84fdeed7c3dcfa0150c4357e0a..a5b4a2d9a49296d3c3525930e6e4c4de574c75ff 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -586,7 +586,7 @@ static void flush_cs_tlb(struct intel_engine_cs *engine)
        I915_WRITE(instpm,
                   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
                                      INSTPM_SYNC_FLUSH));
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    instpm, INSTPM_SYNC_FLUSH, 0,
                                    1000))
                DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
@@ -607,7 +607,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
 
        if (INTEL_GEN(dev_priv) > 2) {
                I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            RING_MI_MODE(engine->mmio_base),
                                            MODE_IDLE,
                                            MODE_IDLE,
@@ -699,7 +699,8 @@ static int init_ring_common(struct intel_engine_cs *engine)
        I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
 
        /* If the head is still not zero, the ring is dead */
-       if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
+       if (intel_wait_for_register(&dev_priv->uncore,
+                                   RING_CTL(engine->mmio_base),
                                    RING_VALID, RING_VALID,
                                    50)) {
                DRM_ERROR("%s initialization failed "

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 676a89bb8194387e7848b70e07c8bc1985bc7dd3..40ddfbb97acbdbaf226d715750fefdb53f8e4a19 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -565,7 +565,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
        int pw_idx = power_well->desc->hsw.idx;
 
        /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
-       WARN_ON(intel_wait_for_register(dev_priv,
+       WARN_ON(intel_wait_for_register(&dev_priv->uncore,
                                        regs->driver,
                                        HSW_PWR_WELL_CTL_STATE(pw_idx),
                                        HSW_PWR_WELL_CTL_STATE(pw_idx),
@@ -620,7 +620,7 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
                                           enum skl_power_gate pg)
 {
        /* Timeout 5us for PG#0, for other PGs 1us */
-       WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
+       WARN_ON(intel_wait_for_register(&dev_priv->uncore, SKL_FUSE_STATUS,
                                        SKL_FUSE_PG_DIST_STATUS(pg),
                                        SKL_FUSE_PG_DIST_STATUS(pg), 1));
 }
@@ -1521,7 +1521,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
         * The PHY may be busy with some initial calibration and whatnot,
         * so the power state can take a while to actually change.
         */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    DISPLAY_PHY_STATUS,
                                    phy_status_mask,
                                    phy_status,
@@ -1556,7 +1556,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
        vlv_set_power_well(dev_priv, power_well, true);
 
        /* Poll for phypwrgood signal */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    DISPLAY_PHY_STATUS,
                                    PHY_POWERGOOD(phy),
                                    PHY_POWERGOOD(phy),

diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 75c872bb8cc9d3fe0d9a0b19d1240035ff06fa4e..57de41b1f9892dd3582108413d9547a07a472e55 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -51,7 +51,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
 
        WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
                                    5)) {
                DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
@@ -63,7 +63,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
        I915_WRITE(VLV_IOSF_DATA, is_read ? 0 : *val);
        I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
                                    5)) {
                DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
@@ -208,7 +208,7 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
        u32 value = 0;
        WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    SBI_CTL_STAT, SBI_BUSY, 0,
                                    100)) {
                DRM_ERROR("timeout waiting for SBI to become ready\n");
@@ -224,7 +224,7 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
                value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
        I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    SBI_CTL_STAT,
                                    SBI_BUSY,
                                    0,
@@ -248,7 +248,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 
        WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    SBI_CTL_STAT, SBI_BUSY, 0,
                                    100)) {
                DRM_ERROR("timeout waiting for SBI to become ready\n");
@@ -264,7 +264,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
                tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
        I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    SBI_CTL_STAT,
                                    SBI_BUSY,
                                    0,

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 83a8ae5c8e75953cd7d1018dd6d7d90c7e3a669a..35d9ce33bf83b2be167781c6aae13f2b205232c9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1831,15 +1831,14 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
  *
  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
  */
-int __intel_wait_for_register(struct drm_i915_private *dev_priv,
-                           i915_reg_t reg,
-                           u32 mask,
-                           u32 value,
-                           unsigned int fast_timeout_us,
-                           unsigned int slow_timeout_ms,
-                           u32 *out_value)
-{
-       struct intel_uncore *uncore = &dev_priv->uncore;
+int __intel_wait_for_register(struct intel_uncore *uncore,
+                             i915_reg_t reg,
+                             u32 mask,
+                             u32 value,
+                             unsigned int fast_timeout_us,
+                             unsigned int slow_timeout_ms,
+                             u32 *out_value)
+{
        unsigned fw =
                intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
        u32 reg_value;

diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 7d83fbd8fc2dbe4b579ea60bab0902ca291cde76..06762501e9eeeb8aa4fb010f1d6285e824ff6bfd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -213,7 +213,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
 
-int __intel_wait_for_register(struct drm_i915_private *dev_priv,
+int __intel_wait_for_register(struct intel_uncore *uncore,
                              i915_reg_t reg,
                              u32 mask,
                              u32 value,
@@ -221,13 +221,13 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
                              unsigned int slow_timeout_ms,
                              u32 *out_value);
 static inline int
-intel_wait_for_register(struct drm_i915_private *dev_priv,
+intel_wait_for_register(struct intel_uncore *uncore,
                        i915_reg_t reg,
                        u32 mask,
                        u32 value,
                        unsigned int timeout_ms)
 {
-       return __intel_wait_for_register(dev_priv, reg, mask, value, 2,
+       return __intel_wait_for_register(uncore, reg, mask, value, 2,
                                         timeout_ms, NULL);
 }
 

diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index 01278b2e257c6a697291628062a5bf9a068dd936..0a950c976bbb66df2e9946259b9fb9aed3e4d904 100644 (file)
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -78,7 +78,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
        mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
                LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    MIPI_GEN_FIFO_STAT(port), mask, mask,
                                    100))
                DRM_ERROR("DPI FIFOs are not empty\n");
@@ -148,7 +148,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 
        /* note: this is never true for reads */
        if (packet.payload_length) {
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            MIPI_GEN_FIFO_STAT(port),
                                            data_mask, 0,
                                            50))
@@ -162,7 +162,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
                I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
        }
 
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    MIPI_GEN_FIFO_STAT(port),
                                    ctrl_mask, 0,
                                    50)) {
@@ -174,7 +174,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
        /* ->rx_len is set only for reads */
        if (msg->rx_len) {
                data_mask = GEN_READ_DATA_AVAIL;
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            MIPI_INTR_STAT(port),
                                            data_mask, data_mask,
                                            50))
@@ -234,7 +234,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
        I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 
        mask = SPL_PKT_SENT_INTERRUPT;
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    MIPI_INTR_STAT(port), mask, mask,
                                    100))
                DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
@@ -353,16 +353,18 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 
        /* Wait for Pwr ACK */
        for_each_dsi_port(port, intel_dsi->ports) {
-               if (intel_wait_for_register(dev_priv,
-                               MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
-                               GLK_MIPIIO_PORT_POWERED, 20))
+               if (intel_wait_for_register(&dev_priv->uncore,
+                                           MIPI_CTRL(port),
+                                           GLK_MIPIIO_PORT_POWERED,
+                                           GLK_MIPIIO_PORT_POWERED,
+                                           20))
                        DRM_ERROR("MIPIO port is powergated\n");
        }
 
        /* Check for cold boot scenario */
        for_each_dsi_port(port, intel_dsi->ports) {
-               cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
-                                                       DEVICE_READY);
+               cold_boot |=
+                       !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY);
        }
 
        return cold_boot;
@@ -377,9 +379,11 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
 
        /* Wait for MIPI PHY status bit to set */
        for_each_dsi_port(port, intel_dsi->ports) {
-               if (intel_wait_for_register(dev_priv,
-                               MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
-                               GLK_PHY_STATUS_PORT_READY, 20))
+               if (intel_wait_for_register(&dev_priv->uncore,
+                                           MIPI_CTRL(port),
+                                           GLK_PHY_STATUS_PORT_READY,
+                                           GLK_PHY_STATUS_PORT_READY,
+                                           20))
                        DRM_ERROR("PHY is not ON\n");
        }
 
@@ -403,8 +407,11 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
                        I915_WRITE(MIPI_DEVICE_READY(port), val);
 
                        /* Wait for ULPS active */
-                       if (intel_wait_for_register(dev_priv,
-                               MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
+                       if (intel_wait_for_register(&dev_priv->uncore,
+                                                   MIPI_CTRL(port),
+                                                   GLK_ULPS_NOT_ACTIVE,
+                                                   0,
+                                                   20))
                                DRM_ERROR("ULPS not active\n");
 
                        /* Exit ULPS */
@@ -427,17 +434,21 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
 
        /* Wait for Stop state */
        for_each_dsi_port(port, intel_dsi->ports) {
-               if (intel_wait_for_register(dev_priv,
-                               MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
-                               GLK_DATA_LANE_STOP_STATE, 20))
+               if (intel_wait_for_register(&dev_priv->uncore,
+                                           MIPI_CTRL(port),
+                                           GLK_DATA_LANE_STOP_STATE,
+                                           GLK_DATA_LANE_STOP_STATE,
+                                           20))
                        DRM_ERROR("Date lane not in STOP state\n");
        }
 
        /* Wait for AFE LATCH */
        for_each_dsi_port(port, intel_dsi->ports) {
-               if (intel_wait_for_register(dev_priv,
-                               BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
-                               AFE_LATCHOUT, 20))
+               if (intel_wait_for_register(&dev_priv->uncore,
+                                           BXT_MIPI_PORT_CTRL(port),
+                                           AFE_LATCHOUT,
+                                           AFE_LATCHOUT,
+                                           20))
                        DRM_ERROR("D-PHY not entering LP-11 state\n");
        }
 }
@@ -537,7 +548,7 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 
        /* Wait for MIPI PHY status bit to unset */
        for_each_dsi_port(port, intel_dsi->ports) {
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            MIPI_CTRL(port),
                                            GLK_PHY_STATUS_PORT_READY, 0, 20))
                        DRM_ERROR("PHY is not turning OFF\n");
@@ -545,7 +556,7 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 
        /* Wait for Pwr ACK bit to unset */
        for_each_dsi_port(port, intel_dsi->ports) {
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            MIPI_CTRL(port),
                                            GLK_MIPIIO_PORT_POWERED, 0, 20))
                        DRM_ERROR("MIPI IO Port is not powergated\n");
@@ -566,7 +577,7 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 
        /* Wait for MIPI PHY status bit to unset */
        for_each_dsi_port(port, intel_dsi->ports) {
-               if (intel_wait_for_register(dev_priv,
+               if (intel_wait_for_register(&dev_priv->uncore,
                                            MIPI_CTRL(port),
                                            GLK_PHY_STATUS_PORT_READY, 0, 20))
                        DRM_ERROR("PHY is not turning OFF\n");
@@ -616,7 +627,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
                 * Port A only. MIPI Port C has no similar bit for checking.
                 */
                if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
-                   intel_wait_for_register(dev_priv,
+                   intel_wait_for_register(&dev_priv->uncore,
                                            port_ctrl, AFE_LATCHOUT, 0,
                                            30))
                        DRM_ERROR("DSI LP not going Low\n");

diff --git a/drivers/gpu/drm/i915/vlv_dsi_pll.c b/drivers/gpu/drm/i915/vlv_dsi_pll.c
index 954d5a8c4fa761841b8cb8bcdd579809dd0c9014..5e7b1fb2db5dbffac352420c482fbb2c46bd3c51 100644 (file)
--- a/drivers/gpu/drm/i915/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/vlv_dsi_pll.c
@@ -244,7 +244,7 @@ void bxt_dsi_pll_disable(struct intel_encoder *encoder)
         * PLL lock should deassert within 200us.
         * Wait up to 1ms before timing out.
         */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    BXT_DSI_PLL_ENABLE,
                                    BXT_DSI_PLL_LOCKED,
                                    0,
@@ -528,7 +528,7 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder,
        I915_WRITE(BXT_DSI_PLL_ENABLE, val);
 
        /* Timeout and fail if PLL not locked */
-       if (intel_wait_for_register(dev_priv,
+       if (intel_wait_for_register(&dev_priv->uncore,
                                    BXT_DSI_PLL_ENABLE,
                                    BXT_DSI_PLL_LOCKED,
                                    BXT_DSI_PLL_LOCKED,