char physicalRev;
logical_chip_type_t chip;
- physicalID = devId750; /* either 0x718 or 0x750 */
+ physicalID = devId750;//either 0x718 or 0x750
physicalRev = revId750;
if (physicalID == 0x718)
unsigned int ulReg;
#if 0
- /* move the code to map regiter function. */
+ //move the code to map regiter function.
if (getChipType() == SM718) {
/* turn on big endian bit*/
ulReg = PEEK32(0x74);
}
}
+ //printk("Finally: pll->n[%lu],m[%lu],od[%lu],pod[%lu]\n",pll->N,pll->M,pll->OD,pll->POD);
return ret;
}
}
/* Restore input frequency from Khz to hz unit */
+// pPLL->inputFreq *= 1000;
ulRequestClk *= 1000;
pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */
+ /* Output debug information */
+ //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency = %d\n", ulRequestClk));
+ //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d, N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD, pPLL->POD));
+
/* Return actual frequency that the PLL can set */
ret = calcPLL(pPLL);
return ret;