drm/amdgpu: move amdgpu_device_(vram|gtt)_location
authorChristian König <christian.koenig@amd.com>
Thu, 23 Aug 2018 13:20:43 +0000 (15:20 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 29 Aug 2018 17:35:18 +0000 (12:35 -0500)
Move that into amdgpu_gmc.c since we are really deadling with GMC
address space here.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index 340e40d03d54a66dbcc005b846655d54677e410f..09bdedfc91c78733e3c9887061b0beae70b33a6d 100644 (file)
@@ -1166,10 +1166,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev);
 
 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
                                  u64 num_vis_bytes);
-void amdgpu_device_vram_location(struct amdgpu_device *adev,
-                                struct amdgpu_gmc *mc, u64 base);
-void amdgpu_device_gart_location(struct amdgpu_device *adev,
-                                struct amdgpu_gmc *mc);
 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
                                             const u32 *registers,
index a20c13c6f6f197c6f6aff1bc14060d00f4c1ab2f..93476b8c2e725c7beaab76819dc55675665e2f32 100644 (file)
@@ -651,71 +651,6 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
                __clear_bit(wb, adev->wb.used);
 }
 
-/**
- * amdgpu_device_vram_location - try to find VRAM location
- *
- * @adev: amdgpu device structure holding all necessary informations
- * @mc: memory controller structure holding memory informations
- * @base: base address at which to put VRAM
- *
- * Function will try to place VRAM at base address provided
- * as parameter.
- */
-void amdgpu_device_vram_location(struct amdgpu_device *adev,
-                                struct amdgpu_gmc *mc, u64 base)
-{
-       uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
-
-       mc->vram_start = base;
-       mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
-       if (limit && limit < mc->real_vram_size)
-               mc->real_vram_size = limit;
-       dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
-                       mc->mc_vram_size >> 20, mc->vram_start,
-                       mc->vram_end, mc->real_vram_size >> 20);
-}
-
-/**
- * amdgpu_device_gart_location - try to find GART location
- *
- * @adev: amdgpu device structure holding all necessary informations
- * @mc: memory controller structure holding memory informations
- *
- * Function will place try to place GART before or after VRAM.
- *
- * If GART size is bigger than space left then we ajust GART size.
- * Thus function will never fails.
- */
-void amdgpu_device_gart_location(struct amdgpu_device *adev,
-                                struct amdgpu_gmc *mc)
-{
-       u64 size_af, size_bf;
-
-       mc->gart_size += adev->pm.smu_prv_buffer_size;
-
-       size_af = adev->gmc.mc_mask - mc->vram_end;
-       size_bf = mc->vram_start;
-       if (size_bf > size_af) {
-               if (mc->gart_size > size_bf) {
-                       dev_warn(adev->dev, "limiting GART\n");
-                       mc->gart_size = size_bf;
-               }
-               mc->gart_start = 0;
-       } else {
-               if (mc->gart_size > size_af) {
-                       dev_warn(adev->dev, "limiting GART\n");
-                       mc->gart_size = size_af;
-               }
-               /* VCE doesn't like it when BOs cross a 4GB segment, so align
-                * the GART base on a 4GB boundary as well.
-                */
-               mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
-       }
-       mc->gart_end = mc->gart_start + mc->gart_size - 1;
-       dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
-                       mc->gart_size >> 20, mc->gart_start, mc->gart_end);
-}
-
 /**
  * amdgpu_device_resize_fb_bar - try to resize FB BAR
  *
index a249931ef51210b9cbe5c4c2e2bbc4ded2155f2a..72dffa3fd194362cb2c23762a5171b413fc367b1 100644 (file)
@@ -78,3 +78,67 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
        }
        return pd_addr;
 }
+
+/**
+ * amdgpu_gmc_vram_location - try to find VRAM location
+ *
+ * @adev: amdgpu device structure holding all necessary informations
+ * @mc: memory controller structure holding memory informations
+ * @base: base address at which to put VRAM
+ *
+ * Function will try to place VRAM at base address provided
+ * as parameter.
+ */
+void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
+                             u64 base)
+{
+       uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
+
+       mc->vram_start = base;
+       mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
+       if (limit && limit < mc->real_vram_size)
+               mc->real_vram_size = limit;
+       dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
+                       mc->mc_vram_size >> 20, mc->vram_start,
+                       mc->vram_end, mc->real_vram_size >> 20);
+}
+
+/**
+ * amdgpu_gmc_gart_location - try to find GART location
+ *
+ * @adev: amdgpu device structure holding all necessary informations
+ * @mc: memory controller structure holding memory informations
+ *
+ * Function will place try to place GART before or after VRAM.
+ *
+ * If GART size is bigger than space left then we ajust GART size.
+ * Thus function will never fails.
+ */
+void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
+{
+       u64 size_af, size_bf;
+
+       mc->gart_size += adev->pm.smu_prv_buffer_size;
+
+       size_af = adev->gmc.mc_mask - mc->vram_end;
+       size_bf = mc->vram_start;
+       if (size_bf > size_af) {
+               if (mc->gart_size > size_bf) {
+                       dev_warn(adev->dev, "limiting GART\n");
+                       mc->gart_size = size_bf;
+               }
+               mc->gart_start = 0;
+       } else {
+               if (mc->gart_size > size_af) {
+                       dev_warn(adev->dev, "limiting GART\n");
+                       mc->gart_size = size_af;
+               }
+               /* VCE doesn't like it when BOs cross a 4GB segment, so align
+                * the GART base on a 4GB boundary as well.
+                */
+               mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
+       }
+       mc->gart_end = mc->gart_start + mc->gart_size - 1;
+       dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
+                       mc->gart_size >> 20, mc->gart_start, mc->gart_end);
+}
index 85030c04c443c61b1b675566e92eec6a879c6a42..588a62f7aebc5c3b8d2e5aa03a0617f074a5d8a8 100644 (file)
@@ -136,5 +136,9 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
                               uint64_t *addr, uint64_t *flags);
 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
+void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
+                             u64 base);
+void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
+                             struct amdgpu_gmc *mc);
 
 #endif
index 9c45ea318bd65e68774fda7f766348e605218b5f..4411463ca719a4e9b6f505110d385a41ec5261aa 100644 (file)
@@ -224,8 +224,8 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
        u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
        base <<= 24;
 
-       amdgpu_device_vram_location(adev, &adev->gmc, base);
-       amdgpu_device_gart_location(adev, mc);
+       amdgpu_gmc_vram_location(adev, &adev->gmc, base);
+       amdgpu_gmc_gart_location(adev, mc);
 }
 
 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
index d3400064e9db2423a967b2ea0fa3db606796ed83..ae776ce9a4153eb55bd5a68a90a4ef9d7439ddc5 100644 (file)
@@ -242,8 +242,8 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
        u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
        base <<= 24;
 
-       amdgpu_device_vram_location(adev, &adev->gmc, base);
-       amdgpu_device_gart_location(adev, mc);
+       amdgpu_gmc_vram_location(adev, &adev->gmc, base);
+       amdgpu_gmc_gart_location(adev, mc);
 }
 
 /**
index fb0d57655f78c09d2f1629699e362378b6c6fe99..53ae49b8bde85fc57daf31fcfb7eb1d857574300 100644 (file)
@@ -411,8 +411,8 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
                base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
        base <<= 24;
 
-       amdgpu_device_vram_location(adev, &adev->gmc, base);
-       amdgpu_device_gart_location(adev, mc);
+       amdgpu_gmc_vram_location(adev, &adev->gmc, base);
+       amdgpu_gmc_gart_location(adev, mc);
 }
 
 /**
index 9e976c2be9550558747ed1c9b4431efb33880510..04d50893a6f2b514f898694ad728baa963c75acd 100644 (file)
@@ -749,8 +749,8 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
        u64 base = 0;
        if (!amdgpu_sriov_vf(adev))
                base = mmhub_v1_0_get_fb_location(adev);
-       amdgpu_device_vram_location(adev, &adev->gmc, base);
-       amdgpu_device_gart_location(adev, mc);
+       amdgpu_gmc_vram_location(adev, &adev->gmc, base);
+       amdgpu_gmc_gart_location(adev, mc);
        /* base offset of vram pages */
        adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 }