drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl

Latency programming remains same as that of ICL and
setting latency otimization for PCS_DW1 lanes is same as
that of EHL, hence extending it to TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190730073648.5157-3-vandita.kulkarni@intel.com

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 7b8fdb16b651755d4f16124f43c5352728cae831..3185cb0bae41b7a0303b2aacb3281e09f944fa43 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -403,8 +403,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
                tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
                I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
 
-               /* For EHL set latency optimization for PCS_DW1 lanes */
-               if (IS_ELKHARTLAKE(dev_priv)) {
+               /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
+               if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
                        tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
                        tmp &= ~LATENCY_OPTIM_MASK;
                        tmp |= LATENCY_OPTIM_VAL(0);