/* NOTREACHED */
}
+/*
+ * Get the rate of ahb clock.
+ */
+static u32 get_ahb_clk(void)
+{
+ uint32_t freq, div, reg;
+
+ freq = get_periph_clk();
+
+ reg = __raw_readl(&mxc_ccm->cbcdr);
+ div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+ MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
+
+ return freq / div;
+}
+
/*
* Get the rate of ipg clock.
*/
static u32 get_ipg_clk(void)
{
- u32 ahb_podf, ipg_podf;
-
- ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
- ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
- MXC_CCM_CBCDR_IPG_PODF_OFFSET;
- ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
- MXC_CCM_CBCDR_AHB_PODF_OFFSET;
- return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
+ uint32_t freq, reg, div;
+
+ freq = get_ahb_clk();
+
+ reg = __raw_readl(&mxc_ccm->cbcdr);
+ div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+ MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+
+ return freq / div;
}
/*
case MXC_ARM_CLK:
return get_mcu_main_clk();
case MXC_AHB_CLK:
- break;
+ return get_ahb_clk();
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
printf("pll4: %dMHz\n", freq / 1000000);
#endif
+ printf("ahb clock : %dHz\n", mxc_get_clock(MXC_AHB_CLK));
printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));