Tegra: memctrl_v2: MC transaction overrides for newer chips

This patch programs MC transaction overrides settings using
mc_txn_override_cfgs array for all Tegra chips beyond Tegra186
rev. A01

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index b8c0e03ed24febe2baffff5af037283e7550c5c2..d3c3e873ae7e606e39c286309fa7d337c98ce5d4 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -375,10 +375,14 @@ void tegra_memctrl_setup(void)
        /*
         * Set the MC_TXN_OVERRIDE registers for write clients.
         */
-       if (!tegra_platform_is_silicon() ||
-           (tegra_platform_is_silicon() && tegra_get_chipid_minor() == 1)) {
+       if ((tegra_get_chipid() == (uint32_t)TEGRA_CHIPID_TEGRA18) &&
+           (!tegra_platform_is_silicon() ||
+           (tegra_platform_is_silicon() && tegra_get_chipid_minor() == 1))) {
 
-               /* GPU and NVENC settings for rev. A01 */
+               /*
+                * GPU and NVENC settings for Tegra186 simulation and
+                * Silicon rev. A01
+                */
                val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
                val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
                tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
@@ -396,7 +400,9 @@ void tegra_memctrl_setup(void)
 
        } else {
 
-               /* settings for rev. A02 */
+               /*
+                * Settings for Tegra186 silicon rev. A02 and onwards.
+                */
                for (i = 0; i < num_txn_override_cfgs; i++) {
                        val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
                        val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;