Refresh kernel patches for version 6.1.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
select GENERIC_IRQ_CHIP
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
-@@ -62,6 +62,7 @@ obj-$(CONFIG_XTENSA_MX) += irq-xtensa-
+@@ -63,6 +63,7 @@ obj-$(CONFIG_XTENSA_MX) += irq-xtensa-
obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
-@@ -31,13 +31,52 @@
+@@ -32,13 +32,52 @@
#define RELO_NORMAL_VEC BIT(18)
struct bmips_quirk {
const char *compatible;
void (*quirk_fn)(void);
-@@ -142,17 +181,161 @@ const char *get_system_type(void)
+@@ -154,17 +193,161 @@ const char *get_system_type(void)
return "Generic BMIPS kernel";
}
#include <asm/addrspace.h>
#include <asm/bmips.h>
#include <asm/bootinfo.h>
-@@ -34,13 +35,16 @@
+@@ -35,13 +36,16 @@
#define REG_BCM6318_SOB ((void __iomem *)CKSEG1ADDR(0x10000900))
#define BCM6318_FREQ_SHIFT 23
#define BCM6318_FREQ_MASK (0x3 << BCM6318_FREQ_SHIFT)
#define REG_BCM6358_DDR_PLLC ((void __iomem *)0xfffe12b8)
#define BCM6358_PLLC_M1_SHIFT 0
#define BCM6358_PLLC_M1_MASK (0xff << BCM6358_PLLC_M1_SHIFT)
-@@ -52,7 +56,9 @@
+@@ -53,7 +57,9 @@
#define REG_BCM6362_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001814))
#define BCM6362_FCVO_SHIFT 1
#define BCM6362_FCVO_MASK (0x1f << BCM6362_FCVO_SHIFT)
#define REG_BCM6368_DDR_PLLC ((void __iomem *)CKSEG1ADDR(0x100012a0))
#define BCM6368_PLLC_P1_SHIFT 0
#define BCM6368_PLLC_P1_MASK (0xf << BCM6368_PLLC_P1_SHIFT)
-@@ -67,6 +73,21 @@
+@@ -68,6 +74,21 @@
#define REG_BCM63268_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001814))
#define BCM63268_FCVO_SHIFT 21
#define BCM63268_FCVO_MASK (0xf << BCM63268_FCVO_SHIFT)
extern bool bmips_rac_flush_disable;
-@@ -77,6 +98,11 @@ struct bmips_cpufreq {
+@@ -78,6 +99,11 @@ struct bmips_cpufreq {
u32 (*cpu_freq)(void);
};
struct bmips_quirk {
const char *compatible;
void (*quirk_fn)(void);
-@@ -340,9 +366,90 @@ void __init plat_time_init(void)
+@@ -352,9 +378,90 @@ void __init plat_time_init(void)
mips_hpt_frequency = freq;
}
const struct bmips_quirk *q;
set_io_port_base(0);
-@@ -360,6 +467,18 @@ void __init plat_mem_setup(void)
+@@ -372,6 +479,18 @@ void __init plat_mem_setup(void)
__dt_setup_arch(dtb);
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
-@@ -274,25 +274,20 @@ config BMIPS_GENERIC
+@@ -272,19 +272,13 @@ config BMIPS_GENERIC
select SYNC_R4K
select COMMON_CLK
select BCM6345_L1_IRQ
select SWAP_IO_SPACE
select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
- select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
- select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
- select HARDIRQS_SW_RESEND
+@@ -294,6 +288,7 @@ config BMIPS_GENERIC
+ select HAVE_PCI
+ select PCI_DRIVERS_GENERIC
+ select FW_CFE
+ select MIPS_L1_CACHE_SHIFT_4
help
Build a generic DT-based kernel image that boots on select
BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
+--- a/drivers/irqchip/Kconfig 2023-05-30 19:59:04.671531242 +0200
++++ b/drivers/irqchip/Kconfig 2023-05-30 19:59:55.203880697 +0200
+@@ -121,7 +121,6 @@ config BCM6345_L1_IRQ
+ config BCM7038_L1_IRQ
+ tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
+ depends on ARCH_BRCMSTB || BMIPS_GENERIC
+- default ARCH_BRCMSTB || BMIPS_GENERIC
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
+@@ -129,14 +128,12 @@ config BCM7038_L1_IRQ
+ config BCM7120_L2_IRQ
+ tristate "Broadcom STB 7120-style L2 interrupt controller driver"
+ depends on ARCH_BRCMSTB || BMIPS_GENERIC
+- default ARCH_BRCMSTB || BMIPS_GENERIC
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+
+ config BRCMSTB_L2_IRQ
+ tristate "Broadcom STB generic L2 interrupt controller driver"
+ depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
+- default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+++ /dev/null
-From 5a37811de679bff03e9c5a746f75574910ede964 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
-Date: Wed, 22 Mar 2023 20:52:13 +0100
-Subject: [PATCH] Revert "mtd: rawnand: Macronix: Add support for block
- protection"
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This reverts commit 03a539c7a118427a6609a26461358c56ac8f3a06.
-
-Macronix block protection doesn't seem to be supported on Sercomm H-500s
-devices since it hangs the device.
-
-Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
----
- drivers/mtd/nand/raw/nand_macronix.c | 72 ----------------------------
- 1 file changed, 72 deletions(-)
-
---- a/drivers/mtd/nand/raw/nand_macronix.c
-+++ b/drivers/mtd/nand/raw/nand_macronix.c
-@@ -12,10 +12,6 @@
- #define MACRONIX_READ_RETRY_BIT BIT(0)
- #define MACRONIX_NUM_READ_RETRY_MODES 6
-
--#define ONFI_FEATURE_ADDR_MXIC_PROTECTION 0xA0
--#define MXIC_BLOCK_PROTECTION_ALL_LOCK 0x38
--#define MXIC_BLOCK_PROTECTION_ALL_UNLOCK 0x0
--
- #define ONFI_FEATURE_ADDR_MXIC_RANDOMIZER 0xB0
- #define MACRONIX_RANDOMIZER_BIT BIT(1)
- #define MACRONIX_RANDOMIZER_ENPGM BIT(0)
-@@ -179,73 +175,6 @@ static void macronix_nand_fix_broken_get
- ONFI_FEATURE_ADDR_TIMING_MODE, 1);
- }
-
--/*
-- * Macronix NAND supports Block Protection by Protectoin(PT) pin;
-- * active high at power-on which protects the entire chip even the #WP is
-- * disabled. Lock/unlock protection area can be partition according to
-- * protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on.
-- */
--static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len)
--{
-- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
-- int ret;
--
-- feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK;
-- nand_select_target(chip, 0);
-- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
-- feature);
-- nand_deselect_target(chip);
-- if (ret)
-- pr_err("%s all blocks failed\n", __func__);
--
-- return ret;
--}
--
--static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len)
--{
-- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
-- int ret;
--
-- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
-- nand_select_target(chip, 0);
-- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
-- feature);
-- nand_deselect_target(chip);
-- if (ret)
-- pr_err("%s all blocks failed\n", __func__);
--
-- return ret;
--}
--
--static void macronix_nand_block_protection_support(struct nand_chip *chip)
--{
-- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
-- int ret;
--
-- bitmap_set(chip->parameters.get_feature_list,
-- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
--
-- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
-- nand_select_target(chip, 0);
-- ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
-- feature);
-- nand_deselect_target(chip);
-- if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) {
-- if (ret)
-- pr_err("Block protection check failed\n");
--
-- bitmap_clear(chip->parameters.get_feature_list,
-- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
-- return;
-- }
--
-- bitmap_set(chip->parameters.set_feature_list,
-- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
--
-- chip->ops.lock_area = mxic_nand_lock;
-- chip->ops.unlock_area = mxic_nand_unlock;
--}
--
- static int nand_power_down_op(struct nand_chip *chip)
- {
- int ret;
-@@ -323,7 +252,6 @@ static int macronix_nand_init(struct nan
-
- macronix_nand_fix_broken_get_timings(chip);
- macronix_nand_onfi_init(chip);
-- macronix_nand_block_protection_support(chip);
- macronix_nand_deep_power_down_support(chip);
-
- return 0;
--- /dev/null
+From 5a37811de679bff03e9c5a746f75574910ede964 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Wed, 22 Mar 2023 20:52:13 +0100
+Subject: [PATCH] Revert "mtd: rawnand: Macronix: Add support for block
+ protection"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit 03a539c7a118427a6609a26461358c56ac8f3a06.
+
+Macronix block protection doesn't seem to be supported on Sercomm H-500s
+devices since it hangs the device.
+
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+---
+ drivers/mtd/nand/raw/nand_macronix.c | 72 ----------------------------
+ 1 file changed, 72 deletions(-)
+
+--- a/drivers/mtd/nand/raw/nand_macronix.c
++++ b/drivers/mtd/nand/raw/nand_macronix.c
+@@ -12,10 +12,6 @@
+ #define MACRONIX_READ_RETRY_BIT BIT(0)
+ #define MACRONIX_NUM_READ_RETRY_MODES 6
+
+-#define ONFI_FEATURE_ADDR_MXIC_PROTECTION 0xA0
+-#define MXIC_BLOCK_PROTECTION_ALL_LOCK 0x38
+-#define MXIC_BLOCK_PROTECTION_ALL_UNLOCK 0x0
+-
+ #define ONFI_FEATURE_ADDR_MXIC_RANDOMIZER 0xB0
+ #define MACRONIX_RANDOMIZER_BIT BIT(1)
+ #define MACRONIX_RANDOMIZER_ENPGM BIT(0)
+@@ -179,73 +175,6 @@ static void macronix_nand_fix_broken_get
+ ONFI_FEATURE_ADDR_TIMING_MODE, 1);
+ }
+
+-/*
+- * Macronix NAND supports Block Protection by Protectoin(PT) pin;
+- * active high at power-on which protects the entire chip even the #WP is
+- * disabled. Lock/unlock protection area can be partition according to
+- * protection bits, i.e. upper 1/2 locked, upper 1/4 locked and so on.
+- */
+-static int mxic_nand_lock(struct nand_chip *chip, loff_t ofs, uint64_t len)
+-{
+- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
+- int ret;
+-
+- feature[0] = MXIC_BLOCK_PROTECTION_ALL_LOCK;
+- nand_select_target(chip, 0);
+- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
+- feature);
+- nand_deselect_target(chip);
+- if (ret)
+- pr_err("%s all blocks failed\n", __func__);
+-
+- return ret;
+-}
+-
+-static int mxic_nand_unlock(struct nand_chip *chip, loff_t ofs, uint64_t len)
+-{
+- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
+- int ret;
+-
+- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
+- nand_select_target(chip, 0);
+- ret = nand_set_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
+- feature);
+- nand_deselect_target(chip);
+- if (ret)
+- pr_err("%s all blocks failed\n", __func__);
+-
+- return ret;
+-}
+-
+-static void macronix_nand_block_protection_support(struct nand_chip *chip)
+-{
+- u8 feature[ONFI_SUBFEATURE_PARAM_LEN];
+- int ret;
+-
+- bitmap_set(chip->parameters.get_feature_list,
+- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
+-
+- feature[0] = MXIC_BLOCK_PROTECTION_ALL_UNLOCK;
+- nand_select_target(chip, 0);
+- ret = nand_get_features(chip, ONFI_FEATURE_ADDR_MXIC_PROTECTION,
+- feature);
+- nand_deselect_target(chip);
+- if (ret || feature[0] != MXIC_BLOCK_PROTECTION_ALL_LOCK) {
+- if (ret)
+- pr_err("Block protection check failed\n");
+-
+- bitmap_clear(chip->parameters.get_feature_list,
+- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
+- return;
+- }
+-
+- bitmap_set(chip->parameters.set_feature_list,
+- ONFI_FEATURE_ADDR_MXIC_PROTECTION, 1);
+-
+- chip->ops.lock_area = mxic_nand_lock;
+- chip->ops.unlock_area = mxic_nand_unlock;
+-}
+-
+ static int nand_power_down_op(struct nand_chip *chip)
+ {
+ int ret;
+@@ -323,7 +252,6 @@ static int macronix_nand_init(struct nan
+
+ macronix_nand_fix_broken_get_timings(chip);
+ macronix_nand_onfi_init(chip);
+- macronix_nand_block_protection_support(chip);
+ macronix_nand_deep_power_down_support(chip);
+
+ return 0;
---
arch/mips/Kconfig | 1 +
arch/mips/pci/Makefile | 1 +
- 2 files changed, 2 insertions(+)
+ 2 files changed, 1 insertions(+), 1 deletions(-)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
-@@ -274,6 +274,7 @@ config BMIPS_GENERIC
- select SYNC_R4K
- select COMMON_CLK
- select BCM6345_L1_IRQ
-+ select HAVE_PCI
- select IRQ_MIPS_CPU
- select DMA_NONCOHERENT
- select SYS_SUPPORTS_32BIT_KERNEL
+@@ -286,7 +286,6 @@ config BMIPS_GENERIC
+ select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
+ select HARDIRQS_SW_RESEND
+ select HAVE_PCI
+- select PCI_DRIVERS_GENERIC
+ select FW_CFE
+ select MIPS_L1_CACHE_SHIFT_4
+ help
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
-@@ -28,6 +28,7 @@ obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xt
+@@ -26,6 +26,7 @@ obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xt
# These are still pretty much in the old state, watch, go blind.
#
obj-$(CONFIG_ATH79) += fixup-ath79.o
+ depends on OF
+
config PCI_MVEBU
- bool "Marvell EBU PCIe controller"
+ tristate "Marvell EBU PCIe controller"
depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
-@@ -288,6 +288,15 @@ config LEDS_COBALT_RAQ
+@@ -281,6 +281,15 @@ config LEDS_COBALT_RAQ
help
This option enables support for the Cobalt Raq series LEDs.
depends on LEDS_CLASS
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
-@@ -77,6 +77,7 @@ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
+@@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o
obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
projects / openwrt / staging / jow.git / commitdiff