status = "okay";
};
-&spi_0 {
+&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
};
};
-&spi_0 {
+&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
status = "okay";
};
-&spi_0 { /* BLSP1 QUP1 */
+&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
status = "okay";
};
-&spi_0 {
+&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
};
};
-&spi_0 { /* BLSP1 QUP1 */
+&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
};
};
-&spi_0 { /* BLSP1 QUP1 */
+&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
};
};
-&spi_0 {
+&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
status = "okay";
};
-&spi_0 {
+&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
status = "okay";
};
- spi_0: spi@78b5000 {
+ spi0: spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
};
};
- i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
+ i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
-&spi_0 {
+&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
status = "okay";
};
-&spi_0 {
+&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
vlan_tag = <0 0x20>;
};
-&i2c_0 {
+&blsp1_i2c3{
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
};
-&i2c_1 {
+&blsp1_i2c4{
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";
+++ /dev/null
-From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Thu, 17 Mar 2016 15:01:09 -0500
-Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq
- support
-
-This adds some operating points for cpu frequeny scaling
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
- 1 file changed, 26 insertions(+), 8 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -40,14 +40,7 @@
- reg = <0x0>;
- clocks = <&gcc GCC_APPS_CLK_SRC>;
- clock-frequency = <0>;
-- operating-points = <
-- /* kHz uV (fixed) */
-- 48000 1100000
-- 200000 1100000
-- 500000 1100000
-- 666000 1100000
-- >;
-- clock-latency = <256000>;
-+ operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@1 {
-@@ -59,6 +52,7 @@
- reg = <0x1>;
- clocks = <&gcc GCC_APPS_CLK_SRC>;
- clock-frequency = <0>;
-+ operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@2 {
-@@ -70,6 +64,7 @@
- reg = <0x2>;
- clocks = <&gcc GCC_APPS_CLK_SRC>;
- clock-frequency = <0>;
-+ operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@3 {
-@@ -81,6 +76,29 @@
- reg = <0x3>;
- clocks = <&gcc GCC_APPS_CLK_SRC>;
- clock-frequency = <0>;
-+ operating-points-v2 = <&cpu0_opp_table>;
-+ };
-+ };
-+
-+ cpu0_opp_table: opp_table0 {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-48000000 {
-+ opp-hz = /bits/ 64 <48000000>;
-+ clock-latency-ns = <256000>;
-+ };
-+ opp-200000000 {
-+ opp-hz = /bits/ 64 <200000000>;
-+ clock-latency-ns = <256000>;
-+ };
-+ opp-500000000 {
-+ opp-hz = /bits/ 64 <500000000>;
-+ clock-latency-ns = <256000>;
-+ };
-+ opp-716000000 {
-+ opp-hz = /bits/ 64 <716000000>;
-+ clock-latency-ns = <256000>;
- };
- };
-
-Check for SCM availability before attempting to use SPM
+From 341844c7e06afccd64261719fa388339a589b0a4 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 22 Jul 2018 12:53:04 +0200
+Subject: [PATCH] soc: qcom: spm: add SCM probe dependency
+
+Check for SCM availability before attempting to use SPM. SPM probe will
+fail otherwise.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/soc/qcom/spm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
+index f9d7a85b2822..53807e839664 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
-@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(stru
+@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
cpumask_t mask;
bool use_scm_power_down = false;
for (i = 0; ; i++) {
state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
if (!state_node)
+--
+2.11.0
+
--- /dev/null
+From 364123029d8d547336323fbd3d659ecd0bba913f Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Mon, 23 Jul 2018 08:41:02 +0200
+Subject: [PATCH 5/8] qcom: ipq4019: use v2 of the kpss bringup mechanism
+
+v1 was the incorrect choice here and sometimes the board
+would not come up properly.
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++--------
+ 1 file changed, 17 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+index 93647db5d90b..06434fd02d40 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -52,7 +52,8 @@
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+- enable-method = "qcom,kpss-acc-v1";
++ enable-method = "qcom,kpss-acc-v2";
++ next-level-cache = <&L2>;
+ qcom,acc = <&acc0>;
+ qcom,saw = <&saw0>;
+ reg = <0x0>;
+@@ -71,7 +72,8 @@
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+- enable-method = "qcom,kpss-acc-v1";
++ enable-method = "qcom,kpss-acc-v2";
++ next-level-cache = <&L2>;
+ qcom,acc = <&acc1>;
+ qcom,saw = <&saw1>;
+ reg = <0x1>;
+@@ -82,7 +84,8 @@
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+- enable-method = "qcom,kpss-acc-v1";
++ enable-method = "qcom,kpss-acc-v2";
++ next-level-cache = <&L2>;
+ qcom,acc = <&acc2>;
+ qcom,saw = <&saw2>;
+ reg = <0x2>;
+@@ -93,13 +96,19 @@
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+- enable-method = "qcom,kpss-acc-v1";
++ enable-method = "qcom,kpss-acc-v2";
++ next-level-cache = <&L2>;
+ qcom,acc = <&acc3>;
+ qcom,saw = <&saw3>;
+ reg = <0x3>;
+ clocks = <&gcc GCC_APPS_CLK_SRC>;
+ clock-frequency = <0>;
+ };
++
++ L2: l2-cache {
++ compatible = "cache";
++ cache-level = <2>;
++ };
+ };
+
+ pmu {
+@@ -268,22 +277,22 @@
+ };
+
+ acc0: clock-controller@b088000 {
+- compatible = "qcom,kpss-acc-v1";
++ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+ };
+
+ acc1: clock-controller@b098000 {
+- compatible = "qcom,kpss-acc-v1";
++ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+ };
+
+ acc2: clock-controller@b0a8000 {
+- compatible = "qcom,kpss-acc-v1";
++ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+ };
+
+ acc3: clock-controller@b0b8000 {
+- compatible = "qcom,kpss-acc-v1";
++ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+ };
+
+--
+2.11.0
+
--- /dev/null
+From 544af73985cd14b450bb8e8a6c22b89a555ac729 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Mon, 23 Jul 2018 09:10:35 +0200
+Subject: [PATCH 6/8] qcom: ipq4019: add cpu operating points for cpufreq
+ support
+
+This adds some operating points for cpu frequeny scaling
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
+ 1 file changed, 26 insertions(+), 8 deletions(-)
+
+Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi
+===================================================================
+--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -41,14 +41,7 @@
+ reg = <0x0>;
+ clocks = <&gcc GCC_APPS_CLK_SRC>;
+ clock-frequency = <0>;
+- operating-points = <
+- /* kHz uV (fixed) */
+- 48000 1100000
+- 200000 1100000
+- 500000 1100000
+- 666000 1100000
+- >;
+- clock-latency = <256000>;
++ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@1 {
+@@ -61,6 +54,7 @@
+ reg = <0x1>;
+ clocks = <&gcc GCC_APPS_CLK_SRC>;
+ clock-frequency = <0>;
++ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@2 {
+@@ -73,6 +67,7 @@
+ reg = <0x2>;
+ clocks = <&gcc GCC_APPS_CLK_SRC>;
+ clock-frequency = <0>;
++ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@3 {
+@@ -85,6 +80,29 @@
+ reg = <0x3>;
+ clocks = <&gcc GCC_APPS_CLK_SRC>;
+ clock-frequency = <0>;
++ operating-points-v2 = <&cpu0_opp_table>;
++ };
++ };
++
++ cpu0_opp_table: opp_table0 {
++ compatible = "operating-points-v2";
++ opp-shared;
++
++ opp-48000000 {
++ opp-hz = /bits/ 64 <48000000>;
++ clock-latency-ns = <256000>;
++ };
++ opp-200000000 {
++ opp-hz = /bits/ 64 <200000000>;
++ clock-latency-ns = <256000>;
++ };
++ opp-500000000 {
++ opp-hz = /bits/ 64 <500000000>;
++ clock-latency-ns = <256000>;
++ };
++ opp-716000000 {
++ opp-hz = /bits/ 64 <716000000>;
++ clock-latency-ns = <256000>;
+ };
+
+ L2: l2-cache {
--- /dev/null
+From d60e006ec0e425877aacc61c7ece3da0434a8fce Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Mon, 23 Jul 2018 16:34:54 +0200
+Subject: [PATCH 7/8] qcom: ipq4019: fix cpu0's qcom,saw2 reg value
+
+while compiling an ipq4019 target, dtc will complain:
+regulator@b089000 unit address format error, expected "2089000"
+
+The saw0 regulator reg value seems to be
+copied and pasted from qcom-ipq8064.dtsi.
+
+This patch fixes the reg value to match that of the
+unit address which in turn silences the warning.
+(There is no driver for qcom,saw2 right now.
+So this went unnoticed)
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+index 98b9850ed2a0..3289b3a6c10e 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -316,7 +316,7 @@
+
+ saw0: regulator@b089000 {
+ compatible = "qcom,saw2";
+- reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
++ reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
+ regulator;
+ };
+
+--
+2.11.0
+
--- /dev/null
+From 89b43d59ec8c9cda588555eb1f2754dd19ef5144 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sun, 22 Jul 2018 12:07:57 +0200
+Subject: [PATCH 8/8] ARM: qcom: Add IPQ4019 SoC support
+
+Add support for the Qualcomm Atheros IPQ4019 SoC.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/Makefile | 1 +
+ arch/arm/mach-qcom/Kconfig | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+Index: linux-4.14.54/arch/arm/Makefile
+===================================================================
+--- linux-4.14.54.orig/arch/arm/Makefile
++++ linux-4.14.54/arch/arm/Makefile
+@@ -150,6 +150,7 @@ endif
+ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
+ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
++textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
+
+ # Machine directory name. This list is sorted alphanumerically
+ # by CONFIG_* macro name.
+Index: linux-4.14.54/arch/arm/mach-qcom/Kconfig
+===================================================================
+--- linux-4.14.54.orig/arch/arm/mach-qcom/Kconfig
++++ linux-4.14.54/arch/arm/mach-qcom/Kconfig
+@@ -27,4 +27,9 @@ config ARCH_MDM9615
+ bool "Enable support for MDM9615"
+ select CLKSRC_QCOM
+
++config ARCH_IPQ40XX
++ bool "Enable support for IPQ40XX"
++ select CLKSRC_QCOM
++ select HAVE_ARM_ARCH_TIMER
++
+ endif
--- /dev/null
+From 5f01733dc755dfadfa51b7b3c6c160e632fc6002 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 24 Jul 2018 15:09:36 +0200
+Subject: [PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document
+
+This patch adds the binding documentation for the HS/SS USB PHY found
+inside Qualcom Dakota SoCs.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ .../bindings/phy/phy-qcom-ipq4019-usb.txt | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
+
+diff --git a/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
+new file mode 100644
+index 000000000000..362877fcafed
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
+@@ -0,0 +1,21 @@
++Qualcom Dakota HS/SS USB PHY
++
++Required properties:
++ - compatible: "qcom,usb-ss-ipq4019-phy",
++ "qcom,usb-hs-ipq4019-phy"
++ - reg: offset and length of the registers
++ - #phy-cells: should be 0
++ - resets: the reset controllers as listed below
++ - reset-names: the names of the reset controllers
++ "por_rst" - the POR reset line for SS and HS phys
++ "srif_rst" - the SRIF reset line for HS phys
++Example:
++
++hsphy@a8000 {
++ compatible = "qcom,usb-hs-ipq4019-phy";
++ phy-cells = <0>;
++ reg = <0xa8000 0x40>;
++ resets = <&gcc USB2_HSPHY_POR_ARES>,
++ <&gcc USB2_HSPHY_S_ARES>;
++ reset-names = "por_rst", "srif_rst";
++};
+--
+2.11.0
+
--- /dev/null
+From 633f0e08498aebfdb932bd71319b4cb136709499 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 24 Jul 2018 14:45:49 +0200
+Subject: [PATCH 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019
+
+Add a driver to setup the USB phy on Qualcom Dakota SoCs.
+The driver sets up HS and SS phys. In case of HS some magic values need to
+be written to magic offsets. These were taken from the SDK driver.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/phy/qualcomm/Kconfig | 7 ++
+ drivers/phy/qualcomm/Makefile | 1 +
+ drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 188 ++++++++++++++++++++++++++++
+ 3 files changed, 196 insertions(+)
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
+
+Index: linux-4.14.54/drivers/phy/qualcomm/Kconfig
+===================================================================
+--- linux-4.14.54.orig/drivers/phy/qualcomm/Kconfig
++++ linux-4.14.54/drivers/phy/qualcomm/Kconfig
+@@ -8,6 +8,13 @@ config PHY_QCOM_APQ8064_SATA
+ depends on OF
+ select GENERIC_PHY
+
++config PHY_QCOM_IPQ4019_USB
++ tristate "Qualcomm IPQ4019 USB PHY module"
++ depends on OF && ARCH_QCOM
++ select GENERIC_PHY
++ help
++ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
++
+ config PHY_QCOM_IPQ806X_SATA
+ tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
+ depends on ARCH_QCOM
+Index: linux-4.14.54/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
+===================================================================
+--- /dev/null
++++ linux-4.14.54/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
+@@ -0,0 +1,188 @@
++/*
++ * Copyright (C) 2018 John Crispin <john@phrozen.org>
++ *
++ * Based on code from
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of_platform.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++
++/*
++ * Magic registers copied from the SDK driver code
++ */
++#define PHY_CTRL0_ADDR 0x000
++#define PHY_CTRL1_ADDR 0x004
++#define PHY_CTRL2_ADDR 0x008
++#define PHY_CTRL3_ADDR 0x00C
++#define PHY_CTRL4_ADDR 0x010
++#define PHY_MISC_ADDR 0x024
++#define PHY_IPG_ADDR 0x030
++
++#define PHY_CTRL0_VAL 0xA4600015
++#define PHY_CTRL1_VAL 0x09500000
++#define PHY_CTRL2_VAL 0x00058180
++#define PHY_CTRL3_VAL 0x6DB6DCD6
++#define PHY_CTRL4_VAL 0x836DB6DB
++#define PHY_MISC_VAL 0x3803FB0C
++#define PHY_IPG_VAL 0x47323232
++
++struct ipq4019_usb_phy {
++ struct device *dev;
++ struct phy *phy;
++ void __iomem *base;
++ struct reset_control *por_rst;
++ struct reset_control *srif_rst;
++};
++
++static int ipq4019_ss_phy_power_off(struct phy *_phy)
++{
++ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
++
++ reset_control_assert(phy->por_rst);
++ msleep(10);
++
++ return 0;
++}
++
++static int ipq4019_ss_phy_power_on(struct phy *_phy)
++{
++ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
++
++ ipq4019_ss_phy_power_off(_phy);
++
++ reset_control_deassert(phy->por_rst);
++
++ return 0;
++}
++
++static struct phy_ops ipq4019_usb_ss_phy_ops = {
++ .power_on = ipq4019_ss_phy_power_on,
++ .power_off = ipq4019_ss_phy_power_off,
++};
++
++static int ipq4019_hs_phy_power_off(struct phy *_phy)
++{
++ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
++
++ reset_control_assert(phy->por_rst);
++ msleep(10);
++
++ reset_control_assert(phy->srif_rst);
++ msleep(10);
++
++ return 0;
++}
++
++static int ipq4019_hs_phy_power_on(struct phy *_phy)
++{
++ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
++
++ ipq4019_hs_phy_power_off(_phy);
++
++ reset_control_deassert(phy->srif_rst);
++ msleep(10);
++
++ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
++ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
++ writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
++ writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
++ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
++ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
++ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
++ msleep(10);
++
++ reset_control_deassert(phy->por_rst);
++
++ return 0;
++}
++
++static struct phy_ops ipq4019_usb_hs_phy_ops = {
++ .power_on = ipq4019_hs_phy_power_on,
++ .power_off = ipq4019_hs_phy_power_off,
++};
++
++static const struct of_device_id ipq4019_usb_phy_of_match[] = {
++ { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops},
++ { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops},
++ { },
++};
++MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match);
++
++static int ipq4019_usb_phy_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct resource *res;
++ struct phy_provider *phy_provider;
++ struct ipq4019_usb_phy *phy;
++ const struct of_device_id *match;
++
++ match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev);
++ if (!match)
++ return -ENODEV;
++
++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
++ if (!phy)
++ return -ENOMEM;
++
++ phy->dev = &pdev->dev;
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ phy->base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(phy->base)) {
++ dev_err(dev, "failed to remap register memory\n");
++ return PTR_ERR(phy->base);
++ }
++
++ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
++ if (IS_ERR(phy->por_rst)) {
++ if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER)
++ dev_err(dev, "POR reset is missing\n");
++ return PTR_ERR(phy->por_rst);
++ }
++
++ phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst");
++ if (IS_ERR(phy->srif_rst))
++ return PTR_ERR(phy->srif_rst);
++
++ phy->phy = devm_phy_create(dev, NULL, match->data);
++ if (IS_ERR(phy->phy)) {
++ dev_err(dev, "failed to create PHY\n");
++ return PTR_ERR(phy->phy);
++ }
++ phy_set_drvdata(phy->phy, phy);
++
++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static struct platform_driver ipq4019_usb_phy_driver = {
++ .probe = ipq4019_usb_phy_probe,
++ .driver = {
++ .of_match_table = ipq4019_usb_phy_of_match,
++ .name = "ipq4019-usb-phy",
++ }
++};
++module_platform_driver(ipq4019_usb_phy_driver);
++
++MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver");
++MODULE_AUTHOR("John Crispin <john@phrozen.org>");
++MODULE_LICENSE("GPL v2");
+Index: linux-4.14.54/drivers/phy/qualcomm/Makefile
+===================================================================
+--- linux-4.14.54.orig/drivers/phy/qualcomm/Makefile
++++ linux-4.14.54/drivers/phy/qualcomm/Makefile
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
++obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
+ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
+ obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
+ obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
--- /dev/null
+From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 24 Jul 2018 14:47:55 +0200
+Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes
+
+This patch makes USB work on the Dakota EVB.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++
+ 2 files changed, 94 insertions(+)
+
+diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+index 418f9a022336..2ee5f05d5a43 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -109,5 +109,25 @@
+ wifi@a800000 {
+ status = "ok";
+ };
++
++ usb3_ss_phy: ssphy@9a000 {
++ status = "ok";
++ };
++
++ usb3_hs_phy: hsphy@a6000 {
++ status = "ok";
++ };
++
++ usb3: usb3@8af8800 {
++ status = "ok";
++ };
++
++ usb2_hs_phy: hsphy@a8000 {
++ status = "ok";
++ };
++
++ usb2: usb2@60f8800 {
++ status = "ok";
++ };
+ };
+ };
+diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+index e5e52adbd5a3..e6b12129f0e4 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -553,5 +553,79 @@
+ "legacy";
+ status = "disabled";
+ };
++
++ usb3_ss_phy: ssphy@9a000 {
++ compatible = "qcom,usb-ss-ipq4019-phy";
++ #phy-cells = <0>;
++ reg = <0x9a000 0x800>;
++ reg-names = "phy_base";
++ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
++ reset-names = "por_rst";
++ status = "disabled";
++ };
++
++ usb3_hs_phy: hsphy@a6000 {
++ compatible = "qcom,usb-hs-ipq4019-phy";
++ #phy-cells = <0>;
++ reg = <0xa6000 0x40>;
++ reg-names = "phy_base";
++ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
++ reset-names = "por_rst", "srif_rst";
++ status = "disabled";
++ };
++
++ usb3@8af8800 {
++ compatible = "qcom,dwc3";
++ reg = <0x8af8800 0x100>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ clocks = <&gcc GCC_USB3_MASTER_CLK>,
++ <&gcc GCC_USB3_SLEEP_CLK>,
++ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
++ clock-names = "master", "sleep", "mock_utmi";
++ ranges;
++ status = "disabled";
++
++ dwc3@8a00000 {
++ compatible = "snps,dwc3";
++ reg = <0x8a00000 0xf8000>;
++ interrupts = <0 132 0>;
++ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
++ phy-names = "usb2-phy", "usb3-phy";
++ dr_mode = "host";
++ };
++ };
++
++ usb2_hs_phy: hsphy@a8000 {
++ compatible = "qcom,usb-hs-ipq4019-phy";
++ #phy-cells = <0>;
++ reg = <0xa8000 0x40>;
++ reg-names = "phy_base";
++ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
++ reset-names = "por_rst", "srif_rst";
++ status = "disabled";
++ };
++
++ usb2@60f8800 {
++ compatible = "qcom,dwc3";
++ reg = <0x60f8800 0x100>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ clocks = <&gcc GCC_USB2_MASTER_CLK>,
++ <&gcc GCC_USB2_SLEEP_CLK>,
++ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
++ clock-names = "master", "sleep", "mock_utmi";
++ ranges;
++ status = "disabled";
++
++ dwc3@6000000 {
++ compatible = "snps,dwc3";
++ reg = <0x6000000 0xf8000>;
++ interrupts = <0 136 0>;
++ phys = <&usb2_hs_phy>;
++ phy-names = "usb2-phy";
++ dr_mode = "host";
++ };
++ };
+ };
+ };
+--
+2.11.0
+
--- /dev/null
+From 187519403273f0599c848d20eca9acce8b1807a5 Mon Sep 17 00:00:00 2001
+From: Sricharan R <sricharan@codeaurora.org>
+Date: Fri, 25 May 2018 11:41:12 +0530
+Subject: [PATCH] ARM: dts: ipq4019: Add a few peripheral nodes
+
+Now with the driver updates for some peripherals being there,
+add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
+peripheral support.
+
+Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
+ 2 files changed, 146 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+index ef8d8c88ed7b..418f9a022336 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -69,7 +69,7 @@
+ status = "ok";
+ };
+
+- spi_0: spi@78b5000 {
++ spi@78b5000 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+index 2efc8a2d41a7..737097e9fb4f 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -40,8 +40,10 @@
+ };
+
+ aliases {
+- spi0 = &spi_0;
+- i2c0 = &i2c_0;
++ spi0 = &blsp1_spi1;
++ spi1 = &blsp1_spi2;
++ i2c0 = &blsp1_i2c3;
++ i2c1 = &blsp1_i2c4;
+ };
+
+ cpus {
+@@ -120,6 +122,12 @@
+ };
+ };
+
++ firmware {
++ scm {
++ compatible = "qcom,scm-ipq4019";
++ };
++ };
++
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 2 0xf08>,
+@@ -165,13 +173,13 @@
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+- interrupts = <0 208 0>;
++ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ blsp_dma: dma@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x23000>;
+- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
++ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+@@ -179,7 +187,7 @@
+ status = "disabled";
+ };
+
+- spi_0: spi@78b5000 {
++ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x78b5000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+@@ -188,10 +196,26 @@
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
++ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
++ compatible = "qcom,spi-qup-v2.2.1";
++ reg = <0x78b6000 0x600>;
++ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
++ <&gcc GCC_BLSP1_AHB_CLK>;
++ clock-names = "core", "iface";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+- i2c_0: i2c@78b7000 {
++ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x78b7000 0x600>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+@@ -200,14 +224,29 @@
+ clock-names = "iface", "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
++ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
++ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
++ compatible = "qcom,i2c-qup-v2.2.1";
++ reg = <0x78b8000 0x600>;
++ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
++ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
++ clock-names = "iface", "core";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
+
+ cryptobam: dma@8e04000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x08e04000 0x20000>;
+- interrupts = <GIC_SPI 207 0>;
++ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+@@ -275,7 +314,7 @@
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78af000 0x200>;
+- interrupts = <0 107 0>;
++ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+@@ -287,7 +326,7 @@
+ serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b0000 0x200>;
+- interrupts = <0 108 0>;
++ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+@@ -309,6 +348,101 @@
+ reg = <0x4ab000 0x4>;
+ };
+
++ pcie0: pci@40000000 {
++ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
++ reg = <0x40000000 0xf1d
++ 0x40000f20 0xa8
++ 0x80000 0x2000
++ 0x40100000 0x1000>;
++ reg-names = "dbi", "elbi", "parf", "config";
++ device_type = "pci";
++ linux,pci-domain = <0>;
++ bus-range = <0x00 0xff>;
++ num-lanes = <1>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
++ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
++
++ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
++ interrupt-names = "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
++ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
++ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
++ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
++ clocks = <&gcc GCC_PCIE_AHB_CLK>,
++ <&gcc GCC_PCIE_AXI_M_CLK>,
++ <&gcc GCC_PCIE_AXI_S_CLK>;
++ clock-names = "aux",
++ "master_bus",
++ "slave_bus";
++
++ resets = <&gcc PCIE_AXI_M_ARES>,
++ <&gcc PCIE_AXI_S_ARES>,
++ <&gcc PCIE_PIPE_ARES>,
++ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
++ <&gcc PCIE_AXI_S_XPU_ARES>,
++ <&gcc PCIE_PARF_XPU_ARES>,
++ <&gcc PCIE_PHY_ARES>,
++ <&gcc PCIE_AXI_M_STICKY_ARES>,
++ <&gcc PCIE_PIPE_STICKY_ARES>,
++ <&gcc PCIE_PWR_ARES>,
++ <&gcc PCIE_AHB_ARES>,
++ <&gcc PCIE_PHY_AHB_ARES>;
++ reset-names = "axi_m",
++ "axi_s",
++ "pipe",
++ "axi_m_vmid",
++ "axi_s_xpu",
++ "parf",
++ "phy",
++ "axi_m_sticky",
++ "pipe_sticky",
++ "pwr",
++ "ahb",
++ "phy_ahb";
++
++ status = "disabled";
++ };
++
++ qpic_bam: dma@7984000 {
++ compatible = "qcom,bam-v1.7.0";
++ reg = <0x7984000 0x1a000>;
++ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GCC_QPIC_CLK>;
++ clock-names = "bam_clk";
++ #dma-cells = <1>;
++ qcom,ee = <0>;
++ status = "disabled";
++ };
++
++ nand: qpic-nand@79b0000 {
++ compatible = "qcom,ipq4019-nand";
++ reg = <0x79b0000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&gcc GCC_QPIC_CLK>,
++ <&gcc GCC_QPIC_AHB_CLK>;
++ clock-names = "core", "aon";
++
++ dmas = <&qpic_bam 0>,
++ <&qpic_bam 1>,
++ <&qpic_bam 2>;
++ dma-names = "tx", "rx", "cmd";
++ status = "disabled";
++
++ nand@0 {
++ reg = <0>;
++
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++ nand-bus-width = <8>;
++ };
++ };
++
+ wifi0: wifi@a000000 {
+ compatible = "qcom,ipq4019-wifi";
+ reg = <0xa000000 0x200000>;
+@@ -342,7 +476,7 @@
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
+- <GIC_SPI 168 IRQ_TYPE_NONE>;
++ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
+@@ -384,7 +518,7 @@
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
+- <GIC_SPI 169 IRQ_TYPE_NONE>;
++ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
+--
+2.11.0
+
--- /dev/null
+From 561a7e69d2811f236266ff9222a1e683ebf8b9e0 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Thu, 1 Mar 2018 20:50:29 +0100
+Subject: [PATCH] ARM: dts: ipq4019: fix PCI range
+
+The PCI range is invalid and PCI attached devices doen't work.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -359,7 +359,7 @@
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
+- 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
++ 0x82000000 0 0x40300000 0x40300000 0 0x400000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
+ interrupt-names = "msi";
--- /dev/null
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Thu, 12 Apr 2018 21:01:38 +0200
+Subject: [PATCH] pinctrl: msm: fix gpio-hog related boot issues
+
+Sven Eckelmann reported an issue with the current IPQ4019 pinctrl.
+Setting up any gpio-hog in the device-tree for his device would
+"kill the bootup completely":
+
+| [ 0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
+| [ 0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe
+| [ 1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517
+| [ 1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register
+| [ 1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip
+| [ 1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
+| [ 1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri
+
+This was also verified on a RT-AC58U (IPQ4018) which would
+no longer boot, if a gpio-hog was specified. (Tried forcing
+the USB LED PIN (GPIO0) to high.).
+
+The problem is that Pinctrl+GPIO registration is currently
+peformed in the following order in pinctrl-msm.c:
+ 1. pinctrl_register()
+ 2. gpiochip_add()
+ 3. gpiochip_add_pin_range()
+
+The actual error code -517 == -EPROBE_DEFER is coming from
+pinctrl_get_device_gpio_range(), which is called through:
+ gpiochip_add
+ of_gpiochip_add
+ of_gpiochip_scan_gpios
+ gpiod_hog
+ gpiochip_request_own_desc
+ __gpiod_request
+ chip->request
+ gpiochip_generic_request
+ pinctrl_gpio_request
+ pinctrl_get_device_gpio_range
+
+pinctrl_get_device_gpio_range() is unable to find any valid
+pin ranges, since nothing has been added to the pinctrldev_list yet.
+so the range can't be found, and the operation fails with -EPROBE_DEFER.
+
+This patch fixes the issue by adding the "gpio-ranges" property to
+the pinctrl device node of all upstream Qcom SoC. The pin ranges are
+then added by the gpio core.
+
+In order to remain compatible with older, existing DTs (and ACPI)
+a check for the "gpio-ranges" property has been added to
+msm_gpio_init(). This prevents the driver of adding the same entry
+to the pinctrldev_list twice.
+
+Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+
+Origin: other, https://patchwork.kernel.org/patch/10339127/
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
+ drivers/pinctrl/qcom/pinctrl-msm.c | 23 ++++++++++++++++++-----
+ 14 files changed, 32 insertions(+), 6 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -166,6 +166,7 @@
+ compatible = "qcom,ipq4019-pinctrl";
+ reg = <0x01000000 0x300000>;
+ gpio-controller;
++ gpio-ranges = <&tlmm 0 0 100>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+--- a/drivers/pinctrl/qcom/pinctrl-msm.c
++++ b/drivers/pinctrl/qcom/pinctrl-msm.c
+@@ -831,11 +831,24 @@ static int msm_gpio_init(struct msm_pinc
+ return ret;
+ }
+
+- ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
+- if (ret) {
+- dev_err(pctrl->dev, "Failed to add pin range\n");
+- gpiochip_remove(&pctrl->chip);
+- return ret;
++ /*
++ * For DeviceTree-supported systems, the gpio core checks the
++ * pinctrl's device node for the "gpio-ranges" property.
++ * If it is present, it takes care of adding the pin ranges
++ * for the driver. In this case the driver can skip ahead.
++ *
++ * In order to remain compatible with older, existing DeviceTree
++ * files which don't set the "gpio-ranges" property or systems that
++ * utilize ACPI the driver has to call gpiochip_add_pin_range().
++ */
++ if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
++ ret = gpiochip_add_pin_range(&pctrl->chip,
++ dev_name(pctrl->dev), 0, 0, chip->ngpio);
++ if (ret) {
++ dev_err(pctrl->dev, "Failed to add pin range\n");
++ gpiochip_remove(&pctrl->chip);
++ return ret;
++ }
+ }
+
+ ret = gpiochip_irqchip_add(chip,
--- /dev/null
+From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@googlemail.com>
+Date: Sun, 11 Mar 2018 14:41:31 +0100
+Subject: [PATCH 2/2] clk: fix apss cpu overclocking
+
+There's an interaction issue between the clk changes:"
+clk: qcom: ipq4019: Add the apss cpu pll divider clock node
+clk: qcom: ipq4019: remove fixed clocks and add pll clocks
+" and the cpufreq-dt.
+
+cpufreq-dt is now spamming the kernel-log with the following:
+
+[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
+for freq 761142857 (-34)
+
+This only happens on certain devices like the Compex WPJ428
+and AVM FritzBox!4040. However, other devices like the Asus
+RT-AC58U and Meraki MR33 work just fine.
+
+The issue stem from the fact that all higher CPU-Clocks
+are achieved by switching the clock-parent to the P_DDRPLLAPSS
+(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
+as part of the DDR calibration.
+
+For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
+at round 533 MHz (ddrpllsdcc = 190285714 Hz).
+
+whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
+clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
+
+This patch attempts to fix the issue by modifying
+clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
+to use a new qcom_find_freq_close() function, which returns the closest
+matching frequency, instead of the next higher. This way, the SoC in
+the FB4040 (with its max clock speed of 710.4 MHz) will no longer
+try to overclock to 761 MHz.
+
+Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
+ 1 file changed, 31 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
+index 46cb256b4aa2..4ec43f7d2e52 100644
+--- a/drivers/clk/qcom/gcc-ipq4019.c
++++ b/drivers/clk/qcom/gcc-ipq4019.c
+@@ -1253,6 +1253,29 @@ static const struct clk_fepll_vco gcc_fepll_vco = {
+ .reg = 0x2f020,
+ };
+
++
++const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
++ unsigned long rate)
++{
++ const struct freq_tbl *last = NULL;
++
++ for ( ; f->freq; f++) {
++ if (rate == f->freq)
++ return f;
++
++ if (f->freq > rate) {
++ if (!last ||
++ (f->freq - rate) < (rate - last->freq))
++ return f;
++ else
++ return last;
++ }
++ last = f;
++ }
++
++ return last;
++}
++
+ /*
+ * Round rate function for APSS CPU PLL Clock divider.
+ * It looks up the frequency table and returns the next higher frequency
+@@ -1265,7 +1288,7 @@ static long clk_cpu_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ struct clk_hw *p_hw;
+ const struct freq_tbl *f;
+
+- f = qcom_find_freq(pll->freq_tbl, rate);
++ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return -EINVAL;
+
+@@ -1288,7 +1311,7 @@ static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ u32 mask;
+ int ret;
+
+- f = qcom_find_freq(pll->freq_tbl, rate);
++ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return -EINVAL;
+
+@@ -1315,6 +1338,7 @@ static unsigned long
+ clk_cpu_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+ {
++ const struct freq_tbl *f;
+ struct clk_fepll *pll = to_clk_fepll(hw);
+ u32 cdiv, pre_div;
+ u64 rate;
+@@ -1335,7 +1359,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *hw,
+ rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
+ do_div(rate, pre_div);
+
+- return rate;
++ f = qcom_find_freq_close(pll->freq_tbl, rate);
++ if (!f)
++ return rate;
++
++ return f->freq;
+ };
+
+ static const struct clk_ops clk_regmap_cpu_div_ops = {
+--
+2.11.0
+
--- /dev/null
+From fc566294610fa49e9d8c31c4ecc9c82f49b11f59 Mon Sep 17 00:00:00 2001
+From: Sven Eckelmann <sven.eckelmann@openmesh.com>
+Date: Wed, 18 Apr 2018 09:10:44 +0200
+Subject: [PATCH] ARM: dts: ipq4019: Add TZ and SMEM reserved regions
+
+The QSEE (trustzone) is started on IPQ4019 before Linux is started.
+According to QCA, it is placed in in the the memory region
+0x87e80000-0x88000000 and must not be accessed directly. There is an
+additional memory region 0x87e00000-0x87E80000 smem which which can be used
+for communication with the TZ. The driver for the latter is not yet ready
+but it is still not allowed to use this memory region like any other
+memory region.
+
+Not reserving this memory region either leads to kernel crashes, kernel
+hangs (often during the boot) or bus errors for userspace programs. The
+latter happens when a program is using a memory region which is mapped to
+these physical memory regions.
+
+ [ 571.758058] Unhandled fault: imprecise external abort (0xc06) at 0x01715ff8
+ [ 571.758099] pgd = cebec000
+ [ 571.763826] [01715ff8] *pgd=8e7fa835, *pte=87e7f75f, *ppte=87e7fc7f
+ Bus error
+
+Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
+
+Forwarded: https://patchwork.kernel.org/patch/10347459/
+---
+Cc: Sricharan Ramabadhran <srichara@qti.qualcomm.com>
+Cc: Senthilkumar N L <snlakshm@qti.qualcomm.com>
+
+There are additional memory regions which have to be initialized first by
+Linux. So they are currently not used. We were told by QCA that the
+features QSDK uses them for are:
+
+* crash dump feature
+ - a couple of regions used when 'qca,scm_restart_reason' dt node has the
+ value 'dload_status' not set to 1
+ + apps_bl <0x87000000 0x400000>
+ + sbl <0x87400000 0x100000>
+ + cnss_debug <0x87400000 0x100000>
+ + cpu_context_dump <0x87b00000 0x080000>
+ - required driver not available in Linux
+ - safe to remove
+* QSEE app execution
+ - region tz_apps <0x87b80000 0x280000>
+ - required driver not available in Linux
+ - safe to remove
+* communication with TZ/QSEE
+ - region smem <0x87b80000 0x280000>
+ - driver changes not yet upstreamed
+ - must not be removed because any access can crash kernel/program
+* trustzone (QSEE) private memory
+ - region tz <0x87e80000 0x180000>
+ - must not be removed because any access can crash kernel/program
+
+The problem with the missing regions was reported in 2016 [1]. So maybe
+this change qualifies for a stable@vger.kernel.org submission.
+
+[1] https://www.spinics.net/lists/linux-arm-msm/msg21536.html
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -23,6 +23,22 @@
+ compatible = "qcom,ipq4019";
+ interrupt-parent = <&intc>;
+
++ reserved-memory {
++ #address-cells = <0x1>;
++ #size-cells = <0x1>;
++ ranges;
++
++ smem_region: smem@87e00000 {
++ reg = <0x87e00000 0x080000>;
++ no-map;
++ };
++
++ tz@87e80000 {
++ reg = <0x87e80000 0x180000>;
++ no-map;
++ };
++ };
++
+ aliases {
+ spi0 = &spi_0;
+ spi1 = &spi_1;
--- /dev/null
+From 07b6d0cdbbda8c917480eceaec668f09e4cf24a5 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Mon, 14 Nov 2016 23:49:22 +0100
+Subject: [PATCH] mtd: nand: add Winbond manufacturer and chip
+
+This patch adds the W25N01GV NAND to the table of
+known devices. Without this patch the device gets detected:
+
+nand: device found, Manufacturer ID: 0xef, Chip ID: 0xaa
+nand: Unknown NAND 256MiB 1,8V 8-bit
+nand: 256 MiB, SLC, erase size: 64 KiB, page size: 1024, OOB size : 16
+
+Whereas the u-boot identifies it as:
+spi_nand: spi_nand_flash_probe SF NAND ID 00:ef:aa:21
+SF: Detected W25N01GV with page size 2 KiB, total 128 MiB
+
+Due to the page size discrepancy, it's impossible to attach
+ubi volumes on the device.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ drivers/mtd/nand/nand_ids.c | 4 ++++
+ include/linux/mtd/nand.h | 1 +
+ 2 files changed, 5 insertions(+)
+
+--- a/drivers/mtd/nand/nand_ids.c
++++ b/drivers/mtd/nand/nand_ids.c
+@@ -54,6 +54,10 @@ struct nand_flash_dev nand_flash_ids[] =
+ { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
+ SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+ NAND_ECC_INFO(40, SZ_1K), 4 },
++ {"W25N01GV 1G 3.3V 8-bit",
++ { .id = {0xef, 0xaa} },
++ SZ_2K, SZ_128, SZ_128K, NAND_NO_SUBPAGE_WRITE,
++ 2, 64, NAND_ECC_INFO(1, SZ_512) },
+
+ LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
+ LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
+++ /dev/null
-From patchwork Mon Jan 29 05:11:16 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [02/15] ARM: dts: ipq4019: Add a few peripheral nodes
-From: Sricharan R <sricharan@codeaurora.org>
-X-Patchwork-Id: 10189263
-Message-Id: <1517202689-14212-3-git-send-email-sricharan@codeaurora.org>
-To: robh+dt@kernel.org, robh@kernel.org, mark.rutland@arm.com,
- linux@armlinux.org.uk, andy.gross@linaro.org, david.brown@linaro.org,
- catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org,
- bjorn.andersson@linaro.org, devicetree@vger.kernel.org,
- linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
- linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org
-Cc: sricharan@codeaurora.org
-Date: Mon, 29 Jan 2018 10:41:16 +0530
-
-Now with the driver updates for some peripherals being there,
-add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
-peripheral support.
-
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 134 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -25,7 +25,9 @@
-
- aliases {
- spi0 = &spi_0;
-+ spi1 = &spi_1;
- i2c0 = &i2c_0;
-+ i2c1 = &i2c_1;
- };
-
- cpus {
-@@ -190,6 +192,22 @@
- clock-names = "core", "iface";
- #address-cells = <1>;
- #size-cells = <0>;
-+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ spi_1: spi@78b6000 { /* BLSP1 QUP2 */
-+ compatible = "qcom,spi-qup-v2.2.1";
-+ reg = <0x78b6000 0x600>;
-+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
-+ dma-names = "rx", "tx";
- status = "disabled";
- };
-
-@@ -202,9 +220,24 @@
- clock-names = "iface", "core";
- #address-cells = <1>;
- #size-cells = <0>;
-+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
-+ dma-names = "rx", "tx";
- status = "disabled";
- };
-
-+ i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
-+ compatible = "qcom,i2c-qup-v2.2.1";
-+ reg = <0x78b8000 0x600>;
-+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
-+ clock-names = "iface", "core";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-
- cryptobam: dma@8e04000 {
- compatible = "qcom,bam-v1.7.0";
-@@ -311,6 +344,101 @@
- reg = <0x4ab000 0x4>;
- };
-
-+ pcie0: pci@40000000 {
-+ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
-+ reg = <0x40000000 0xf1d
-+ 0x40000f20 0xa8
-+ 0x80000 0x2000
-+ 0x40100000 0x1000>;
-+ reg-names = "dbi", "elbi", "parf", "config";
-+ device_type = "pci";
-+ linux,pci-domain = <0>;
-+ bus-range = <0x00 0xff>;
-+ num-lanes = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
-+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
-+
-+ interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
-+ interrupt-names = "msi";
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0x7>;
-+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
-+ <&gcc GCC_PCIE_AXI_M_CLK>,
-+ <&gcc GCC_PCIE_AXI_S_CLK>;
-+ clock-names = "aux",
-+ "master_bus",
-+ "slave_bus";
-+
-+ resets = <&gcc PCIE_AXI_M_ARES>,
-+ <&gcc PCIE_AXI_S_ARES>,
-+ <&gcc PCIE_PIPE_ARES>,
-+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
-+ <&gcc PCIE_AXI_S_XPU_ARES>,
-+ <&gcc PCIE_PARF_XPU_ARES>,
-+ <&gcc PCIE_PHY_ARES>,
-+ <&gcc PCIE_AXI_M_STICKY_ARES>,
-+ <&gcc PCIE_PIPE_STICKY_ARES>,
-+ <&gcc PCIE_PWR_ARES>,
-+ <&gcc PCIE_AHB_ARES>,
-+ <&gcc PCIE_PHY_AHB_ARES>;
-+ reset-names = "axi_m",
-+ "axi_s",
-+ "pipe",
-+ "axi_m_vmid",
-+ "axi_s_xpu",
-+ "parf",
-+ "phy",
-+ "axi_m_sticky",
-+ "pipe_sticky",
-+ "pwr",
-+ "ahb",
-+ "phy_ahb";
-+
-+ status = "disabled";
-+ };
-+
-+ qpic_bam: dma@7984000 {
-+ compatible = "qcom,bam-v1.7.0";
-+ reg = <0x7984000 0x1a000>;
-+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_QPIC_CLK>;
-+ clock-names = "bam_clk";
-+ #dma-cells = <1>;
-+ qcom,ee = <0>;
-+ status = "disabled";
-+ };
-+
-+ nand: qpic-nand@79b0000 {
-+ compatible = "qcom,ipq4019-nand";
-+ reg = <0x79b0000 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ clocks = <&gcc GCC_QPIC_CLK>,
-+ <&gcc GCC_QPIC_AHB_CLK>;
-+ clock-names = "core", "aon";
-+
-+ dmas = <&qpic_bam 0>,
-+ <&qpic_bam 1>,
-+ <&qpic_bam 2>;
-+ dma-names = "tx", "rx", "cmd";
-+ status = "disabled";
-+
-+ nand@0 {
-+ reg = <0>;
-+
-+ nand-ecc-strength = <4>;
-+ nand-ecc-step-size = <512>;
-+ nand-bus-width = <8>;
-+ };
-+ };
-+
- wifi0: wifi@a000000 {
- compatible = "qcom,ipq4019-wifi";
- reg = <0xa000000 0x200000>;
+++ /dev/null
-From 561a7e69d2811f236266ff9222a1e683ebf8b9e0 Mon Sep 17 00:00:00 2001
-From: Mathias Kresin <dev@kresin.me>
-Date: Thu, 1 Mar 2018 20:50:29 +0100
-Subject: [PATCH] ARM: dts: ipq4019: fix PCI range
-
-The PCI range is invalid and PCI attached devices doen't work.
-
-Signed-off-by: Mathias Kresin <dev@kresin.me>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -359,7 +359,7 @@
- #size-cells = <2>;
-
- ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
-- 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
-+ 0x82000000 0 0x40300000 0x40300000 0 0x400000>;
-
- interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
- interrupt-names = "msi";
+++ /dev/null
-From 07b6d0cdbbda8c917480eceaec668f09e4cf24a5 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Mon, 14 Nov 2016 23:49:22 +0100
-Subject: [PATCH] mtd: nand: add Winbond manufacturer and chip
-
-This patch adds the W25N01GV NAND to the table of
-known devices. Without this patch the device gets detected:
-
-nand: device found, Manufacturer ID: 0xef, Chip ID: 0xaa
-nand: Unknown NAND 256MiB 1,8V 8-bit
-nand: 256 MiB, SLC, erase size: 64 KiB, page size: 1024, OOB size : 16
-
-Whereas the u-boot identifies it as:
-spi_nand: spi_nand_flash_probe SF NAND ID 00:ef:aa:21
-SF: Detected W25N01GV with page size 2 KiB, total 128 MiB
-
-Due to the page size discrepancy, it's impossible to attach
-ubi volumes on the device.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- drivers/mtd/nand/nand_ids.c | 4 ++++
- include/linux/mtd/nand.h | 1 +
- 2 files changed, 5 insertions(+)
-
---- a/drivers/mtd/nand/nand_ids.c
-+++ b/drivers/mtd/nand/nand_ids.c
-@@ -54,6 +54,10 @@ struct nand_flash_dev nand_flash_ids[] =
- { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
- SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
- NAND_ECC_INFO(40, SZ_1K), 4 },
-+ {"W25N01GV 1G 3.3V 8-bit",
-+ { .id = {0xef, 0xaa} },
-+ SZ_2K, SZ_128, SZ_128K, NAND_NO_SUBPAGE_WRITE,
-+ 2, 64, NAND_ECC_INFO(1, SZ_512) },
-
- LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
- LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
+++ /dev/null
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Thu, 12 Apr 2018 21:01:38 +0200
-Subject: [PATCH] pinctrl: msm: fix gpio-hog related boot issues
-
-Sven Eckelmann reported an issue with the current IPQ4019 pinctrl.
-Setting up any gpio-hog in the device-tree for his device would
-"kill the bootup completely":
-
-| [ 0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
-| [ 0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe
-| [ 1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517
-| [ 1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register
-| [ 1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip
-| [ 1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
-| [ 1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri
-
-This was also verified on a RT-AC58U (IPQ4018) which would
-no longer boot, if a gpio-hog was specified. (Tried forcing
-the USB LED PIN (GPIO0) to high.).
-
-The problem is that Pinctrl+GPIO registration is currently
-peformed in the following order in pinctrl-msm.c:
- 1. pinctrl_register()
- 2. gpiochip_add()
- 3. gpiochip_add_pin_range()
-
-The actual error code -517 == -EPROBE_DEFER is coming from
-pinctrl_get_device_gpio_range(), which is called through:
- gpiochip_add
- of_gpiochip_add
- of_gpiochip_scan_gpios
- gpiod_hog
- gpiochip_request_own_desc
- __gpiod_request
- chip->request
- gpiochip_generic_request
- pinctrl_gpio_request
- pinctrl_get_device_gpio_range
-
-pinctrl_get_device_gpio_range() is unable to find any valid
-pin ranges, since nothing has been added to the pinctrldev_list yet.
-so the range can't be found, and the operation fails with -EPROBE_DEFER.
-
-This patch fixes the issue by adding the "gpio-ranges" property to
-the pinctrl device node of all upstream Qcom SoC. The pin ranges are
-then added by the gpio core.
-
-In order to remain compatible with older, existing DTs (and ACPI)
-a check for the "gpio-ranges" property has been added to
-msm_gpio_init(). This prevents the driver of adding the same entry
-to the pinctrldev_list twice.
-
-Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-
-Origin: other, https://patchwork.kernel.org/patch/10339127/
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
- drivers/pinctrl/qcom/pinctrl-msm.c | 23 ++++++++++++++++++-----
- 14 files changed, 32 insertions(+), 6 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -166,6 +166,7 @@
- compatible = "qcom,ipq4019-pinctrl";
- reg = <0x01000000 0x300000>;
- gpio-controller;
-+ gpio-ranges = <&tlmm 0 0 100>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
---- a/drivers/pinctrl/qcom/pinctrl-msm.c
-+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
-@@ -831,11 +831,24 @@ static int msm_gpio_init(struct msm_pinc
- return ret;
- }
-
-- ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
-- if (ret) {
-- dev_err(pctrl->dev, "Failed to add pin range\n");
-- gpiochip_remove(&pctrl->chip);
-- return ret;
-+ /*
-+ * For DeviceTree-supported systems, the gpio core checks the
-+ * pinctrl's device node for the "gpio-ranges" property.
-+ * If it is present, it takes care of adding the pin ranges
-+ * for the driver. In this case the driver can skip ahead.
-+ *
-+ * In order to remain compatible with older, existing DeviceTree
-+ * files which don't set the "gpio-ranges" property or systems that
-+ * utilize ACPI the driver has to call gpiochip_add_pin_range().
-+ */
-+ if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
-+ ret = gpiochip_add_pin_range(&pctrl->chip,
-+ dev_name(pctrl->dev), 0, 0, chip->ngpio);
-+ if (ret) {
-+ dev_err(pctrl->dev, "Failed to add pin range\n");
-+ gpiochip_remove(&pctrl->chip);
-+ return ret;
-+ }
- }
-
- ret = gpiochip_irqchip_add(chip,
+++ /dev/null
-From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Fri, 8 Apr 2016 15:26:10 -0500
-Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
-
-v1 was the incorrect choice here and sometimes the board
-would not come up properly.
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
-Changes:
- - moved L2-Cache to be a subnode of cpu0
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
- 1 file changed, 24 insertions(+), 8 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -36,19 +36,27 @@
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
-- enable-method = "qcom,kpss-acc-v1";
-+ enable-method = "qcom,kpss-acc-v2";
-+ next-level-cache = <&L2>;
- qcom,acc = <&acc0>;
- qcom,saw = <&saw0>;
- reg = <0x0>;
- clocks = <&gcc GCC_APPS_CLK_SRC>;
- clock-frequency = <0>;
- operating-points-v2 = <&cpu0_opp_table>;
-+
-+ L2: l2-cache {
-+ compatible = "qcom,arch-cache";
-+ cache-level = <2>;
-+ qcom,saw = <&saw_l2>;
-+ };
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
-- enable-method = "qcom,kpss-acc-v1";
-+ enable-method = "qcom,kpss-acc-v2";
-+ next-level-cache = <&L2>;
- qcom,acc = <&acc1>;
- qcom,saw = <&saw1>;
- reg = <0x1>;
-@@ -60,7 +68,8 @@
- cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
-- enable-method = "qcom,kpss-acc-v1";
-+ enable-method = "qcom,kpss-acc-v2";
-+ next-level-cache = <&L2>;
- qcom,acc = <&acc2>;
- qcom,saw = <&saw2>;
- reg = <0x2>;
-@@ -72,7 +81,8 @@
- cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
-- enable-method = "qcom,kpss-acc-v1";
-+ enable-method = "qcom,kpss-acc-v2";
-+ next-level-cache = <&L2>;
- qcom,acc = <&acc3>;
- qcom,saw = <&saw3>;
- reg = <0x3>;
-@@ -265,22 +275,22 @@
- };
-
- acc0: clock-controller@b088000 {
-- compatible = "qcom,kpss-acc-v1";
-+ compatible = "qcom,kpss-acc-v2";
- reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
- };
-
- acc1: clock-controller@b098000 {
-- compatible = "qcom,kpss-acc-v1";
-+ compatible = "qcom,kpss-acc-v2";
- reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
- };
-
- acc2: clock-controller@b0a8000 {
-- compatible = "qcom,kpss-acc-v1";
-+ compatible = "qcom,kpss-acc-v2";
- reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
- };
-
- acc3: clock-controller@b0b8000 {
-- compatible = "qcom,kpss-acc-v1";
-+ compatible = "qcom,kpss-acc-v2";
- reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
- };
-
-@@ -308,6 +318,12 @@
- regulator;
- };
-
-+ saw_l2: regulator@b012000 {
-+ compatible = "qcom,saw2";
-+ reg = <0xb012000 0x1000>;
-+ regulator;
-+ };
-+
- serial@78af000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x78af000 0x200>;
+++ /dev/null
-From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Thu, 17 Mar 2016 16:22:28 -0500
-Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
-
-This adds the SoC nodes to the ipq4019 device tree and
-enable it for the DK01.1 board.
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
-Changes:
- - replaced space with tab
- - added sleep and mock_utmi clocks
- - added registers for usb2 and usb3 parent node
- - changed compatible to qca,ipa4019-dwc3
- - updated usb2 and usb3 names
- (included the reg - in case they become necessary later)
----
- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 71 +++++++++++++++++++++++++++
- 2 files changed, 91 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -101,5 +101,25 @@
- wifi@a800000 {
- status = "ok";
- };
-+
-+ usb3_ss_phy: ssphy@9a000 {
-+ status = "ok";
-+ };
-+
-+ usb3_hs_phy: hsphy@a6000 {
-+ status = "ok";
-+ };
-+
-+ usb3: usb3@8af8800 {
-+ status = "ok";
-+ };
-+
-+ usb2_hs_phy: hsphy@a8000 {
-+ status = "ok";
-+ };
-+
-+ usb2: usb2@60f8800 {
-+ status = "ok";
-+ };
- };
- };
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -539,5 +539,79 @@
- "legacy";
- status = "disabled";
- };
-+
-+ usb3_ss_phy: ssphy@9a000 {
-+ compatible = "qcom,usb-ss-ipq4019-phy";
-+ #phy-cells = <0>;
-+ reg = <0x9a000 0x800>;
-+ reg-names = "phy_base";
-+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
-+ reset-names = "por_rst";
-+ status = "disabled";
-+ };
-+
-+ usb3_hs_phy: hsphy@a6000 {
-+ compatible = "qcom,usb-hs-ipq4019-phy";
-+ #phy-cells = <0>;
-+ reg = <0xa6000 0x40>;
-+ reg-names = "phy_base";
-+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
-+ reset-names = "por_rst", "srif_rst";
-+ status = "disabled";
-+ };
-+
-+ usb3@8af8800 {
-+ compatible = "qcom,dwc3";
-+ reg = <0x8af8800 0x100>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
-+ <&gcc GCC_USB3_SLEEP_CLK>,
-+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
-+ clock-names = "master", "sleep", "mock_utmi";
-+ ranges;
-+ status = "disabled";
-+
-+ dwc3@8a00000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x8a00000 0xf8000>;
-+ interrupts = <0 132 0>;
-+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ dr_mode = "host";
-+ };
-+ };
-+
-+ usb2_hs_phy: hsphy@a8000 {
-+ compatible = "qcom,usb-hs-ipq4019-phy";
-+ #phy-cells = <0>;
-+ reg = <0xa8000 0x40>;
-+ reg-names = "phy_base";
-+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
-+ reset-names = "por_rst", "srif_rst";
-+ status = "disabled";
-+ };
-+
-+ usb2@60f8800 {
-+ compatible = "qcom,dwc3";
-+ reg = <0x60f8800 0x100>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
-+ <&gcc GCC_USB2_SLEEP_CLK>,
-+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
-+ clock-names = "master", "sleep", "mock_utmi";
-+ ranges;
-+ status = "disabled";
-+
-+ dwc3@6000000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x6000000 0xf8000>;
-+ interrupts = <0 136 0>;
-+ phys = <&usb2_hs_phy>;
-+ phy-names = "usb2-phy";
-+ dr_mode = "host";
-+ };
-+ };
- };
- };
---- a/drivers/phy/qualcomm/Kconfig
-+++ b/drivers/phy/qualcomm/Kconfig
-@@ -8,6 +8,13 @@ config PHY_QCOM_APQ8064_SATA
- depends on OF
- select GENERIC_PHY
-
-+config PHY_QCOM_IPQ4019_USB
-+ tristate "Qualcomm IPQ4019 USB PHY module"
-+ depends on OF && ARCH_QCOM
-+ select GENERIC_PHY
-+ help
-+ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
-+
- config PHY_QCOM_IPQ806X_SATA
- tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
- depends on ARCH_QCOM
---- a/drivers/phy/qualcomm/Makefile
-+++ b/drivers/phy/qualcomm/Makefile
-@@ -1,5 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
- obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
-+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
- obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
- obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
- obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
-@@ -0,0 +1,188 @@
-+/*
-+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
-+ *
-+ * Based on code from
-+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/of_platform.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+
-+/*
-+ * Magic registers copied from the SDK driver code
-+ */
-+#define PHY_CTRL0_ADDR 0x000
-+#define PHY_CTRL1_ADDR 0x004
-+#define PHY_CTRL2_ADDR 0x008
-+#define PHY_CTRL3_ADDR 0x00C
-+#define PHY_CTRL4_ADDR 0x010
-+#define PHY_MISC_ADDR 0x024
-+#define PHY_IPG_ADDR 0x030
-+
-+#define PHY_CTRL0_VAL 0xA4600015
-+#define PHY_CTRL1_VAL 0x09500000
-+#define PHY_CTRL2_VAL 0x00058180
-+#define PHY_CTRL3_VAL 0x6DB6DCD6
-+#define PHY_CTRL4_VAL 0x836DB6DB
-+#define PHY_MISC_VAL 0x3803FB0C
-+#define PHY_IPG_VAL 0x47323232
-+
-+struct ipq4019_usb_phy {
-+ struct device *dev;
-+ struct phy *phy;
-+ void __iomem *base;
-+ struct reset_control *por_rst;
-+ struct reset_control *srif_rst;
-+};
-+
-+static int ipq4019_ss_phy_power_off(struct phy *_phy)
-+{
-+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
-+
-+ reset_control_assert(phy->por_rst);
-+ msleep(10);
-+
-+ return 0;
-+}
-+
-+static int ipq4019_ss_phy_power_on(struct phy *_phy)
-+{
-+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
-+
-+ ipq4019_ss_phy_power_off(_phy);
-+
-+ reset_control_deassert(phy->por_rst);
-+
-+ return 0;
-+}
-+
-+static struct phy_ops ipq4019_usb_ss_phy_ops = {
-+ .power_on = ipq4019_ss_phy_power_on,
-+ .power_off = ipq4019_ss_phy_power_off,
-+};
-+
-+static int ipq4019_hs_phy_power_off(struct phy *_phy)
-+{
-+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
-+
-+ reset_control_assert(phy->por_rst);
-+ msleep(10);
-+
-+ reset_control_assert(phy->srif_rst);
-+ msleep(10);
-+
-+ return 0;
-+}
-+
-+static int ipq4019_hs_phy_power_on(struct phy *_phy)
-+{
-+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
-+
-+ ipq4019_hs_phy_power_off(_phy);
-+
-+ reset_control_deassert(phy->srif_rst);
-+ msleep(10);
-+
-+ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
-+ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
-+ writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
-+ writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
-+ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
-+ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
-+ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
-+ msleep(10);
-+
-+ reset_control_deassert(phy->por_rst);
-+
-+ return 0;
-+}
-+
-+static struct phy_ops ipq4019_usb_hs_phy_ops = {
-+ .power_on = ipq4019_hs_phy_power_on,
-+ .power_off = ipq4019_hs_phy_power_off,
-+};
-+
-+static const struct of_device_id ipq4019_usb_phy_of_match[] = {
-+ { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops},
-+ { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops},
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match);
-+
-+static int ipq4019_usb_phy_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct resource *res;
-+ struct phy_provider *phy_provider;
-+ struct ipq4019_usb_phy *phy;
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev);
-+ if (!match)
-+ return -ENODEV;
-+
-+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
-+ if (!phy)
-+ return -ENOMEM;
-+
-+ phy->dev = &pdev->dev;
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ phy->base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(phy->base)) {
-+ dev_err(dev, "failed to remap register memory\n");
-+ return PTR_ERR(phy->base);
-+ }
-+
-+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
-+ if (IS_ERR(phy->por_rst)) {
-+ if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER)
-+ dev_err(dev, "POR reset is missing\n");
-+ return PTR_ERR(phy->por_rst);
-+ }
-+
-+ phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst");
-+ if (IS_ERR(phy->srif_rst))
-+ return PTR_ERR(phy->srif_rst);
-+
-+ phy->phy = devm_phy_create(dev, NULL, match->data);
-+ if (IS_ERR(phy->phy)) {
-+ dev_err(dev, "failed to create PHY\n");
-+ return PTR_ERR(phy->phy);
-+ }
-+ phy_set_drvdata(phy->phy, phy);
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+}
-+
-+static struct platform_driver ipq4019_usb_phy_driver = {
-+ .probe = ipq4019_usb_phy_probe,
-+ .driver = {
-+ .of_match_table = ipq4019_usb_phy_of_match,
-+ .name = "ipq4019-usb-phy",
-+ }
-+};
-+module_platform_driver(ipq4019_usb_phy_driver);
-+
-+MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver");
-+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sat, 19 Nov 2016 00:58:18 +0100
-Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
-
-Add support for the Qualcomm Atheros IPQ4019 SoC.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/Makefile | 1 +
- arch/arm/mach-qcom/Kconfig | 5 +++++
- 2 files changed, 6 insertions(+)
-
---- a/arch/arm/Makefile
-+++ b/arch/arm/Makefile
-@@ -149,6 +149,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
- endif
- textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
- textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
-+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
- textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
-
- # Machine directory name. This list is sorted alphanumerically
---- a/arch/arm/mach-qcom/Kconfig
-+++ b/arch/arm/mach-qcom/Kconfig
-@@ -27,4 +27,9 @@ config ARCH_MDM9615
- bool "Enable support for MDM9615"
- select CLKSRC_QCOM
-
-+config ARCH_IPQ40XX
-+ bool "Enable support for IPQ40XX"
-+ select CLKSRC_QCOM
-+ select HAVE_ARM_ARCH_TIMER
-+
- endif
+++ /dev/null
-From fc566294610fa49e9d8c31c4ecc9c82f49b11f59 Mon Sep 17 00:00:00 2001
-From: Sven Eckelmann <sven.eckelmann@openmesh.com>
-Date: Wed, 18 Apr 2018 09:10:44 +0200
-Subject: [PATCH] ARM: dts: ipq4019: Add TZ and SMEM reserved regions
-
-The QSEE (trustzone) is started on IPQ4019 before Linux is started.
-According to QCA, it is placed in in the the memory region
-0x87e80000-0x88000000 and must not be accessed directly. There is an
-additional memory region 0x87e00000-0x87E80000 smem which which can be used
-for communication with the TZ. The driver for the latter is not yet ready
-but it is still not allowed to use this memory region like any other
-memory region.
-
-Not reserving this memory region either leads to kernel crashes, kernel
-hangs (often during the boot) or bus errors for userspace programs. The
-latter happens when a program is using a memory region which is mapped to
-these physical memory regions.
-
- [ 571.758058] Unhandled fault: imprecise external abort (0xc06) at 0x01715ff8
- [ 571.758099] pgd = cebec000
- [ 571.763826] [01715ff8] *pgd=8e7fa835, *pte=87e7f75f, *ppte=87e7fc7f
- Bus error
-
-Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
-
-Forwarded: https://patchwork.kernel.org/patch/10347459/
----
-Cc: Sricharan Ramabadhran <srichara@qti.qualcomm.com>
-Cc: Senthilkumar N L <snlakshm@qti.qualcomm.com>
-
-There are additional memory regions which have to be initialized first by
-Linux. So they are currently not used. We were told by QCA that the
-features QSDK uses them for are:
-
-* crash dump feature
- - a couple of regions used when 'qca,scm_restart_reason' dt node has the
- value 'dload_status' not set to 1
- + apps_bl <0x87000000 0x400000>
- + sbl <0x87400000 0x100000>
- + cnss_debug <0x87400000 0x100000>
- + cpu_context_dump <0x87b00000 0x080000>
- - required driver not available in Linux
- - safe to remove
-* QSEE app execution
- - region tz_apps <0x87b80000 0x280000>
- - required driver not available in Linux
- - safe to remove
-* communication with TZ/QSEE
- - region smem <0x87b80000 0x280000>
- - driver changes not yet upstreamed
- - must not be removed because any access can crash kernel/program
-* trustzone (QSEE) private memory
- - region tz <0x87e80000 0x180000>
- - must not be removed because any access can crash kernel/program
-
-The problem with the missing regions was reported in 2016 [1]. So maybe
-this change qualifies for a stable@vger.kernel.org submission.
-
-[1] https://www.spinics.net/lists/linux-arm-msm/msg21536.html
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -23,6 +23,22 @@
- compatible = "qcom,ipq4019";
- interrupt-parent = <&intc>;
-
-+ reserved-memory {
-+ #address-cells = <0x1>;
-+ #size-cells = <0x1>;
-+ ranges;
-+
-+ smem_region: smem@87e00000 {
-+ reg = <0x87e00000 0x080000>;
-+ no-map;
-+ };
-+
-+ tz@87e80000 {
-+ reg = <0x87e80000 0x180000>;
-+ no-map;
-+ };
-+ };
-+
- aliases {
- spi0 = &spi_0;
- spi1 = &spi_1;
+++ /dev/null
-From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@googlemail.com>
-Date: Thu, 11 Mar 2018 14:41:31 +0100
-Subject: [PATCH] clk: fix apss cpu overclocking
-
-There's an interaction issue between the clk changes:"
-clk: qcom: ipq4019: Add the apss cpu pll divider clock node
-clk: qcom: ipq4019: remove fixed clocks and add pll clocks
-" and the cpufreq-dt.
-
-cpufreq-dt is now spamming the kernel-log with the following:
-
-[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
-for freq 761142857 (-34)
-
-This only happens on certain devices like the Compex WPJ428
-and AVM FritzBox!4040. However, other devices like the Asus
-RT-AC58U and Meraki MR33 work just fine.
-
-The issue stem from the fact that all higher CPU-Clocks
-are achieved by switching the clock-parent to the P_DDRPLLAPSS
-(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
-as part of the DDR calibration.
-
-For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
-at round 533 MHz (ddrpllsdcc = 190285714 Hz).
-
-whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
-clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
-
-This patch attempts to fix the issue by modifying
-clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
-to use a new qcom_find_freq_close() function, which returns the closest
-matching frequency, instead of the next higher. This way, the SoC in
-the FB4040 (with its max clock speed of 710.4 MHz) will no longer
-try to overclock to 761 MHz.
-
-Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1253,6 +1253,29 @@ static const struct clk_fepll_vco gcc_fe
- .reg = 0x2f020,
- };
-
-+
-+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
-+ unsigned long rate)
-+{
-+ const struct freq_tbl *last = NULL;
-+
-+ for ( ; f->freq; f++) {
-+ if (rate == f->freq)
-+ return f;
-+
-+ if (f->freq > rate) {
-+ if (!last ||
-+ (f->freq - rate) < (rate - last->freq))
-+ return f;
-+ else
-+ return last;
-+ }
-+ last = f;
-+ }
-+
-+ return last;
-+}
-+
- /*
- * Round rate function for APSS CPU PLL Clock divider.
- * It looks up the frequency table and returns the next higher frequency
-@@ -1265,7 +1288,7 @@ static long clk_cpu_div_round_rate(struc
- struct clk_hw *p_hw;
- const struct freq_tbl *f;
-
-- f = qcom_find_freq(pll->freq_tbl, rate);
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
- if (!f)
- return -EINVAL;
-
-@@ -1288,7 +1311,7 @@ static int clk_cpu_div_set_rate(struct c
- u32 mask;
- int ret;
-
-- f = qcom_find_freq(pll->freq_tbl, rate);
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
- if (!f)
- return -EINVAL;
-
-@@ -1315,6 +1338,7 @@ static unsigned long
- clk_cpu_div_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
- {
-+ const struct freq_tbl *f;
- struct clk_fepll *pll = to_clk_fepll(hw);
- u32 cdiv, pre_div;
- u64 rate;
-@@ -1335,7 +1359,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
- rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
- do_div(rate, pre_div);
-
-- return rate;
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
-+ if (!f)
-+ return rate;
-+
-+ return f->freq;
- };
-
- static const struct clk_ops clk_regmap_cpu_div_ops = {
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+===================================================================
+--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -15,12 +15,39 @@
*/
rng@22000 {
status = "ok";
};
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -93,14 +93,6 @@
+@@ -66,14 +93,6 @@
pinctrl-names = "default";
status = "ok";
cs-gpios = <&tlmm 54 0>;
};
serial@78af000 {
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-@@ -19,4 +19,71 @@
+@@ -102,6 +121,22 @@
+ status = "ok";
+ };
+
++ mdio@90000 {
++ status = "okay";
++ };
++
++ ess-switch@c000000 {
++ status = "okay";
++ };
++
++ ess-psgmii@98000 {
++ status = "okay";
++ };
++
++ edma@c080000 {
++ status = "okay";
++ };
++
+ usb3_ss_phy: ssphy@9a000 {
+ status = "ok";
+ };
+Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+===================================================================
+--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
++++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+@@ -18,5 +18,73 @@
+
/ {
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
++ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019";
+ memory {
+ device_type = "memory";
+ };
+};
+
-+&spi_0 {
++&blsp1_spi1 {
+ mx25l25635f@0 {
+ compatible = "mx25l25635f", "jedec,spi-nor";
+ #address-cells = <1>;
+ };
+ };
};
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-@@ -18,6 +18,7 @@
-
- / {
- model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
-+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019";
-
- memory {
- device_type = "memory";
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -121,6 +121,22 @@
- status = "ok";
- };
-
-+ mdio@90000 {
-+ status = "okay";
-+ };
-+
-+ ess-switch@c000000 {
-+ status = "okay";
-+ };
-+
-+ ess-psgmii@98000 {
-+ status = "okay";
-+ };
-+
-+ edma@c080000 {
-+ status = "okay";
-+ };
-+
- usb3_ss_phy: ssphy@9a000 {
- status = "ok";
- };
projects / openwrt / staging / lynxis.git / commitdiff