drm/i915/selftests: Handle a potential failure of intel_ring_begin

Silence smatch over:

drivers/gpu/drm/i915/selftests/intel_workarounds.c:58 read_nonprivs() error: 'cs' dereferencing possible ERR_PTR()

by handling a potential (but unlikely) failure of intel_ring_begin.

Fixes: f4ecfbfc32ed ("drm/i915: Check whitelist registers across resets")
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1523915821-30624-1-git-send-email-oscar.mateo@intel.com

diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index fe7deca33d77fb739a17c1e7c903412a94b15c26..5455b2626627540bcc84b910fa736f20e14fc56c 100644 (file)
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -54,6 +54,11 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
                srm++;
 
        cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
+       if (IS_ERR(cs)) {
+               err = PTR_ERR(cs);
+               goto err_req;
+       }
+
        for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
                *cs++ = srm;
                *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
@@ -75,6 +80,8 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
 
        return result;
 
+err_req:
+       i915_request_add(rq);
 err_pin:
        i915_vma_unpin(vma);
 err_obj: