mmc: sunxi: Gate the clock when rate is 0

The MMC core assumes that the code will gate the clock when the bus
frequency is set to 0, which we've been ignoring so far.

Handle that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index ab4324e6eb7409e45acec6b91b437ab58bdf9439..019f95e8e7c5052cdb17c1144031f12393e39e17 100644 (file)
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -765,6 +765,9 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
        if (ret)
                return ret;
 
+       if (!ios->clock)
+               return 0;
+
        /* 8 bit DDR requires a higher module clock */
        if (ios->timing == MMC_TIMING_MMC_DDR52 &&
            ios->bus_width == MMC_BUS_WIDTH_8)
@@ -882,7 +885,7 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
        mmc_writel(host, REG_GCTRL, rval);
 
        /* set up clock */
-       if (ios->clock && ios->power_mode) {
+       if (ios->power_mode) {
                host->ferror = sunxi_mmc_clk_set_rate(host, ios);
                /* Android code had a usleep_range(50000, 55000); here */
        }