drm/amd/powerplay: move the funciton of conv_profile_to_workload to asic file

the function of conv_profile_to_workload is asic related function,
so move them into vega20_ppt file

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 2f8fe2a3d6946af1955ae74f0fc12cf6ca6532c1..46f3ac8bfe88d3970ed1c62c47c79b773352167c 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -451,6 +451,7 @@ struct pptable_funcs {
                                              *clocks);
        int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
        int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
+       int (*conv_profile_to_workload)(struct smu_context *smu, int power_profile);
        enum amd_dpm_forced_level (*get_performance_level)(struct smu_context *smu);
        int (*force_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
        int (*pre_display_config_changed)(struct smu_context *smu);
@@ -728,6 +729,8 @@ struct smu_funcs
        ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
 #define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
        ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
+#define smu_conv_profile_to_workload(smu, type) \
+       ((smu)->ppt_funcs->conv_profile_to_workload ? (smu)->ppt_funcs->conv_profile_to_workload((smu), (type)) : 0)
 #define smu_dpm_set_uvd_enable(smu, enable) \
        ((smu)->funcs->dpm_set_uvd_enable ? (smu)->funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
 #define smu_dpm_set_vce_enable(smu, enable) \

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 14c0a7a2d9a55290770afca52aa914e7e1520804..020ed004a07638513525455f52a46e1ebd27543f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1652,37 +1652,6 @@ static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
        return 0;
 }
 
-static int smu_v11_0_conv_power_profile_to_pplib_workload(int power_profile)
-{
-       int pplib_workload = 0;
-
-       switch (power_profile) {
-       case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
-            pplib_workload = WORKLOAD_DEFAULT_BIT;
-            break;
-       case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
-            pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
-            break;
-       case PP_SMC_POWER_PROFILE_POWERSAVING:
-            pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
-            break;
-       case PP_SMC_POWER_PROFILE_VIDEO:
-            pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
-            break;
-       case PP_SMC_POWER_PROFILE_VR:
-            pplib_workload = WORKLOAD_PPLIB_VR_BIT;
-            break;
-       case PP_SMC_POWER_PROFILE_COMPUTE:
-            pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
-            break;
-       case PP_SMC_POWER_PROFILE_CUSTOM:
-               pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
-               break;
-       }
-
-       return pplib_workload;
-}
-
 static int smu_v11_0_get_power_profile_mode(struct smu_context *smu, char *buf)
 {
        DpmActivityMonitorCoeffInt_t activity_monitor;
@@ -1719,7 +1688,7 @@ static int smu_v11_0_get_power_profile_mode(struct smu_context *smu, char *buf)
 
        for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
                /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
-               workload_type = smu_v11_0_conv_power_profile_to_pplib_workload(i);
+               workload_type = smu_conv_profile_to_workload(smu, i);
                result = smu_update_table_with_arg(smu, TABLE_ACTIVITY_MONITOR_COEFF,
                                                   workload_type, &activity_monitor, false);
                if (result) {
@@ -1868,8 +1837,7 @@ static int smu_v11_0_set_power_profile_mode(struct smu_context *smu, long *input
        }
 
        /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
-       workload_type =
-               smu_v11_0_conv_power_profile_to_pplib_workload(smu->power_profile_mode);
+       workload_type = smu_conv_profile_to_workload(smu, smu->power_profile_mode);
        smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
                                    1 << workload_type);
 
@@ -2142,7 +2110,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
        .get_sclk = smu_v11_0_dpm_get_sclk,
        .get_mclk = smu_v11_0_dpm_get_mclk,
        .set_od8_default_settings = smu_v11_0_set_od8_default_settings,
-       .conv_power_profile_to_pplib_workload = smu_v11_0_conv_power_profile_to_pplib_workload,
        .get_power_profile_mode = smu_v11_0_get_power_profile_mode,
        .set_power_profile_mode = smu_v11_0_set_power_profile_mode,
        .update_od8_settings = smu_v11_0_update_od8_settings,

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 62497ad66a39f3be161fa2c7c53a8c536ff687bb..3243928b6ee26a98b398af0371d7711cd6733696 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1496,6 +1496,37 @@ static int vega20_get_od_percentage(struct smu_context *smu,
        return value;
 }
 
+static int vega20_conv_profile_to_workload(struct smu_context *smu, int power_profile)
+{
+       int pplib_workload = 0;
+
+       switch (power_profile) {
+       case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
+               pplib_workload = WORKLOAD_DEFAULT_BIT;
+               break;
+       case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
+               pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
+               break;
+       case PP_SMC_POWER_PROFILE_POWERSAVING:
+               pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
+               break;
+       case PP_SMC_POWER_PROFILE_VIDEO:
+               pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
+               break;
+       case PP_SMC_POWER_PROFILE_VR:
+               pplib_workload = WORKLOAD_PPLIB_VR_BIT;
+               break;
+       case PP_SMC_POWER_PROFILE_COMPUTE:
+               pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
+               break;
+       case PP_SMC_POWER_PROFILE_CUSTOM:
+               pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
+               break;
+       }
+
+       return pplib_workload;
+}
+
 static int
 vega20_get_profiling_clk_mask(struct smu_context *smu,
                              enum amd_dpm_forced_level level,
@@ -2541,6 +2572,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
        .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
        .set_default_od8_settings = vega20_set_default_od8_setttings,
        .get_od_percentage = vega20_get_od_percentage,
+       .conv_profile_to_workload = vega20_conv_profile_to_workload,
        .get_performance_level = vega20_get_performance_level,
        .force_performance_level = vega20_force_performance_level,
        .update_specified_od8_value = vega20_update_specified_od8_value,