return pll_val;
}
-static void ar71xx_set_pll_ge0(int speed)
+static void ar71xx_set_speed_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
val, AR71XX_ETH0_PLL_SHIFT);
}
-static void ar71xx_set_pll_ge1(int speed)
+static void ar71xx_set_speed_ge1(int speed)
{
u32 val = ar71xx_get_eth_pll(1, speed);
val, AR71XX_ETH1_PLL_SHIFT);
}
-static void ar724x_set_pll_ge0(int speed)
+static void ar724x_set_speed_ge0(int speed)
{
/* TODO */
}
-static void ar724x_set_pll_ge1(int speed)
+static void ar724x_set_speed_ge1(int speed)
{
/* TODO */
}
-static void ar7242_set_pll_ge0(int speed)
+static void ar7242_set_speed_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
void __iomem *base;
iounmap(base);
}
-static void ar91xx_set_pll_ge0(int speed)
+static void ar91xx_set_speed_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
val, AR91XX_ETH0_PLL_SHIFT);
}
-static void ar91xx_set_pll_ge1(int speed)
+static void ar91xx_set_speed_ge1(int speed)
{
u32 val = ar71xx_get_eth_pll(1, speed);
val, AR91XX_ETH1_PLL_SHIFT);
}
-static void ar933x_set_pll_ge0(int speed)
+static void ar933x_set_speed_ge0(int speed)
{
/* TODO */
}
-static void ar933x_set_pll_ge1(int speed)
+static void ar933x_set_speed_ge1(int speed)
{
/* TODO */
}
-static void ar934x_set_pll_ge0(int speed)
+static void ar934x_set_speed_ge0(int speed)
{
/* TODO */
}
-static void ar934x_set_pll_ge1(int speed)
+static void ar934x_set_speed_ge1(int speed)
{
/* TODO */
}
case AR71XX_SOC_AR7130:
pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
: ar71xx_ddr_flush_ge0;
- pdata->set_pll = id ? ar71xx_set_pll_ge1
- : ar71xx_set_pll_ge0;
+ pdata->set_speed = id ? ar71xx_set_speed_ge1
+ : ar71xx_set_speed_ge0;
break;
case AR71XX_SOC_AR7141:
case AR71XX_SOC_AR7161:
pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
: ar71xx_ddr_flush_ge0;
- pdata->set_pll = id ? ar71xx_set_pll_ge1
- : ar71xx_set_pll_ge0;
+ pdata->set_speed = id ? ar71xx_set_speed_ge1
+ : ar71xx_set_speed_ge0;
pdata->has_gbit = 1;
break;
RESET_MODULE_GE1_PHY;
pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
: ar724x_ddr_flush_ge0;
- pdata->set_pll = id ? ar724x_set_pll_ge1
- : ar7242_set_pll_ge0;
+ pdata->set_speed = id ? ar724x_set_speed_ge1
+ : ar7242_set_speed_ge0;
pdata->has_gbit = 1;
pdata->is_ar724x = 1;
ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY;
pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
: ar724x_ddr_flush_ge0;
- pdata->set_pll = id ? ar724x_set_pll_ge1
- : ar724x_set_pll_ge0;
+ pdata->set_speed = id ? ar724x_set_speed_ge1
+ : ar724x_set_speed_ge0;
pdata->is_ar724x = 1;
if (ar71xx_soc == AR71XX_SOC_AR7240)
pdata->is_ar7240 = 1;
case AR71XX_SOC_AR9130:
pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
: ar91xx_ddr_flush_ge0;
- pdata->set_pll = id ? ar91xx_set_pll_ge1
- : ar91xx_set_pll_ge0;
+ pdata->set_speed = id ? ar91xx_set_speed_ge1
+ : ar91xx_set_speed_ge0;
pdata->is_ar91xx = 1;
break;
case AR71XX_SOC_AR9132:
pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
: ar91xx_ddr_flush_ge0;
- pdata->set_pll = id ? ar91xx_set_pll_ge1
- : ar91xx_set_pll_ge0;
+ pdata->set_speed = id ? ar91xx_set_speed_ge1
+ : ar91xx_set_speed_ge0;
pdata->is_ar91xx = 1;
pdata->has_gbit = 1;
break;
AR933X_RESET_GE1_MDIO;
pdata->ddr_flush = id ? ar933x_ddr_flush_ge1
: ar933x_ddr_flush_ge0;
- pdata->set_pll = id ? ar933x_set_pll_ge1
- : ar933x_set_pll_ge0;
+ pdata->set_speed = id ? ar933x_set_speed_ge1
+ : ar933x_set_speed_ge0;
pdata->has_gbit = 1;
pdata->is_ar724x = 1;
AR934X_RESET_GE1_MDIO;
pdata->ddr_flush = id ? ar934x_ddr_flush_ge1
: ar934x_ddr_flush_ge0;
- pdata->set_pll = id ? ar934x_set_pll_ge1
- : ar934x_set_pll_ge0;
+ pdata->set_speed = id ? ar934x_set_speed_ge1
+ : ar934x_set_speed_ge0;
pdata->has_gbit = 1;
pdata->is_ar724x = 1;