ar71xx: fix NAND controller base for QCA955x SoCs
authorGabor Juhos <juhosg@openwrt.org>
Tue, 1 Jan 2013 13:10:26 +0000 (13:10 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Tue, 1 Jan 2013 13:10:26 +0000 (13:10 +0000)
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 34942

target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch

index 407de3600826ad634a63b5fa0c46640efff97482..26c87c8ef2628cb309027eb7110ec3b8d724d581 100644 (file)
@@ -50,7 +50,7 @@
  #define QCA955X_EHCI_SIZE     0x200
 +#define QCA955X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
 +#define QCA955X_GMAC_SIZE     0x40
-+#define QCA955X_NFC_BASE      0x1b000200
++#define QCA955X_NFC_BASE      0x1b800200
 +#define QCA955X_NFC_SIZE      0xb8
  
  #define AR9300_OTP_BASE               0x14000
index 38290e88574de8df015d9af5d147c4801b857c4b..aa962059b7dcee6c80e8a42b99b7f32f7c63b048 100644 (file)
@@ -48,7 +48,7 @@
  #define QCA955X_EHCI_SIZE     0x200
 +#define QCA955X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
 +#define QCA955X_GMAC_SIZE     0x40
-+#define QCA955X_NFC_BASE      0x1b000200
++#define QCA955X_NFC_BASE      0x1b800200
 +#define QCA955X_NFC_SIZE      0xb8
  
  #define AR9300_OTP_BASE               0x14000