ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10

This function was never used in SPL and the default implementation of
dram_bank_mmu_setup() does the same thing. The only difference is the
part which configures OCRAM as cachable, which doesn't really work as
it covers more than the OCRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index 706a038b88809149e6b39186fa5c6c6d41f20561..1f2b7f4819901ffbf94e05d17c57c4062a6f14c8 100644 (file)
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -713,28 +713,3 @@ int ddr_calibration_sequence(void)
 
        return 0;
 }
-
-void dram_bank_mmu_setup(int bank)
-{
-       bd_t *bd = gd->bd;
-       int     i;
-
-       debug("%s: bank: %d\n", __func__, bank);
-       for (i = bd->bi_dram[bank].start >> 20;
-            i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
-            i++) {
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-               set_section_dcache(i, DCACHE_WRITETHROUGH);
-#else
-               set_section_dcache(i, DCACHE_WRITEBACK);
-#endif
-       }
-
-       /* same as above but just that we would want cacheable for ocram too */
-       i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-       set_section_dcache(i, DCACHE_WRITETHROUGH);
-#else
-       set_section_dcache(i, DCACHE_WRITEBACK);
-#endif
-}