armv7:ls1021a: Enable workaround for DDR erratum A-009942
authorShengzhou Liu <Shengzhou.Liu@nxp.com>
Thu, 1 Sep 2016 06:50:36 +0000 (14:50 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 14 Sep 2016 21:08:15 +0000 (14:08 -0700)
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/include/asm/arch-ls102xa/config.h
board/freescale/ls1021atwr/ls1021atwr.c

index ab9493f01cca4883e7bba9d467801ca6fe4665f6..f2ce793c8f5f2477187faea9e40c381ef5676f9f 100644 (file)
 #define CONFIG_USB_MAX_CONTROLLER_COUNT                1
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A010315
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #else
index 4638bed478eae8ee7acd92517ff6a6b2c864bd2a..d96fd774d36b3d7e5c8950fa298e053f1c8780df 100644 (file)
@@ -142,7 +142,7 @@ int checkboard(void)
 void ddrmc_init(void)
 {
        struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
-       u32 temp_sdram_cfg;
+       u32 temp_sdram_cfg, tmp;
 
        out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 
@@ -189,6 +189,11 @@ void ddrmc_init(void)
        out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 
        out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+       /* DDR erratum A-009942 */
+       tmp = in_be32(&ddr->debug[28]);
+       out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
        udelay(1);
 
 #ifdef CONFIG_DEEP_SLEEP