/*
- * Copyright 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define IMX_IO_MUX_H
#include <stdint.h>
+#include <lib/utils_def.h>
/*
* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET 0x0020
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET 0x0024
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET 0x0028
+
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET 0x002C
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B BIT(0)
+
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET 0x0030
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET 0x0034
#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET 0x0154
#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET 0x0158
#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET 0x015C
+
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET 0x0160
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT0_I2C4_SCL 0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT2_WDOG4_WDOG_B BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT3_CSI_PIXCLK (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT4_USB_OTG1_ID BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT5_GPIO4_IO14 (BIT(2) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT6_EPDC_VCOM0 (BIT(2) | BIT(1))
+
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET 0x0164
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT0_I2C4_SDA 0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT2_WDOG4_WDOG_RST_B_DEB BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT3_CSI_MCLK (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT4_USB_OTG2_ID BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT5_GPIO4_IO15 (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT6_EPDC_VCOM1 (BIT(2) | BIT(1))
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET 0x0168
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK 0x00
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET 0x01C4
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET 0x01C8
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET 0x01CC
+
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET 0x01D0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET 0x01D4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET 0x01D8
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET 0x0434
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET 0x0438
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET 0x043C
+
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET 0x0440
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET 0x0444
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET 0x0448
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET 0x0464
#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET 0x0468
#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET 0x046C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_0_X1 0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4 BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_2_X2 BIT(1)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6 (BIT(1) | BIT(0))
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4 BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW BIT(2)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_FAST 0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_HYS BIT(3)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PE BIT(4)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PD_100K (0 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_5K (1 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K (2 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_100K (3 << 5)
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0470
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0474
#define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET 0x0708
#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET 0x070C
#define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET 0x0710
+
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET 0x0714
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SCL_ALT1 0x00
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SDA_ALT1 BIT(0)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_RX_DATA_ALT2 BIT(1)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_TX_BCLK_ALT2 (BIT(1) | BIT(0))
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO06_ALT3 BIT(2)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO07_ALT3 (BIT(2) | BIT(1))
+
#define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET 0x0718
#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET 0x071C
#define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET 0x0720
--- /dev/null
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <plat/common/common_def.h>
+
+#define PLATFORM_STACK_SIZE 0x1000
+
+#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
+#define PLATFORM_CLUSTER_COUNT 1
+#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
+
+#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
+
+#define PICOPI_PRIMARY_CPU 0
+
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
+
+#define PLAT_MAX_RET_STATE 1
+#define PLAT_MAX_OFF_STATE 2
+
+/* Local power state for power domains in Run state. */
+#define PLAT_LOCAL_STATE_RUN 0
+
+/* Local power state for retention. Valid only for CPU power domains */
+#define PLAT_LOCAL_STATE_RET 1
+
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains.
+ */
+#define PLAT_LOCAL_STATE_OFF 2
+
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ * i.MX7 has a 32 byte cacheline size
+ * i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01/2018 pg 298
+ */
+#define CACHE_WRITEBACK_SHIFT 4
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+/*
+ * Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
+ */
+#define BOOT_ROM_BASE 0x00000000
+#define BOOT_ROM_SIZE 0x00020000
+
+#define OCRAM_S_BASE 0x00180000
+#define OCRAM_S_SIZE 0x00008000
+
+/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
+#define DRAM_BASE 0x80000000
+#define DRAM_SIZE 0x20000000
+#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
+
+/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
+#define IMX7_OPTEE_SIZE 0x02000000
+#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE)
+#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
+
+/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
+#define BL2_RAM_SIZE 0x00100000
+#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE)
+#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
+#define SHARED_RAM_SIZE 0x00001000
+#define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE)
+#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE)
+
+/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
+#define IMX7_UBOOT_SIZE 0x00100000
+#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
+#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
+
+/* Define FIP image absolute location 0x80000000 - 0x80100000 */
+#define IMX7_FIP_SIZE 0x00100000
+#define IMX7_FIP_BASE (DRAM_BASE)
+#define IMX7_FIP_LIMIT (IMX7_FIP_BASE + IMX7_FIP_SIZE)
+
+/* Define FIP image location at 1MB offset */
+#define IMX7_FIP_MMC_BASE (1024 * 1024)
+
+/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
+#define IMX7_DTB_SIZE 0x00100000
+#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
+#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE)
+
+/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
+#define IMX7_DTB_OVERLAY_SIZE 0x00001000
+#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT
+#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \
+ IMX7_DTB_OVERLAY_SIZE)
+/*
+ * BL2 specific defines.
+ *
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
+#define BL2_BASE BL2_RAM_BASE
+#define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/*
+ * BL3-2/OPTEE
+ */
+# define BL32_BASE IMX7_OPTEE_BASE
+# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
+
+/*
+ * BL3-3/U-BOOT
+ */
+#define BL33_BASE IMX7_UBOOT_BASE
+#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
+
+/*
+ * ATF's view of memory
+ *
+ * 0xa0000000 +-----------------+
+ * | DDR | BL32/OPTEE
+ * 0x9e000000 +-----------------+
+ * | DDR | BL23 ATF
+ * 0x9df00000 +-----------------+
+ * | DDR | Shared MBOX RAM
+ * 0x9de00000 +-----------------+
+ * | DDR | Unallocated
+ * 0x87900000 +-----------------+
+ * | DDR | BL33/U-BOOT
+ * 0x87800000 +-----------------+
+ * | DDR | Unallocated
+ * 0x83100000 +-----------------+
+ * | DDR | DTB
+ * 0x83000000 +-----------------+
+ * | DDR | Unallocated
+ * 0x80100000 +-----------------+
+ * | DDR | FIP
+ * 0x80000000 +-----------------+
+ * | SOC I/0 |
+ * 0x00a00000 +-----------------+
+ * | OCRAM | Not used
+ * 0x00900000 +-----------------+
+ * | SOC I/0 |
+ * 0x00188000 +-----------------+
+ * | OCRAM_S | Not used
+ * 0x00180000 +-----------------+
+ * | SOC I/0 |
+ * 0x00020000 +-----------------+
+ * | BootROM | BL1
+ * 0x00000000 +-----------------+
+ */
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define MAX_MMAP_REGIONS 10
+#define MAX_XLAT_TABLES 6
+#define MAX_IO_DEVICES 2
+#define MAX_IO_HANDLES 3
+#define MAX_IO_BLOCK_DEVICES 1
+
+/* UART defines */
+#define PLAT_IMX7_BOOT_UART_BASE MXC_UART5_BASE
+#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000
+#define PLAT_IMX7_CONSOLE_BAUDRATE 115200
+
+/* MMC defines */
+#ifndef PLAT_PICOPI_SD
+#define PLAT_PICOPI_SD 3
+#endif
+
+#if PLAT_PICOPI_SD == 1
+#define PLAT_PICOPI_BOOT_MMC_BASE USDHC1_BASE
+#endif /* PLAT_PICOPI_SD == 1 */
+
+#if PLAT_PICOPI_SD == 2
+#define PLAT_PICOPI_BOOT_MMC_BASE USDHC2_BASE
+#endif /* PLAT_PICOPI_SD == 2 */
+
+#if PLAT_PICOPI_SD == 3
+#define PLAT_PICOPI_BOOT_MMC_BASE USDHC3_BASE
+#endif /* PLAT_PICOPI_SD == 3 */
+
+/*
+ * System counter
+ */
+#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */
+
+#endif /* PLATFORM_DEF_H */
--- /dev/null
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <drivers/mmc.h>
+#include <lib/utils.h>
+
+#include <imx_caam.h>
+#include <imx_clock.h>
+#include <imx_io_mux.h>
+#include <imx_uart.h>
+#include <imx_usdhc.h>
+#include <imx7_def.h>
+
+#define UART5_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M)
+
+#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
+ CCM_TARGET_POST_PODF(2))
+
+#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
+
+#define PICOPI_UART5_RX_MUX \
+ IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA
+
+#define PICOPI_UART5_TX_MUX \
+ IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA
+
+#define PICOPI_SD3_FEATURES \
+ (IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K | \
+ IOMUXC_SW_PAD_CTL_PAD_SD3_PE | \
+ IOMUXC_SW_PAD_CTL_PAD_SD3_HYS | \
+ IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW | \
+ IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6)
+
+static void picopi_setup_pinmux(void)
+{
+ /* Configure UART5 TX */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET,
+ PICOPI_UART5_TX_MUX);
+ /* Configure UART5 RX */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET,
+ PICOPI_UART5_RX_MUX);
+
+ /* Configure USDHC3 */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET,
+ IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B);
+
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET,
+ PICOPI_SD3_FEATURES);
+}
+
+static void picopi_usdhc_setup(void)
+{
+ imx_usdhc_params_t params;
+ struct mmc_device_info info;
+
+ zeromem(¶ms, sizeof(imx_usdhc_params_t));
+ params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE;
+ params.clk_rate = 25000000;
+ params.bus_width = MMC_BUS_WIDTH_8;
+ info.mmc_dev_type = MMC_IS_EMMC;
+ imx_usdhc_init(¶ms, &info);
+}
+
+static void picopi_setup_usb_clocks(void)
+{
+ uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
+
+ imx_clock_set_usb_clk_root_bits(usb_en_bits);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
+}
+
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
+ u_register_t arg3, u_register_t arg4)
+{
+ uint32_t uart5_en_bits = (uint32_t)UART5_CLK_SELECT;
+ uint32_t usdhc_clock_sel = PLAT_PICOPI_SD - 1;
+
+ /* Initialize clocks etc */
+ imx_clock_enable_uart(4, uart5_en_bits);
+ imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
+
+ picopi_setup_usb_clocks();
+
+ /* Setup pin-muxes */
+ picopi_setup_pinmux();
+
+ picopi_usdhc_setup();
+}
--- /dev/null
+#
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Include imx7 common
+include plat/imx/imx7/common/imx7.mk
+
+# Platform
+PLAT_INCLUDES += -Iplat/imx/imx7/picopi/include \
+
+BL2_SOURCES += drivers/imx/usdhc/imx_usdhc.c \
+ plat/imx/imx7/picopi/picopi_bl2_el3_setup.c \
+
+# Build config flags
+# ------------------
+
+ARM_CORTEX_A7 := yes
+WORKAROUND_CVE_2017_5715 := 0
+
+RESET_TO_BL31 := 0
+
+# Non-TF Boot ROM
+BL2_AT_EL3 := 1
+
+# Indicate single-core
+COLD_BOOT_SINGLE_CPU := 1
+
+# Have different sections for code and rodata
+SEPARATE_CODE_AND_RODATA := 1
+
+# Use Coherent memory
+USE_COHERENT_MEM := 1
+
+# Use multi console API
+MULTI_CONSOLE_API := 1
+
+PLAT_PICOPI_UART :=5
+$(eval $(call add_define,PLAT_PICOPI_UART))
projects / project / bcm63xx / atf.git / commitdiff