-From cb376159800b9b44be76949c3aee89eb06d29faa Mon Sep 17 00:00:00 2001
+From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 09:55:13 +0100
-Subject: [PATCH 07/27] irqchip/irq-ath79-intc: add irq cascade driver for
+Subject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for
QCA9556 SoCs
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/irqchip/Makefile | 1 +
- drivers/irqchip/irq-ath79-intc.c | 104 +++++++++++++++++++++++++++++++++++++++
- 2 files changed, 105 insertions(+)
+ drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 143 insertions(+)
create mode 100644 drivers/irqchip/irq-ath79-intc.c
--- a/drivers/irqchip/Makefile
-From f711421eb5f6f790f1ebc09a13ae4aed8ba5f67b Mon Sep 17 00:00:00 2001
+From e029f998594f151008ecbfa024e2957edd2a5189 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 09:58:19 +0100
-Subject: [PATCH 08/27] irqchip/irq-ath79-cpu: drop !OF init helper
+Subject: [PATCH 08/33] irqchip/irq-ath79-cpu: drop !OF init helper
Signed-off-by: John Crispin <john@phrozen.org>
---
-From 3ea2bff4ed3ce74dc4303aa20f5e906e78352f6b Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
+From e93fe20529aeb8738b87533f66c46e2c21524530 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
Date: Tue, 6 Mar 2018 10:06:10 +0100
-Subject: [PATCH 09/27] MIPS: ath79: add lots of missing registers
+Subject: [PATCH 09/33] MIPS: ath79: add lots of missing registers
+This patch adds many new registers for various QCA MIPS SoCs. The patch is
+an aggragate of many contributions made to OpenWrt.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Henryk Heisig <hyniu@o2.pl>
+Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
+Signed-off-by: Weijie Gao <hackpascal@gmail.com>
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Julien Dusser <julien.dusser@free.fr>
Signed-off-by: John Crispin <john@phrozen.org>
---
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 773 ++++++++++++++++++++++++-
- 1 file changed, 771 insertions(+), 2 deletions(-)
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 771 ++++++++++++++++++++++++-
+ 1 file changed, 770 insertions(+), 1 deletion(-)
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
/*
* SRIF block
-@@ -552,4 +1007,322 @@
+@@ -552,4 +1007,318 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
-+#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3
-+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18
-+#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3
-+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20
+
+/*
+ * QCA953X GMAC Interface
--- /dev/null
+From 2741304648dbdab7697d7758166a582b5291c53d Mon Sep 17 00:00:00 2001
+From: Matthias Schiffer <mschiffer@universe-factory.net>
+Date: Sat, 23 Jun 2018 15:08:56 +0200
+Subject: [PATCH 10/33] MIPS: ath79: add support for QCA953x QCA956x TP9343
+
+This patch adds support for 2 new types of QCA silicon. TP9343 is
+essentially the same as the QCA956X but is licensed by TPLink.
+
+Signed-off-by: Weijie Gao <hackpascal@gmail.com>
+Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/clock.c | 193 +++++++++++++++++++++++++++++++
+ arch/mips/ath79/common.c | 8 ++
+ arch/mips/ath79/early_printk.c | 4 +
+ arch/mips/ath79/setup.c | 34 +++++-
+ arch/mips/include/asm/mach-ath79/ath79.h | 33 ++++++
+ 5 files changed, 269 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(vo
+ iounmap(dpll_base);
+ }
+
++static void __init qca953x_clocks_init(void)
++{
++ unsigned long ref_rate;
++ unsigned long cpu_rate;
++ unsigned long ddr_rate;
++ unsigned long ahb_rate;
++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
++ u32 cpu_pll, ddr_pll;
++ u32 bootstrap;
++
++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
++ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
++ ref_rate = 40 * 1000 * 1000;
++ else
++ ref_rate = 25 * 1000 * 1000;
++
++ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
++ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
++ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
++ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
++ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
++ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
++ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
++
++ cpu_pll = nint * ref_rate / ref_div;
++ cpu_pll += frac * (ref_rate >> 6) / ref_div;
++ cpu_pll /= (1 << out_div);
++
++ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
++ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
++ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
++ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
++ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
++ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
++ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
++ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
++ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
++
++ ddr_pll = nint * ref_rate / ref_div;
++ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
++ ddr_pll /= (1 << out_div);
++
++ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
++
++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
++ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
++
++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
++ cpu_rate = ref_rate;
++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
++ cpu_rate = cpu_pll / (postdiv + 1);
++ else
++ cpu_rate = ddr_pll / (postdiv + 1);
++
++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
++ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
++
++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
++ ddr_rate = ref_rate;
++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
++ ddr_rate = ddr_pll / (postdiv + 1);
++ else
++ ddr_rate = cpu_pll / (postdiv + 1);
++
++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
++ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
++
++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
++ ahb_rate = ref_rate;
++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
++ ahb_rate = ddr_pll / (postdiv + 1);
++ else
++ ahb_rate = cpu_pll / (postdiv + 1);
++
++ ath79_add_sys_clkdev("ref", ref_rate);
++ ath79_add_sys_clkdev("cpu", cpu_rate);
++ ath79_add_sys_clkdev("ddr", ddr_rate);
++ ath79_add_sys_clkdev("ahb", ahb_rate);
++
++ clk_add_alias("wdt", NULL, "ref", NULL);
++ clk_add_alias("uart", NULL, "ref", NULL);
++}
++
+ static void __init qca955x_clocks_init(void)
+ {
+ unsigned long ref_rate;
+@@ -440,6 +525,110 @@ static void __init qca955x_clocks_init(v
+ clk_add_alias("uart", NULL, "ref", NULL);
+ }
+
++static void __init qca956x_clocks_init(void)
++{
++ unsigned long ref_rate;
++ unsigned long cpu_rate;
++ unsigned long ddr_rate;
++ unsigned long ahb_rate;
++ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
++ u32 cpu_pll, ddr_pll;
++ u32 bootstrap;
++
++ /*
++ * QCA956x timer init workaround has to be applied right before setting
++ * up the clock. Else, there will be no jiffies
++ */
++ u32 misc;
++
++ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
++ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
++ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
++
++ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
++ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
++ ref_rate = 40 * 1000 * 1000;
++ else
++ ref_rate = 25 * 1000 * 1000;
++
++ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
++ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
++ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
++
++ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
++ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
++ QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
++ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
++ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
++ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
++ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
++
++ cpu_pll = nint * ref_rate / ref_div;
++ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
++ cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
++ cpu_pll /= (1 << out_div);
++
++ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
++ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
++ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
++ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
++ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
++ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
++ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
++ QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
++ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
++ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
++ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
++ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
++
++ ddr_pll = nint * ref_rate / ref_div;
++ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
++ ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
++ ddr_pll /= (1 << out_div);
++
++ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
++
++ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
++ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
++
++ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
++ cpu_rate = ref_rate;
++ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
++ cpu_rate = ddr_pll / (postdiv + 1);
++ else
++ cpu_rate = cpu_pll / (postdiv + 1);
++
++ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
++ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
++
++ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
++ ddr_rate = ref_rate;
++ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
++ ddr_rate = cpu_pll / (postdiv + 1);
++ else
++ ddr_rate = ddr_pll / (postdiv + 1);
++
++ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
++ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
++
++ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
++ ahb_rate = ref_rate;
++ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
++ ahb_rate = ddr_pll / (postdiv + 1);
++ else
++ ahb_rate = cpu_pll / (postdiv + 1);
++
++ ath79_add_sys_clkdev("ref", ref_rate);
++ ath79_add_sys_clkdev("cpu", cpu_rate);
++ ath79_add_sys_clkdev("ddr", ddr_rate);
++ ath79_add_sys_clkdev("ahb", ahb_rate);
++
++ clk_add_alias("wdt", NULL, "ref", NULL);
++ clk_add_alias("uart", NULL, "ref", NULL);
++}
++
+ void __init ath79_clocks_init(void)
+ {
+ if (soc_is_ar71xx())
+@@ -450,8 +639,12 @@ void __init ath79_clocks_init(void)
+ ar933x_clocks_init();
+ else if (soc_is_ar934x())
+ ar934x_clocks_init();
++ else if (soc_is_qca953x())
++ qca953x_clocks_init();
+ else if (soc_is_qca955x())
+ qca955x_clocks_init();
++ else if (soc_is_qca956x() || soc_is_tp9343())
++ qca956x_clocks_init();
+ else
+ BUG();
+ }
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -103,8 +103,12 @@ void ath79_device_reset_set(u32 mask)
+ reg = AR933X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar934x())
+ reg = AR934X_RESET_REG_RESET_MODULE;
++ else if (soc_is_qca953x())
++ reg = QCA953X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca955x())
+ reg = QCA955X_RESET_REG_RESET_MODULE;
++ else if (soc_is_qca956x() || soc_is_tp9343())
++ reg = QCA956X_RESET_REG_RESET_MODULE;
+ else
+ BUG();
+
+@@ -131,8 +135,12 @@ void ath79_device_reset_clear(u32 mask)
+ reg = AR933X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar934x())
+ reg = AR934X_RESET_REG_RESET_MODULE;
++ else if (soc_is_qca953x())
++ reg = QCA953X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca955x())
+ reg = QCA955X_RESET_REG_RESET_MODULE;
++ else if (soc_is_qca956x() || soc_is_tp9343())
++ reg = QCA956X_RESET_REG_RESET_MODULE;
+ else
+ BUG();
+
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -76,8 +76,12 @@ static void prom_putchar_init(void)
+ case REV_ID_MAJOR_AR9341:
+ case REV_ID_MAJOR_AR9342:
+ case REV_ID_MAJOR_AR9344:
++ case REV_ID_MAJOR_QCA9533:
++ case REV_ID_MAJOR_QCA9533_V2:
+ case REV_ID_MAJOR_QCA9556:
+ case REV_ID_MAJOR_QCA9558:
++ case REV_ID_MAJOR_TP9343:
++ case REV_ID_MAJOR_QCA956X:
+ _prom_putchar = prom_putchar_ar71xx;
+ break;
+
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
+ u32 major;
+ u32 minor;
+ u32 rev = 0;
++ u32 ver = 1;
+
+ id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
+ major = id & REV_ID_MAJOR_MASK;
+@@ -151,6 +152,17 @@ static void __init ath79_detect_sys_type
+ rev = id & AR934X_REV_ID_REVISION_MASK;
+ break;
+
++ case REV_ID_MAJOR_QCA9533_V2:
++ ver = 2;
++ ath79_soc_rev = 2;
++ /* drop through */
++
++ case REV_ID_MAJOR_QCA9533:
++ ath79_soc = ATH79_SOC_QCA9533;
++ chip = "9533";
++ rev = id & QCA953X_REV_ID_REVISION_MASK;
++ break;
++
+ case REV_ID_MAJOR_QCA9556:
+ ath79_soc = ATH79_SOC_QCA9556;
+ chip = "9556";
+@@ -163,14 +175,30 @@ static void __init ath79_detect_sys_type
+ rev = id & QCA955X_REV_ID_REVISION_MASK;
+ break;
+
++ case REV_ID_MAJOR_QCA956X:
++ ath79_soc = ATH79_SOC_QCA956X;
++ chip = "956X";
++ rev = id & QCA956X_REV_ID_REVISION_MASK;
++ break;
++
++ case REV_ID_MAJOR_TP9343:
++ ath79_soc = ATH79_SOC_TP9343;
++ chip = "9343";
++ rev = id & QCA956X_REV_ID_REVISION_MASK;
++ break;
++
+ default:
+ panic("ath79: unknown SoC, id:0x%08x", id);
+ }
+
+- ath79_soc_rev = rev;
++ if (ver == 1)
++ ath79_soc_rev = rev;
+
+- if (soc_is_qca955x())
+- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
++ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
++ chip, ver, rev);
++ else if (soc_is_tp9343())
++ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
+ chip, rev);
+ else
+ sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,8 +32,11 @@ enum ath79_soc_type {
+ ATH79_SOC_AR9341,
+ ATH79_SOC_AR9342,
+ ATH79_SOC_AR9344,
++ ATH79_SOC_QCA9533,
+ ATH79_SOC_QCA9556,
+ ATH79_SOC_QCA9558,
++ ATH79_SOC_TP9343,
++ ATH79_SOC_QCA956X,
+ };
+
+ extern enum ath79_soc_type ath79_soc;
+@@ -100,6 +103,16 @@ static inline int soc_is_ar934x(void)
+ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
+
++static inline int soc_is_qca9533(void)
++{
++ return ath79_soc == ATH79_SOC_QCA9533;
++}
++
++static inline int soc_is_qca953x(void)
++{
++ return soc_is_qca9533();
++}
++
+ static inline int soc_is_qca9556(void)
+ {
+ return ath79_soc == ATH79_SOC_QCA9556;
+@@ -115,6 +128,26 @@ static inline int soc_is_qca955x(void)
+ return soc_is_qca9556() || soc_is_qca9558();
+ }
+
++static inline int soc_is_tp9343(void)
++{
++ return ath79_soc == ATH79_SOC_TP9343;
++}
++
++static inline int soc_is_qca9561(void)
++{
++ return ath79_soc == ATH79_SOC_QCA956X;
++}
++
++static inline int soc_is_qca9563(void)
++{
++ return ath79_soc == ATH79_SOC_QCA956X;
++}
++
++static inline int soc_is_qca956x(void)
++{
++ return soc_is_qca9561() || soc_is_qca9563();
++}
++
+ void ath79_ddr_wb_flush(unsigned int reg);
+ void ath79_ddr_set_pci_windows(void);
+
+++ /dev/null
-From f3d5027255ef0752ed12b65c3bf7eb363fc3c096 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 10:00:55 +0100
-Subject: [PATCH 10/27] MIPS: ath79: select the PINCTRL subsystem
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -191,6 +191,7 @@ config ATH79
- select CSRC_R4K
- select DMA_NONCOHERENT
- select GPIOLIB
-+ select PINCTRL
- select HAVE_CLK
- select COMMON_CLK
- select CLKDEV_LOOKUP
--- /dev/null
+From 0c8856211d26f84277f7fcb0b9595e5c646bc464 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 10:00:55 +0100
+Subject: [PATCH 11/33] MIPS: ath79: select the PINCTRL subsystem
+
+The pinmux on QCA SoCs is controlled by a single register. The
+"pinctrl-single" driver can be used but requires the target
+to select PINCTRL.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -191,6 +191,7 @@ config ATH79
+ select CSRC_R4K
+ select DMA_NONCOHERENT
+ select GPIOLIB
++ select PINCTRL
+ select HAVE_CLK
+ select COMMON_CLK
+ select CLKDEV_LOOKUP
+++ /dev/null
-From ac3a5ee699f3baa7654c93a3ffda46be82443344 Mon Sep 17 00:00:00 2001
-From: Markos Chandras <markos.chandras@imgtec.com>
-Date: Wed, 21 Aug 2013 11:47:22 +0100
-Subject: [PATCH 12/27] MIPS: ath79: Avoid using unitialized 'reg' variable
-
-Fixes the following build error:
-arch/mips/include/asm/mach-ath79/ath79.h:139:20: error: 'reg' may be used
-uninitialized in this function [-Werror=maybe-uninitialized]
-arch/mips/ath79/common.c:62:6: note: 'reg' was declared here
-In file included from arch/mips/ath79/common.c:20:0:
-arch/mips/ath79/common.c: In function 'ath79_device_reset_clear':
-arch/mips/include/asm/mach-ath79/ath79.h:139:20:
-error: 'reg' may be used uninitialized in this function
-[-Werror=maybe-uninitialized]
-arch/mips/ath79/common.c:90:6: note: 'reg' was declared here
-
-Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
-Acked-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/ath79/common.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -106,7 +106,7 @@ void ath79_device_reset_set(u32 mask)
- else if (soc_is_qca955x())
- reg = QCA955X_RESET_REG_RESET_MODULE;
- else
-- BUG();
-+ panic("Reset register not defined for this SOC");
-
- spin_lock_irqsave(&ath79_device_reset_lock, flags);
- t = ath79_reset_rr(reg);
-@@ -134,7 +134,7 @@ void ath79_device_reset_clear(u32 mask)
- else if (soc_is_qca955x())
- reg = QCA955X_RESET_REG_RESET_MODULE;
- else
-- BUG();
-+ panic("Reset register not defined for this SOC");
-
- spin_lock_irqsave(&ath79_device_reset_lock, flags);
- t = ath79_reset_rr(reg);
-From 11562939754b8f877562d9a137854022eb521716 Mon Sep 17 00:00:00 2001
+From 59c7470bc5c4b29ed77d46fc4982f1d85b5cbec1 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Mon, 5 Mar 2018 11:33:54 +0100
-Subject: [PATCH 13/27] MIPS: ath79: fix system restart
+Subject: [PATCH 13/33] MIPS: ath79: fix system restart
+
+This patch disables irq on reboot to fix hang issues that were observed
+due to pending interrupts.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
if (cpu_wait)
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -134,6 +134,7 @@ static inline u32 ath79_pll_rr(unsigned
+@@ -167,6 +167,7 @@ static inline u32 ath79_pll_rr(unsigned
static inline void ath79_reset_wr(unsigned reg, u32 val)
{
__raw_writel(val, ath79_reset_base + reg);
-From 5a8496923bafc4350f51b26964fdc3252a09fd79 Mon Sep 17 00:00:00 2001
+From 30dc99e95ac4410072850ae466f696cb56097bb4 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Mon, 5 Mar 2018 11:35:29 +0100
-Subject: [PATCH 14/27] MIPS: ath79: finetune cpu-overrides
+Subject: [PATCH 14/33] MIPS: ath79: finetune cpu-overrides
+
+This patch adds a few additional cpu feature overrides so that they do not
+need to be probed at runtime.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h | 6 ++++++
1 file changed, 6 insertions(+)
-From b14f8260724abec6c82970085dece6a143d3a0db Mon Sep 17 00:00:00 2001
+From f55a400f4a691f3750eaf7bfcd6ecbf7ed1622f0 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 5 Mar 2018 11:38:21 +0100
-Subject: [PATCH 15/27] MIPS: ath79: enable uart during early_prink
+Subject: [PATCH 15/33] MIPS: ath79: enable uart during early_prink
+
+This patch ensures, that the poinmux register is properly setup for the
+boot console uart when early_printk is enabled.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/early_printk.c | 44 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
static void prom_putchar_init(void)
{
void __iomem *base;
-@@ -88,8 +128,10 @@ static void prom_putchar_init(void)
+@@ -92,8 +132,10 @@ static void prom_putchar_init(void)
default:
_prom_putchar = prom_putchar_dummy;
+++ /dev/null
-From cff23ba486e3c5d17c4d7e446f5eddead855c101 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 08:45:55 +0100
-Subject: [PATCH 16/27] MIPS: ath79: add support for QCA953x SoC
-
-Note that the clock calculation looks very similar to the QCA955x, but the
-meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
-
-Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
----
- arch/mips/ath79/Kconfig | 6 ++-
- arch/mips/ath79/clock.c | 87 ++++++++++++++++++++++++++++++++
- arch/mips/ath79/common.c | 4 ++
- arch/mips/ath79/dev-common.c | 4 ++
- arch/mips/ath79/early_printk.c | 2 +
- arch/mips/ath79/irq.c | 33 +++++++++++-
- arch/mips/ath79/setup.c | 21 ++++++--
- arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
- 8 files changed, 162 insertions(+), 6 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -94,6 +94,10 @@ config SOC_AR934X
- select PCI_AR724X if PCI
- def_bool n
-
-+config SOC_QCA953X
-+ select USB_ARCH_HAS_EHCI
-+ def_bool n
-+
- config SOC_QCA955X
- select HW_HAS_PCI
- select PCI_AR724X if PCI
-@@ -115,7 +119,7 @@ config ATH79_DEV_USB
- def_bool n
-
- config ATH79_DEV_WMAC
-- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
-+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
- def_bool n
-
- endif
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(vo
- iounmap(dpll_base);
- }
-
-+static void __init qca953x_clocks_init(void)
-+{
-+ unsigned long ref_rate;
-+ unsigned long cpu_rate;
-+ unsigned long ddr_rate;
-+ unsigned long ahb_rate;
-+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
-+ u32 cpu_pll, ddr_pll;
-+ u32 bootstrap;
-+
-+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
-+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
-+ ref_rate = 40 * 1000 * 1000;
-+ else
-+ ref_rate = 25 * 1000 * 1000;
-+
-+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
-+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
-+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
-+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
-+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
-+ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
-+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
-+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
-+
-+ cpu_pll = nint * ref_rate / ref_div;
-+ cpu_pll += frac * (ref_rate >> 6) / ref_div;
-+ cpu_pll /= (1 << out_div);
-+
-+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
-+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
-+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
-+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
-+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
-+ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
-+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
-+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
-+
-+ ddr_pll = nint * ref_rate / ref_div;
-+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
-+ ddr_pll /= (1 << out_div);
-+
-+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
-+
-+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
-+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-+
-+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
-+ cpu_rate = ref_rate;
-+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
-+ cpu_rate = cpu_pll / (postdiv + 1);
-+ else
-+ cpu_rate = ddr_pll / (postdiv + 1);
-+
-+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
-+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
-+
-+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
-+ ddr_rate = ref_rate;
-+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
-+ ddr_rate = ddr_pll / (postdiv + 1);
-+ else
-+ ddr_rate = cpu_pll / (postdiv + 1);
-+
-+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
-+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
-+
-+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
-+ ahb_rate = ref_rate;
-+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
-+ ahb_rate = ddr_pll / (postdiv + 1);
-+ else
-+ ahb_rate = cpu_pll / (postdiv + 1);
-+
-+ ath79_add_sys_clkdev("ref", ref_rate);
-+ ath79_add_sys_clkdev("cpu", cpu_rate);
-+ ath79_add_sys_clkdev("ddr", ddr_rate);
-+ ath79_add_sys_clkdev("ahb", ahb_rate);
-+
-+ clk_add_alias("wdt", NULL, "ref", NULL);
-+ clk_add_alias("uart", NULL, "ref", NULL);
-+}
-+
- static void __init qca955x_clocks_init(void)
- {
- unsigned long ref_rate;
-@@ -450,6 +535,8 @@ void __init ath79_clocks_init(void)
- ar933x_clocks_init();
- else if (soc_is_ar934x())
- ar934x_clocks_init();
-+ else if (soc_is_qca953x())
-+ qca953x_clocks_init();
- else if (soc_is_qca955x())
- qca955x_clocks_init();
- else
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -103,6 +103,8 @@ void ath79_device_reset_set(u32 mask)
- reg = AR933X_RESET_REG_RESET_MODULE;
- else if (soc_is_ar934x())
- reg = AR934X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_qca953x())
-+ reg = QCA953X_RESET_REG_RESET_MODULE;
- else if (soc_is_qca955x())
- reg = QCA955X_RESET_REG_RESET_MODULE;
- else
-@@ -131,6 +133,8 @@ void ath79_device_reset_clear(u32 mask)
- reg = AR933X_RESET_REG_RESET_MODULE;
- else if (soc_is_ar934x())
- reg = AR934X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_qca953x())
-+ reg = QCA953X_RESET_REG_RESET_MODULE;
- else if (soc_is_qca955x())
- reg = QCA955X_RESET_REG_RESET_MODULE;
- else
---- a/arch/mips/ath79/dev-common.c
-+++ b/arch/mips/ath79/dev-common.c
-@@ -85,6 +85,7 @@ void __init ath79_register_uart(void)
- soc_is_ar724x() ||
- soc_is_ar913x() ||
- soc_is_ar934x() ||
-+ soc_is_qca953x() ||
- soc_is_qca955x()) {
- ath79_uart_data[0].uartclk = uart_clk_rate;
- platform_device_register(&ath79_uart_device);
-@@ -148,6 +149,9 @@ void __init ath79_gpio_init(void)
- } else if (soc_is_ar934x()) {
- ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
- ath79_gpio_pdata.oe_inverted = 1;
-+ } else if (soc_is_qca953x()) {
-+ ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
-+ ath79_gpio_pdata.oe_inverted = 1;
- } else if (soc_is_qca955x()) {
- ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
- ath79_gpio_pdata.oe_inverted = 1;
---- a/arch/mips/ath79/early_printk.c
-+++ b/arch/mips/ath79/early_printk.c
-@@ -116,6 +116,8 @@ static void prom_putchar_init(void)
- case REV_ID_MAJOR_AR9341:
- case REV_ID_MAJOR_AR9342:
- case REV_ID_MAJOR_AR9344:
-+ case REV_ID_MAJOR_QCA9533:
-+ case REV_ID_MAJOR_QCA9533_V2:
- case REV_ID_MAJOR_QCA9556:
- case REV_ID_MAJOR_QCA9558:
- _prom_putchar = prom_putchar_ar71xx;
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void)
- irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
- }
-
-+static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
-+{
-+ u32 status;
-+
-+ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
-+
-+ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
-+ ath79_ddr_wb_flush(3);
-+ generic_handle_irq(ATH79_IP2_IRQ(0));
-+ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
-+ ath79_ddr_wb_flush(4);
-+ generic_handle_irq(ATH79_IP2_IRQ(1));
-+ } else {
-+ spurious_interrupt();
-+ }
-+}
-+
-+static void qca953x_irq_init(void)
-+{
-+ int i;
-+
-+ for (i = ATH79_IP2_IRQ_BASE;
-+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+
-+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
-+}
-+
- static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
- {
- u32 status;
-@@ -143,7 +171,7 @@ void __init arch_init_irq(void)
- soc_is_ar913x() || soc_is_ar933x()) {
- irq_wb_chan2 = 3;
- irq_wb_chan3 = 2;
-- } else if (soc_is_ar934x()) {
-+ } else if (soc_is_ar934x() || soc_is_qca953x()) {
- irq_wb_chan3 = 2;
- }
-
-@@ -154,6 +182,7 @@ void __init arch_init_irq(void)
- else if (soc_is_ar724x() ||
- soc_is_ar933x() ||
- soc_is_ar934x() ||
-+ soc_is_qca953x() ||
- soc_is_qca955x())
- misc_is_ar71xx = false;
- else
-@@ -164,6 +193,8 @@ void __init arch_init_irq(void)
-
- if (soc_is_ar934x())
- ar934x_ip2_irq_init();
-+ else if (soc_is_qca953x())
-+ qca953x_irq_init();
- else if (soc_is_qca955x())
- qca955x_irq_init();
- }
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type
- u32 major;
- u32 minor;
- u32 rev = 0;
-+ u32 ver = 1;
-
- id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
- major = id & REV_ID_MAJOR_MASK;
-@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type
- rev = id & AR934X_REV_ID_REVISION_MASK;
- break;
-
-+ case REV_ID_MAJOR_QCA9533_V2:
-+ ver = 2;
-+ ath79_soc_rev = 2;
-+ /* drop through */
-+
-+ case REV_ID_MAJOR_QCA9533:
-+ ath79_soc = ATH79_SOC_QCA9533;
-+ chip = "9533";
-+ rev = id & QCA953X_REV_ID_REVISION_MASK;
-+ break;
-+
- case REV_ID_MAJOR_QCA9556:
- ath79_soc = ATH79_SOC_QCA9556;
- chip = "9556";
-@@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type
- panic("ath79: unknown SoC, id:0x%08x", id);
- }
-
-- ath79_soc_rev = rev;
-+ if (ver == 1)
-+ ath79_soc_rev = rev;
-
-- if (soc_is_qca955x())
-- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
-- chip, rev);
-+ if (soc_is_qca953x() || soc_is_qca955x())
-+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
-+ chip, ver, rev);
- else
- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
- pr_info("SoC: %s\n", ath79_sys_type);
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -32,6 +32,7 @@ enum ath79_soc_type {
- ATH79_SOC_AR9341,
- ATH79_SOC_AR9342,
- ATH79_SOC_AR9344,
-+ ATH79_SOC_QCA9533,
- ATH79_SOC_QCA9556,
- ATH79_SOC_QCA9558,
- };
-@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
- return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
- }
-
-+static inline int soc_is_qca9533(void)
-+{
-+ return ath79_soc == ATH79_SOC_QCA9533;
-+}
-+
-+static inline int soc_is_qca953x(void)
-+{
-+ return soc_is_qca9533();
-+}
-+
- static inline int soc_is_qca9556(void)
- {
- return ath79_soc == ATH79_SOC_QCA9556;
--- /dev/null
+From d3fa9694bc71338161ae2b9c7ee08b57b8140f93 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Tue, 6 Mar 2018 08:37:43 +0100
+Subject: [PATCH 16/33] MIPS: ath79: get PCIe controller out of reset
+
+The ar724x pci driver expects the PCIe controller to be brought out of
+reset by the bootloader.
+
+At least the AVM Fritz 300E bootloader doesn't take care of releasing
+the different PCIe controller related resets which causes an endless
+hang as soon as either the PCIE Reset register (0x180f0018) or the PCI
+Application Control register (0x180f0000) is read from.
+
+Do the full "PCIE Root Complex Initialization Sequence" if the PCIe
+host controller is still in reset during probing.
+
+The QCA u-boot sleeps 10ms after the PCIE Application Control bit is
+set to ready. It has been shown that 10ms might not be enough time if
+PCIe should be used right after setting the bit. During my tests it
+took up to 20ms till the link was up. Giving the link up to 100ms
+should work for all cases.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -12,14 +12,18 @@
+ #include <linux/irq.h>
+ #include <linux/pci.h>
+ #include <linux/init.h>
++#include <linux/delay.h>
+ #include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+
++#define AR724X_PCI_REG_APP 0x00
+ #define AR724X_PCI_REG_RESET 0x18
+ #define AR724X_PCI_REG_INT_STATUS 0x4c
+ #define AR724X_PCI_REG_INT_MASK 0x50
+
++#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
++
+ #define AR724X_PCI_RESET_LINK_UP BIT(0)
+
+ #define AR724X_PCI_INT_DEV0 BIT(14)
+@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a
+ apc);
+ }
+
++static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
++{
++ u32 ppl, app;
++ int wait = 0;
++
++ /* deassert PCIe host controller and PCIe PHY reset */
++ ath79_device_reset_clear(AR724X_RESET_PCIE);
++ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
++
++ /* remove the reset of the PCIE PLL */
++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++
++ /* deassert bypass for the PCIE PLL */
++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++
++ /* set PCIE Application Control to ready */
++ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
++ app |= AR724X_PCI_APP_LTSSM_ENABLE;
++ __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
++
++ /* wait up to 100ms for PHY link up */
++ do {
++ mdelay(10);
++ wait++;
++ } while (wait < 10 && !ar724x_pci_check_link(apc));
++}
++
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
+ struct ar724x_pci_controller *apc;
+@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf
+ apc->pci_controller.io_resource = &apc->io_res;
+ apc->pci_controller.mem_resource = &apc->mem_res;
+
++ /*
++ * Do the full PCIE Root Complex Initialization Sequence if the PCIe
++ * host controller is in reset.
++ */
++ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
++ ar724x_pci_hw_init(apc);
++
+ apc->link_up = ar724x_pci_check_link(apc);
+ if (!apc->link_up)
+ dev_warn(&pdev->dev, "PCIe link is down\n");
+++ /dev/null
-From 6aeb24b9508bbe91f89cd4eb21d0d7582d971146 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <hackpascal@gmail.com>
-Date: Tue, 6 Mar 2018 08:48:31 +0100
-Subject: [PATCH 17/27] MIPS: ath79: add support for qca956x soc
-
-This patch adds soc support for QCA9561 and TP9343.
-TP9343 is a reduced version of QCA9561, which can be found in TP-LINK routers in China.
-The qca956x_wmac has not yet been supported by ath9k.
-
-tested on TL-WDR6500 and TL-WR882N v1 (Chinese version)
-
-Signed-off-by: Weijie Gao <hackpascal@gmail.com>
----
- arch/mips/ath79/Kconfig | 2 +-
- arch/mips/ath79/clock.c | 96 ++++++++++++++++++++++++++++++++
- arch/mips/ath79/common.c | 4 ++
- arch/mips/ath79/dev-common.c | 7 ++-
- arch/mips/ath79/early_printk.c | 2 +
- arch/mips/ath79/irq.c | 87 ++++++++++++++++++++++++++++-
- arch/mips/ath79/pci.c | 12 ++++
- arch/mips/ath79/setup.c | 17 +++++-
- arch/mips/include/asm/mach-ath79/ath79.h | 22 ++++++++
- 9 files changed, 245 insertions(+), 4 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -119,7 +119,7 @@ config ATH79_DEV_USB
- def_bool n
-
- config ATH79_DEV_WMAC
-- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
-+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
- def_bool n
-
- endif
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -525,6 +525,100 @@ static void __init qca955x_clocks_init(v
- clk_add_alias("uart", NULL, "ref", NULL);
- }
-
-+static void __init qca956x_clocks_init(void)
-+{
-+ unsigned long ref_rate;
-+ unsigned long cpu_rate;
-+ unsigned long ddr_rate;
-+ unsigned long ahb_rate;
-+ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
-+ u32 cpu_pll, ddr_pll;
-+ u32 bootstrap;
-+
-+ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
-+ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
-+ ref_rate = 40 * 1000 * 1000;
-+ else
-+ ref_rate = 25 * 1000 * 1000;
-+
-+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
-+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
-+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
-+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
-+
-+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
-+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
-+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
-+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
-+ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
-+ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
-+ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
-+
-+ cpu_pll = nint * ref_rate / ref_div;
-+ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
-+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
-+ cpu_pll /= (1 << out_div);
-+
-+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
-+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
-+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
-+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
-+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
-+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
-+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
-+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
-+ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
-+ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
-+ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
-+
-+ ddr_pll = nint * ref_rate / ref_div;
-+ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
-+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
-+ ddr_pll /= (1 << out_div);
-+
-+ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
-+
-+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
-+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-+
-+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
-+ cpu_rate = ref_rate;
-+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
-+ cpu_rate = ddr_pll / (postdiv + 1);
-+ else
-+ cpu_rate = cpu_pll / (postdiv + 1);
-+
-+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
-+ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
-+
-+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
-+ ddr_rate = ref_rate;
-+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
-+ ddr_rate = cpu_pll / (postdiv + 1);
-+ else
-+ ddr_rate = ddr_pll / (postdiv + 1);
-+
-+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
-+ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
-+
-+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
-+ ahb_rate = ref_rate;
-+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
-+ ahb_rate = ddr_pll / (postdiv + 1);
-+ else
-+ ahb_rate = cpu_pll / (postdiv + 1);
-+
-+ ath79_add_sys_clkdev("ref", ref_rate);
-+ ath79_add_sys_clkdev("cpu", cpu_rate);
-+ ath79_add_sys_clkdev("ddr", ddr_rate);
-+ ath79_add_sys_clkdev("ahb", ahb_rate);
-+
-+ clk_add_alias("wdt", NULL, "ref", NULL);
-+ clk_add_alias("uart", NULL, "ref", NULL);
-+}
-+
- void __init ath79_clocks_init(void)
- {
- if (soc_is_ar71xx())
-@@ -539,6 +633,8 @@ void __init ath79_clocks_init(void)
- qca953x_clocks_init();
- else if (soc_is_qca955x())
- qca955x_clocks_init();
-+ else if (soc_is_qca956x() || soc_is_tp9343())
-+ qca956x_clocks_init();
- else
- BUG();
- }
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask)
- reg = QCA953X_RESET_REG_RESET_MODULE;
- else if (soc_is_qca955x())
- reg = QCA955X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_qca956x() || soc_is_tp9343())
-+ reg = QCA956X_RESET_REG_RESET_MODULE;
- else
- panic("Reset register not defined for this SOC");
-
-@@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask)
- reg = QCA953X_RESET_REG_RESET_MODULE;
- else if (soc_is_qca955x())
- reg = QCA955X_RESET_REG_RESET_MODULE;
-+ else if (soc_is_qca956x() || soc_is_tp9343())
-+ reg = QCA956X_RESET_REG_RESET_MODULE;
- else
- panic("Reset register not defined for this SOC");
-
---- a/arch/mips/ath79/dev-common.c
-+++ b/arch/mips/ath79/dev-common.c
-@@ -86,7 +86,9 @@ void __init ath79_register_uart(void)
- soc_is_ar913x() ||
- soc_is_ar934x() ||
- soc_is_qca953x() ||
-- soc_is_qca955x()) {
-+ soc_is_qca955x() ||
-+ soc_is_qca956x() ||
-+ soc_is_tp9343()) {
- ath79_uart_data[0].uartclk = uart_clk_rate;
- platform_device_register(&ath79_uart_device);
- } else if (soc_is_ar933x()) {
-@@ -155,6 +157,9 @@ void __init ath79_gpio_init(void)
- } else if (soc_is_qca955x()) {
- ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
- ath79_gpio_pdata.oe_inverted = 1;
-+ } else if (soc_is_qca956x() || soc_is_tp9343()) {
-+ ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT;
-+ ath79_gpio_pdata.oe_inverted = 1;
- } else {
- BUG();
- }
---- a/arch/mips/ath79/early_printk.c
-+++ b/arch/mips/ath79/early_printk.c
-@@ -120,6 +120,8 @@ static void prom_putchar_init(void)
- case REV_ID_MAJOR_QCA9533_V2:
- case REV_ID_MAJOR_QCA9556:
- case REV_ID_MAJOR_QCA9558:
-+ case REV_ID_MAJOR_TP9343:
-+ case REV_ID_MAJOR_QCA956X:
- _prom_putchar = prom_putchar_ar71xx;
- break;
-
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -156,6 +156,87 @@ static void qca955x_irq_init(void)
- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
- }
-
-+static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
-+{
-+ u32 status;
-+
-+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
-+ status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
-+
-+ if (status == 0) {
-+ spurious_interrupt();
-+ return;
-+ }
-+
-+ if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
-+ /* TODO: flush DDR? */
-+ generic_handle_irq(ATH79_IP2_IRQ(0));
-+ }
-+
-+ if (status & QCA956X_EXT_INT_WMAC_ALL) {
-+ /* TODO: flsuh DDR? */
-+ generic_handle_irq(ATH79_IP2_IRQ(1));
-+ }
-+}
-+
-+static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
-+{
-+ u32 status;
-+
-+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
-+ status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
-+ QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
-+
-+ if (status == 0) {
-+ spurious_interrupt();
-+ return;
-+ }
-+
-+ if (status & QCA956X_EXT_INT_USB1) {
-+ /* TODO: flush DDR? */
-+ generic_handle_irq(ATH79_IP3_IRQ(0));
-+ }
-+
-+ if (status & QCA956X_EXT_INT_USB2) {
-+ /* TODO: flush DDR? */
-+ generic_handle_irq(ATH79_IP3_IRQ(1));
-+ }
-+
-+ if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
-+ /* TODO: flush DDR? */
-+ generic_handle_irq(ATH79_IP3_IRQ(2));
-+ }
-+}
-+
-+static void qca956x_enable_timer_cb(void) {
-+ u32 misc;
-+
-+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
-+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
-+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
-+}
-+
-+static void qca956x_irq_init(void)
-+{
-+ int i;
-+
-+ for (i = ATH79_IP2_IRQ_BASE;
-+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+
-+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
-+
-+ for (i = ATH79_IP3_IRQ_BASE;
-+ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
-+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+
-+ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
-+
-+ /* QCA956x timer init workaround has to be applied right before setting
-+ * up the clock. Else, there will be no jiffies */
-+ late_time_init = &qca956x_enable_timer_cb;
-+}
-+
- void __init arch_init_irq(void)
- {
- unsigned irq_wb_chan2 = -1;
-@@ -183,7 +264,9 @@ void __init arch_init_irq(void)
- soc_is_ar933x() ||
- soc_is_ar934x() ||
- soc_is_qca953x() ||
-- soc_is_qca955x())
-+ soc_is_qca955x() ||
-+ soc_is_qca956x() ||
-+ soc_is_tp9343())
- misc_is_ar71xx = false;
- else
- BUG();
-@@ -197,4 +280,6 @@ void __init arch_init_irq(void)
- qca953x_irq_init();
- else if (soc_is_qca955x())
- qca955x_irq_init();
-+ else if (soc_is_qca956x() || soc_is_tp9343())
-+ qca956x_irq_init();
- }
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -82,6 +82,9 @@ int pcibios_map_irq(const struct pci_dev
- } else if (soc_is_qca955x()) {
- ath79_pci_irq_map = qca955x_pci_irq_map;
- ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
-+ } else if (soc_is_qca956x()) {
-+ ath79_pci_irq_map = qca956x_pci_irq_map;
-+ ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
- } else {
- pr_crit("pci %s: invalid irq map\n",
- pci_name((struct pci_dev *) dev));
-@@ -261,6 +264,15 @@ int __init ath79_register_pci(void)
- QCA955X_PCI_MEM_SIZE,
- 1,
- ATH79_IP3_IRQ(2));
-+ } else if (soc_is_qca956x()) {
-+ pdev = ath79_register_pci_ar724x(0,
-+ QCA956X_PCI_CFG_BASE1,
-+ QCA956X_PCI_CTRL_BASE1,
-+ QCA956X_PCI_CRP_BASE1,
-+ QCA956X_PCI_MEM_BASE1,
-+ QCA956X_PCI_MEM_SIZE,
-+ 1,
-+ ATH79_IP3_IRQ(2));
- } else {
- /* No PCI support */
- return -ENODEV;
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
- rev = id & QCA955X_REV_ID_REVISION_MASK;
- break;
-
-+ case REV_ID_MAJOR_QCA956X:
-+ ath79_soc = ATH79_SOC_QCA956X;
-+ chip = "956X";
-+ rev = id & QCA956X_REV_ID_REVISION_MASK;
-+ break;
-+
-+ case REV_ID_MAJOR_TP9343:
-+ ath79_soc = ATH79_SOC_TP9343;
-+ chip = "9343";
-+ rev = id & QCA956X_REV_ID_REVISION_MASK;
-+ break;
-+
- default:
- panic("ath79: unknown SoC, id:0x%08x", id);
- }
-@@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
- if (ver == 1)
- ath79_soc_rev = rev;
-
-- if (soc_is_qca953x() || soc_is_qca955x())
-+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
- chip, ver, rev);
-+ else if (soc_is_tp9343())
-+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
-+ chip, rev);
- else
- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
- pr_info("SoC: %s\n", ath79_sys_type);
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -35,6 +35,8 @@ enum ath79_soc_type {
- ATH79_SOC_QCA9533,
- ATH79_SOC_QCA9556,
- ATH79_SOC_QCA9558,
-+ ATH79_SOC_TP9343,
-+ ATH79_SOC_QCA956X,
- };
-
- extern enum ath79_soc_type ath79_soc;
-@@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
- return soc_is_qca9556() || soc_is_qca9558();
- }
-
-+static inline int soc_is_tp9343(void)
-+{
-+ return ath79_soc == ATH79_SOC_TP9343;
-+}
-+
-+static inline int soc_is_qca9561(void)
-+{
-+ return ath79_soc == ATH79_SOC_QCA956X;
-+}
-+
-+static inline int soc_is_qca9563(void)
-+{
-+ return ath79_soc == ATH79_SOC_QCA956X;
-+}
-+
-+static inline int soc_is_qca956x(void)
-+{
-+ return soc_is_qca9561() || soc_is_qca9563();
-+}
-+
- void ath79_ddr_wb_flush(unsigned int reg);
- void ath79_ddr_set_pci_windows(void);
-
--- /dev/null
+From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Mon, 25 Jun 2018 15:52:10 +0200
+Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc
+
+With the driver being converted from platform_data to pure OF, we need to
+also add some docs.
+
+Cc: Rob Herring <robh+dt@kernel.org>
+Cc: devicetree@vger.kernel.org
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
+@@ -0,0 +1,38 @@
++* Qualcomm Atheros AR7100 PCI express root complex
++
++Required properties:
++- compatible: should contain "qcom,ar7100-pci" to identify the core.
++- reg: Should contain the register ranges as listed in the reg-names property.
++- reg-names: Definition: Must include the following entries
++ - "cfg_base" IO Memory
++- #address-cells: set to <3>
++- #size-cells: set to <2>
++- ranges: ranges for the PCI memory and I/O regions
++- interrupt-map-mask and interrupt-map: standard PCI
++ properties to define the mapping of the PCIe interface to interrupt
++ numbers.
++- #interrupt-cells: set to <1>
++- interrupt-controller: define to enable the builtin IRQ cascade.
++
++Optional properties:
++- interrupt-parent: phandle to the MIPS IRQ controller
++
++* Example for ar7100
++ pcie-controller@180c0000 {
++ compatible = "qca,ar7100-pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0x0>;
++ reg = <0x17010000 0x100>;
++ reg-names = "cfg_base";
++ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
++ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
++ interrupt-parent = <&cpuintc>;
++ interrupts = <2>;
++
++ interrupt-controller;
++ #interrupt-cells = <1>;
++
++ interrupt-map-mask = <0 0 0 1>;
++ interrupt-map = <0 0 0 0 &pcie0 0>;
++ };
--- /dev/null
+From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:07:23 +0200
+Subject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF
+
+With the ath79 target getting converted to pure OF, we can drop all the
+platform data code and add the missing OF bits to the driver. We also add
+a irq domain for the PCI/e controllers cascade, thus making it usable from
+dts files.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++-----------------------
+ 1 file changed, 41 insertions(+), 41 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -18,8 +18,11 @@
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
+ #include <linux/interrupt.h>
++#include <linux/irqchip/chained_irq.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
+
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+@@ -49,12 +52,13 @@
+ #define AR71XX_PCI_IRQ_COUNT 5
+
+ struct ar71xx_pci_controller {
++ struct device_node *np;
+ void __iomem *cfg_base;
+ int irq;
+- int irq_base;
+ struct pci_controller pci_ctrl;
+ struct resource io_res;
+ struct resource mem_res;
++ struct irq_domain *domain;
+ };
+
+ /* Byte lane enable bits */
+@@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = {
+
+ static void ar71xx_pci_irq_handler(struct irq_desc *desc)
+ {
+- struct ar71xx_pci_controller *apc;
+ void __iomem *base = ath79_reset_base;
++ struct irq_chip *chip = irq_desc_get_chip(desc);
++ struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
+ u32 pending;
+
+- apc = irq_desc_get_handler_data(desc);
+-
++ chained_irq_enter(chip, desc);
+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+
+ if (pending & AR71XX_PCI_INT_DEV0)
+- generic_handle_irq(apc->irq_base + 0);
++ generic_handle_irq(irq_linear_revmap(apc->domain, 1));
+
+ else if (pending & AR71XX_PCI_INT_DEV1)
+- generic_handle_irq(apc->irq_base + 1);
++ generic_handle_irq(irq_linear_revmap(apc->domain, 2));
+
+ else if (pending & AR71XX_PCI_INT_DEV2)
+- generic_handle_irq(apc->irq_base + 2);
++ generic_handle_irq(irq_linear_revmap(apc->domain, 3));
+
+ else if (pending & AR71XX_PCI_INT_CORE)
+- generic_handle_irq(apc->irq_base + 4);
++ generic_handle_irq(irq_linear_revmap(apc->domain, 4));
+
+ else
+ spurious_interrupt();
++ chained_irq_exit(chip, desc);
+ }
+
+ static void ar71xx_pci_irq_unmask(struct irq_data *d)
+@@ -261,7 +266,7 @@ static void ar71xx_pci_irq_unmask(struct
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+- irq = d->irq - apc->irq_base;
++ irq = irq_linear_revmap(apc->domain, d->irq);
+
+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+@@ -278,7 +283,7 @@ static void ar71xx_pci_irq_mask(struct i
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+- irq = d->irq - apc->irq_base;
++ irq = irq_linear_revmap(apc->domain, d->irq);
+
+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+@@ -294,24 +299,31 @@ static struct irq_chip ar71xx_pci_irq_ch
+ .irq_mask_ack = ar71xx_pci_irq_mask,
+ };
+
++static int ar71xx_pci_irq_map(struct irq_domain *d,
++ unsigned int irq, irq_hw_number_t hw)
++{
++ struct ar71xx_pci_controller *apc = d->host_data;
++
++ irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
++ irq_set_chip_data(irq, apc);
++
++ return 0;
++}
++
++static const struct irq_domain_ops ar71xx_pci_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = ar71xx_pci_irq_map,
++};
++
+ static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
+ {
+ void __iomem *base = ath79_reset_base;
+- int i;
+
+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
+
+- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
+-
+- apc->irq_base = ATH79_PCI_IRQ_BASE;
+- for (i = apc->irq_base;
+- i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
+- irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+- handle_level_irq);
+- irq_set_chip_data(i, apc);
+- }
+-
++ apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
++ &ar71xx_pci_domain_ops, apc);
+ irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
+ apc);
+ }
+@@ -328,6 +340,11 @@ static void ar71xx_pci_reset(void)
+ mdelay(100);
+ }
+
++static const struct of_device_id ar71xx_pci_ids[] = {
++ { .compatible = "qca,ar7100-pci" },
++ {},
++};
++
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
+ struct ar71xx_pci_controller *apc;
+@@ -348,26 +365,6 @@ static int ar71xx_pci_probe(struct platf
+ if (apc->irq < 0)
+ return -EINVAL;
+
+- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
+- if (!res)
+- return -EINVAL;
+-
+- apc->io_res.parent = res;
+- apc->io_res.name = "PCI IO space";
+- apc->io_res.start = res->start;
+- apc->io_res.end = res->end;
+- apc->io_res.flags = IORESOURCE_IO;
+-
+- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
+- if (!res)
+- return -EINVAL;
+-
+- apc->mem_res.parent = res;
+- apc->mem_res.name = "PCI memory space";
+- apc->mem_res.start = res->start;
+- apc->mem_res.end = res->end;
+- apc->mem_res.flags = IORESOURCE_MEM;
+-
+ ar71xx_pci_reset();
+
+ /* setup COMMAND register */
+@@ -380,9 +377,11 @@ static int ar71xx_pci_probe(struct platf
+
+ ar71xx_pci_irq_init(apc);
+
++ apc->np = pdev->dev.of_node;
+ apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
+ apc->pci_ctrl.mem_resource = &apc->mem_res;
+ apc->pci_ctrl.io_resource = &apc->io_res;
++ pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);
+
+ register_pci_controller(&apc->pci_ctrl);
+
+@@ -393,6 +392,7 @@ static struct platform_driver ar71xx_pci
+ .probe = ar71xx_pci_probe,
+ .driver = {
+ .name = "ar71xx-pci",
++ .of_match_table = of_match_ptr(ar71xx_pci_ids),
+ },
+ };
+
+++ /dev/null
-From 308c2ef9c4f1be2e1cee699042671eb973b51803 Mon Sep 17 00:00:00 2001
-From: Mathias Kresin <dev@kresin.me>
-Date: Tue, 6 Mar 2018 08:37:43 +0100
-Subject: [PATCH 19/27] MIPS: ath79: get PCIe controller out of reset
-
-The ar724x pci driver expects the PCIe controller to be brought out of
-reset by the bootloader.
-
-At least the AVM Fritz 300E bootloader doesn't take care of releasing
-the different PCIe controller related resets which causes an endless
-hang as soon as either the PCIE Reset register (0x180f0018) or the PCI
-Application Control register (0x180f0000) is read from.
-
-Do the full "PCIE Root Complex Initialization Sequence" if the PCIe
-host controller is still in reset during probing.
-
-The QCA u-boot sleeps 10ms after the PCIE Application Control bit is
-set to ready. It has been shown that 10ms might not be enough time if
-PCIe should be used right after setting the bit. During my tests it
-took up to 20ms till the link was up. Giving the link up to 100ms
-should work for all cases.
-
-Signed-off-by: Mathias Kresin <dev@kresin.me>
----
- arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 42 insertions(+)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -12,14 +12,18 @@
- #include <linux/irq.h>
- #include <linux/pci.h>
- #include <linux/init.h>
-+#include <linux/delay.h>
- #include <linux/platform_device.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
-
-+#define AR724X_PCI_REG_APP 0x00
- #define AR724X_PCI_REG_RESET 0x18
- #define AR724X_PCI_REG_INT_STATUS 0x4c
- #define AR724X_PCI_REG_INT_MASK 0x50
-
-+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
-+
- #define AR724X_PCI_RESET_LINK_UP BIT(0)
-
- #define AR724X_PCI_INT_DEV0 BIT(14)
-@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a
- apc);
- }
-
-+static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
-+{
-+ u32 ppl, app;
-+ int wait = 0;
-+
-+ /* deassert PCIe host controller and PCIe PHY reset */
-+ ath79_device_reset_clear(AR724X_RESET_PCIE);
-+ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
-+
-+ /* remove the reset of the PCIE PLL */
-+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
-+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
-+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
-+
-+ /* deassert bypass for the PCIE PLL */
-+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
-+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
-+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
-+
-+ /* set PCIE Application Control to ready */
-+ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
-+ app |= AR724X_PCI_APP_LTSSM_ENABLE;
-+ __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
-+
-+ /* wait up to 100ms for PHY link up */
-+ do {
-+ mdelay(10);
-+ wait++;
-+ } while (wait < 10 && !ar724x_pci_check_link(apc));
-+}
-+
- static int ar724x_pci_probe(struct platform_device *pdev)
- {
- struct ar724x_pci_controller *apc;
-@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf
- apc->pci_controller.io_resource = &apc->io_res;
- apc->pci_controller.mem_resource = &apc->mem_res;
-
-+ /*
-+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe
-+ * host controller is in reset.
-+ */
-+ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
-+ ar724x_pci_hw_init(apc);
-+
- apc->link_up = ar724x_pci_check_link(apc);
- if (!apc->link_up)
- dev_warn(&pdev->dev, "PCIe link is down\n");
--- /dev/null
+From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Mon, 25 Jun 2018 15:52:02 +0200
+Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc
+
+With the driver being converted from platform_data to pure OF, we need to
+also add some docs.
+
+Cc: Rob Herring <robh+dt@kernel.org>
+Cc: devicetree@vger.kernel.org
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ .../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
+@@ -0,0 +1,42 @@
++* Qualcomm Atheros AR724X PCI express root complex
++
++Required properties:
++- compatible: should contain "qcom,ar7240-pci" to identify the core.
++- reg: Should contain the register ranges as listed in the reg-names property.
++- reg-names: Definition: Must include the following entries
++ - "crp_base" Configuration registers
++ - "ctrl_base" Control registers
++ - "cfg_base" IO Memory
++- #address-cells: set to <3>
++- #size-cells: set to <2>
++- ranges: ranges for the PCI memory and I/O regions
++- interrupt-map-mask and interrupt-map: standard PCI
++ properties to define the mapping of the PCIe interface to interrupt
++ numbers.
++- #interrupt-cells: set to <1>
++- interrupt-parent: phandle to the MIPS IRQ controller
++
++Optional properties:
++- interrupt-controller: define to enable the builtin IRQ cascade.
++
++* Example for qca9557
++ pcie-controller@180c0000 {
++ compatible = "qcom,ar7240-pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0x0>;
++ reg = <0x180c0000 0x1000>,
++ <0x180f0000 0x100>,
++ <0x14000000 0x1000>;
++ reg-names = "crp_base", "ctrl_base", "cfg_base";
++ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000
++ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
++ interrupt-parent = <&intc2>;
++ interrupts = <1>;
++
++ interrupt-controller;
++ #interrupt-cells = <1>;
++
++ interrupt-map-mask = <0 0 0 1>;
++ interrupt-map = <0 0 0 0 &pcie0 0>;
++ };
+++ /dev/null
-From cc5a306038b7956b5736a70696dddaaf3792df76 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 09:22:49 +0100
-Subject: [PATCH 20/27] MIPS: ath79: turn pci-ar71xx driver into a pure OF
- driver
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/pci/pci-ar71xx.c | 81 +++++++++++++++++++++++-----------------------
- 1 file changed, 40 insertions(+), 41 deletions(-)
-
---- a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -18,8 +18,11 @@
- #include <linux/pci.h>
- #include <linux/pci_regs.h>
- #include <linux/interrupt.h>
-+#include <linux/irqchip/chained_irq.h>
- #include <linux/init.h>
- #include <linux/platform_device.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
-@@ -49,12 +52,13 @@
- #define AR71XX_PCI_IRQ_COUNT 5
-
- struct ar71xx_pci_controller {
-+ struct device_node *np;
- void __iomem *cfg_base;
- int irq;
-- int irq_base;
- struct pci_controller pci_ctrl;
- struct resource io_res;
- struct resource mem_res;
-+ struct irq_domain *domain;
- };
-
- /* Byte lane enable bits */
-@@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = {
-
- static void ar71xx_pci_irq_handler(struct irq_desc *desc)
- {
-- struct ar71xx_pci_controller *apc;
- void __iomem *base = ath79_reset_base;
-+ struct irq_chip *chip = irq_desc_get_chip(desc);
-+ struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
- u32 pending;
-
-- apc = irq_desc_get_handler_data(desc);
--
-+ chained_irq_enter(chip, desc);
- pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
- if (pending & AR71XX_PCI_INT_DEV0)
-- generic_handle_irq(apc->irq_base + 0);
-+ generic_handle_irq(irq_linear_revmap(apc->domain, 1));
-
- else if (pending & AR71XX_PCI_INT_DEV1)
-- generic_handle_irq(apc->irq_base + 1);
-+ generic_handle_irq(irq_linear_revmap(apc->domain, 2));
-
- else if (pending & AR71XX_PCI_INT_DEV2)
-- generic_handle_irq(apc->irq_base + 2);
-+ generic_handle_irq(irq_linear_revmap(apc->domain, 3));
-
- else if (pending & AR71XX_PCI_INT_CORE)
-- generic_handle_irq(apc->irq_base + 4);
-+ generic_handle_irq(irq_linear_revmap(apc->domain, 4));
-
- else
- spurious_interrupt();
-+ chained_irq_exit(chip, desc);
- }
-
- static void ar71xx_pci_irq_unmask(struct irq_data *d)
-@@ -261,7 +266,7 @@ static void ar71xx_pci_irq_unmask(struct
- u32 t;
-
- apc = irq_data_get_irq_chip_data(d);
-- irq = d->irq - apc->irq_base;
-+ irq = irq_linear_revmap(apc->domain, d->irq);
-
- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-@@ -278,7 +283,7 @@ static void ar71xx_pci_irq_mask(struct i
- u32 t;
-
- apc = irq_data_get_irq_chip_data(d);
-- irq = d->irq - apc->irq_base;
-+ irq = irq_linear_revmap(apc->domain, d->irq);
-
- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-@@ -294,24 +299,30 @@ static struct irq_chip ar71xx_pci_irq_ch
- .irq_mask_ack = ar71xx_pci_irq_mask,
- };
-
-+static int ar71xx_pci_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ struct ar71xx_pci_controller *apc = d->host_data;
-+
-+ irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
-+ irq_set_chip_data(irq, apc);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops ar71xx_pci_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = ar71xx_pci_irq_map,
-+};
-+
- static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
- {
- void __iomem *base = ath79_reset_base;
-- int i;
-
- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
-
-- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
--
-- apc->irq_base = ATH79_PCI_IRQ_BASE;
-- for (i = apc->irq_base;
-- i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
-- irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
-- handle_level_irq);
-- irq_set_chip_data(i, apc);
-- }
--
-+ apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
-+ &ar71xx_pci_domain_ops, apc);
- irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
- apc);
- }
-@@ -328,6 +339,11 @@ static void ar71xx_pci_reset(void)
- mdelay(100);
- }
-
-+static const struct of_device_id ar71xx_pci_ids[] = {
-+ { .compatible = "qca,ar7100-pci" },
-+ {},
-+};
-+
- static int ar71xx_pci_probe(struct platform_device *pdev)
- {
- struct ar71xx_pci_controller *apc;
-@@ -348,26 +364,6 @@ static int ar71xx_pci_probe(struct platf
- if (apc->irq < 0)
- return -EINVAL;
-
-- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
-- if (!res)
-- return -EINVAL;
--
-- apc->io_res.parent = res;
-- apc->io_res.name = "PCI IO space";
-- apc->io_res.start = res->start;
-- apc->io_res.end = res->end;
-- apc->io_res.flags = IORESOURCE_IO;
--
-- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
-- if (!res)
-- return -EINVAL;
--
-- apc->mem_res.parent = res;
-- apc->mem_res.name = "PCI memory space";
-- apc->mem_res.start = res->start;
-- apc->mem_res.end = res->end;
-- apc->mem_res.flags = IORESOURCE_MEM;
--
- ar71xx_pci_reset();
-
- /* setup COMMAND register */
-@@ -378,11 +374,13 @@ static int ar71xx_pci_probe(struct platf
- /* clear bus errors */
- ar71xx_pci_check_error(apc, 1);
-
-- ar71xx_pci_irq_init(apc);
--
-+ apc->np = pdev->dev.of_node;
- apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
- apc->pci_ctrl.mem_resource = &apc->mem_res;
- apc->pci_ctrl.io_resource = &apc->io_res;
-+ pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);
-+
-+ ar71xx_pci_irq_init(apc);
-
- register_pci_controller(&apc->pci_ctrl);
-
-@@ -393,6 +391,7 @@ static struct platform_driver ar71xx_pci
- .probe = ar71xx_pci_probe,
- .driver = {
- .name = "ar71xx-pci",
-+ .of_match_table = of_match_ptr(ar71xx_pci_ids),
- },
- };
-
--- /dev/null
+From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:07:37 +0200
+Subject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF
+
+With the ath79 target getting converted to pure OF, we can drop all the
+platform data code and add the missing OF bits to the driver. We also add
+a irq domain for the PCI/e controllers cascade, thus making it usable from
+dts files.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------
+ 1 file changed, 42 insertions(+), 46 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -14,8 +14,11 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/platform_device.h>
++#include <linux/irqchip/chained_irq.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
+
+ #define AR724X_PCI_REG_APP 0x00
+ #define AR724X_PCI_REG_RESET 0x18
+@@ -45,17 +48,20 @@ struct ar724x_pci_controller {
+ void __iomem *crp_base;
+
+ int irq;
+- int irq_base;
+
+ bool link_up;
+ bool bar0_is_cached;
+ u32 bar0_value;
+
++ struct device_node *np;
+ struct pci_controller pci_controller;
++ struct irq_domain *domain;
+ struct resource io_res;
+ struct resource mem_res;
+ };
+
++static struct irq_chip ar724x_pci_irq_chip;
++
+ static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+ {
+ u32 reset;
+@@ -231,35 +237,31 @@ static struct pci_ops ar724x_pci_ops = {
+
+ static void ar724x_pci_irq_handler(struct irq_desc *desc)
+ {
+- struct ar724x_pci_controller *apc;
+- void __iomem *base;
++ struct irq_chip *chip = irq_desc_get_chip(desc);
++ struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);
+ u32 pending;
+
+- apc = irq_desc_get_handler_data(desc);
+- base = apc->ctrl_base;
+-
+- pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
+- __raw_readl(base + AR724X_PCI_REG_INT_MASK);
++ chained_irq_enter(chip, desc);
++ pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &
++ __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);
+
+ if (pending & AR724X_PCI_INT_DEV0)
+- generic_handle_irq(apc->irq_base + 0);
+-
++ generic_handle_irq(irq_linear_revmap(apc->domain, 1));
+ else
+ spurious_interrupt();
++ chained_irq_exit(chip, desc);
+ }
+
+ static void ar724x_pci_irq_unmask(struct irq_data *d)
+ {
+ struct ar724x_pci_controller *apc;
+ void __iomem *base;
+- int offset;
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+ base = apc->ctrl_base;
+- offset = apc->irq_base - d->irq;
+
+- switch (offset) {
++ switch (irq_linear_revmap(apc->domain, d->irq)) {
+ case 0:
+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(t | AR724X_PCI_INT_DEV0,
+@@ -273,14 +275,12 @@ static void ar724x_pci_irq_mask(struct i
+ {
+ struct ar724x_pci_controller *apc;
+ void __iomem *base;
+- int offset;
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+ base = apc->ctrl_base;
+- offset = apc->irq_base - d->irq;
+
+- switch (offset) {
++ switch (irq_linear_revmap(apc->domain, d->irq)) {
+ case 0:
+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(t & ~AR724X_PCI_INT_DEV0,
+@@ -305,26 +305,34 @@ static struct irq_chip ar724x_pci_irq_ch
+ .irq_mask_ack = ar724x_pci_irq_mask,
+ };
+
++static int ar724x_pci_irq_map(struct irq_domain *d,
++ unsigned int irq, irq_hw_number_t hw)
++{
++ struct ar724x_pci_controller *apc = d->host_data;
++
++ irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);
++ irq_set_chip_data(irq, apc);
++
++ return 0;
++}
++
++static const struct irq_domain_ops ar724x_pci_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = ar724x_pci_irq_map,
++};
++
+ static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
+ int id)
+ {
+ void __iomem *base;
+- int i;
+
+ base = apc->ctrl_base;
+
+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+
+- apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
+-
+- for (i = apc->irq_base;
+- i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
+- irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+- handle_level_irq);
+- irq_set_chip_data(i, apc);
+- }
+-
++ apc->domain = irq_domain_add_linear(apc->np, 2,
++ &ar724x_pci_domain_ops, apc);
+ irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
+ apc);
+ }
+@@ -394,29 +402,11 @@ static int ar724x_pci_probe(struct platf
+ if (apc->irq < 0)
+ return -EINVAL;
+
+- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
+- if (!res)
+- return -EINVAL;
+-
+- apc->io_res.parent = res;
+- apc->io_res.name = "PCI IO space";
+- apc->io_res.start = res->start;
+- apc->io_res.end = res->end;
+- apc->io_res.flags = IORESOURCE_IO;
+-
+- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
+- if (!res)
+- return -EINVAL;
+-
+- apc->mem_res.parent = res;
+- apc->mem_res.name = "PCI memory space";
+- apc->mem_res.start = res->start;
+- apc->mem_res.end = res->end;
+- apc->mem_res.flags = IORESOURCE_MEM;
+-
++ apc->np = pdev->dev.of_node;
+ apc->pci_controller.pci_ops = &ar724x_pci_ops;
+ apc->pci_controller.io_resource = &apc->io_res;
+ apc->pci_controller.mem_resource = &apc->mem_res;
++ pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);
+
+ /*
+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe
+@@ -438,10 +428,16 @@ static int ar724x_pci_probe(struct platf
+ return 0;
+ }
+
++static const struct of_device_id ar724x_pci_ids[] = {
++ { .compatible = "qcom,ar7240-pci" },
++ {},
++};
++
+ static struct platform_driver ar724x_pci_driver = {
+ .probe = ar724x_pci_probe,
+ .driver = {
+ .name = "ar724x-pci",
++ .of_match_table = of_match_ptr(ar724x_pci_ids),
+ },
+ };
+
--- /dev/null
+From 288a8eb0d41f09fda242e05f8a7bd1f5b3489477 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 6 Mar 2018 13:19:26 +0100
+Subject: [PATCH 21/33] MIPS: ath79: add helpers for setting clocks and expose
+ the ref clock
+
+Preparation for transitioning the legacy clock setup code over
+to OF.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/clock.c | 128 ++++++++++++++++++----------------
+ include/dt-bindings/clock/ath79-clk.h | 3 +-
+ 2 files changed, 68 insertions(+), 63 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -37,20 +37,46 @@ static struct clk_onecell_data clk_data
+ .clk_num = ARRAY_SIZE(clks),
+ };
+
+-static struct clk *__init ath79_add_sys_clkdev(
+- const char *id, unsigned long rate)
++static const char * const clk_names[ATH79_CLK_END] = {
++ [ATH79_CLK_CPU] = "cpu",
++ [ATH79_CLK_DDR] = "ddr",
++ [ATH79_CLK_AHB] = "ahb",
++ [ATH79_CLK_REF] = "ref",
++};
++
++static const char * __init ath79_clk_name(int type)
+ {
+- struct clk *clk;
+- int err;
++ BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
++ return clk_names[type];
++}
+
+- clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
++static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
++{
+ if (IS_ERR(clk))
+- panic("failed to allocate %s clock structure", id);
++ panic("failed to allocate %s clock structure", clk_names[type]);
+
+- err = clk_register_clkdev(clk, id, NULL);
+- if (err)
+- panic("unable to register %s clock device", id);
++ clks[type] = clk;
++ clk_register_clkdev(clk, name, NULL);
++}
+
++static struct clk * __init ath79_set_clk(int type, unsigned long rate)
++{
++ const char *name = ath79_clk_name(type);
++ struct clk *clk;
++
++ clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
++ __ath79_set_clk(type, name, clk);
++ return clk;
++}
++
++static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
++ unsigned int mult, unsigned int div)
++{
++ const char *name = ath79_clk_name(type);
++ struct clk *clk;
++
++ clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
++ __ath79_set_clk(type, name, clk);
+ return clk;
+ }
+
+@@ -80,27 +106,15 @@ static void __init ar71xx_clocks_init(vo
+ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
+ ahb_rate = cpu_rate / div;
+
+- ath79_add_sys_clkdev("ref", ref_rate);
+- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
+- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
+- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
++ ath79_set_clk(ATH79_CLK_REF, ref_rate);
++ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
++ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
++ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+
+ clk_add_alias("wdt", NULL, "ahb", NULL);
+ clk_add_alias("uart", NULL, "ahb", NULL);
+ }
+
+-static struct clk * __init ath79_reg_ffclk(const char *name,
+- const char *parent_name, unsigned int mult, unsigned int div)
+-{
+- struct clk *clk;
+-
+- clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+- if (IS_ERR(clk))
+- panic("failed to allocate %s clock structure", name);
+-
+- return clk;
+-}
+-
+ static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+ {
+ u32 pll;
+@@ -114,24 +128,19 @@ static void __init ar724x_clk_init(struc
+ ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
+ ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
+
+- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
+- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
+- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
++ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
++ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
++ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
+ }
+
+ static void __init ar724x_clocks_init(void)
+ {
+ struct clk *ref_clk;
+
+- ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
++ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
+
+ ar724x_clk_init(ref_clk, ath79_pll_base);
+
+- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
+- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
+- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
+- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
+-
+ clk_add_alias("wdt", NULL, "ahb", NULL);
+ clk_add_alias("uart", NULL, "ahb", NULL);
+ }
+@@ -186,12 +195,12 @@ static void __init ar9330_clk_init(struc
+ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
+ }
+
+- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
+- ninit_mul, ref_div * out_div * cpu_div);
+- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
+- ninit_mul, ref_div * out_div * ddr_div);
+- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
+- ninit_mul, ref_div * out_div * ahb_div);
++ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
++ ref_div * out_div * cpu_div);
++ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
++ ref_div * out_div * ddr_div);
++ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
++ ref_div * out_div * ahb_div);
+ }
+
+ static void __init ar933x_clocks_init(void)
+@@ -206,15 +215,10 @@ static void __init ar933x_clocks_init(vo
+ else
+ ref_rate = (25 * 1000 * 1000);
+
+- ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
++ ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
+
+ ar9330_clk_init(ref_clk, ath79_pll_base);
+
+- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
+- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
+- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
+- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
+-
+ clk_add_alias("wdt", NULL, "ahb", NULL);
+ clk_add_alias("uart", NULL, "ref", NULL);
+ }
+@@ -344,10 +348,10 @@ static void __init ar934x_clocks_init(vo
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+- ath79_add_sys_clkdev("ref", ref_rate);
+- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
+- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
+- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
++ ath79_set_clk(ATH79_CLK_REF, ref_rate);
++ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
++ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
++ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+
+ clk_add_alias("wdt", NULL, "ref", NULL);
+ clk_add_alias("uart", NULL, "ref", NULL);
+@@ -431,10 +435,10 @@ static void __init qca953x_clocks_init(v
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+- ath79_add_sys_clkdev("ref", ref_rate);
+- ath79_add_sys_clkdev("cpu", cpu_rate);
+- ath79_add_sys_clkdev("ddr", ddr_rate);
+- ath79_add_sys_clkdev("ahb", ahb_rate);
++ ath79_set_clk(ATH79_CLK_REF, ref_rate);
++ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
++ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
++ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+
+ clk_add_alias("wdt", NULL, "ref", NULL);
+ clk_add_alias("uart", NULL, "ref", NULL);
+@@ -516,10 +520,10 @@ static void __init qca955x_clocks_init(v
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+- ath79_add_sys_clkdev("ref", ref_rate);
+- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
+- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
+- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
++ ath79_set_clk(ATH79_CLK_REF, ref_rate);
++ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
++ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
++ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+
+ clk_add_alias("wdt", NULL, "ref", NULL);
+ clk_add_alias("uart", NULL, "ref", NULL);
+@@ -620,10 +624,10 @@ static void __init qca956x_clocks_init(v
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+- ath79_add_sys_clkdev("ref", ref_rate);
+- ath79_add_sys_clkdev("cpu", cpu_rate);
+- ath79_add_sys_clkdev("ddr", ddr_rate);
+- ath79_add_sys_clkdev("ahb", ahb_rate);
++ ath79_set_clk(ATH79_CLK_REF, ref_rate);
++ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
++ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
++ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+
+ clk_add_alias("wdt", NULL, "ref", NULL);
+ clk_add_alias("uart", NULL, "ref", NULL);
+--- a/include/dt-bindings/clock/ath79-clk.h
++++ b/include/dt-bindings/clock/ath79-clk.h
+@@ -13,7 +13,8 @@
+ #define ATH79_CLK_CPU 0
+ #define ATH79_CLK_DDR 1
+ #define ATH79_CLK_AHB 2
++#define ATH79_CLK_REF 3
+
+-#define ATH79_CLK_END 3
++#define ATH79_CLK_END 4
+
+ #endif /* __DT_BINDINGS_ATH79_CLK_H */
+++ /dev/null
-From 0e7f36bfd68401e8c42933e7f770f270497bb9a8 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 09:23:25 +0100
-Subject: [PATCH 21/27] MIPS: ath79: turn pci-ar724x driver into a pure OF
- driver
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/pci/pci-ar724x.c | 86 +++++++++++++++++++++-------------------------
- 1 file changed, 40 insertions(+), 46 deletions(-)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -14,8 +14,11 @@
- #include <linux/init.h>
- #include <linux/delay.h>
- #include <linux/platform_device.h>
-+#include <linux/irqchip/chained_irq.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-
- #define AR724X_PCI_REG_APP 0x00
- #define AR724X_PCI_REG_RESET 0x18
-@@ -45,17 +48,20 @@ struct ar724x_pci_controller {
- void __iomem *crp_base;
-
- int irq;
-- int irq_base;
-
- bool link_up;
- bool bar0_is_cached;
- u32 bar0_value;
-
-+ struct device_node *np;
- struct pci_controller pci_controller;
-+ struct irq_domain *domain;
- struct resource io_res;
- struct resource mem_res;
- };
-
-+static struct irq_chip ar724x_pci_irq_chip;
-+
- static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
- {
- u32 reset;
-@@ -231,35 +237,31 @@ static struct pci_ops ar724x_pci_ops = {
-
- static void ar724x_pci_irq_handler(struct irq_desc *desc)
- {
-- struct ar724x_pci_controller *apc;
-- void __iomem *base;
-+ struct irq_chip *chip = irq_desc_get_chip(desc);
-+ struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);
- u32 pending;
-
-- apc = irq_desc_get_handler_data(desc);
-- base = apc->ctrl_base;
--
-- pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
-- __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-+ chained_irq_enter(chip, desc);
-+ pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &
-+ __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);
-
- if (pending & AR724X_PCI_INT_DEV0)
-- generic_handle_irq(apc->irq_base + 0);
--
-+ generic_handle_irq(irq_linear_revmap(apc->domain, 1));
- else
- spurious_interrupt();
-+ chained_irq_exit(chip, desc);
- }
-
- static void ar724x_pci_irq_unmask(struct irq_data *d)
- {
- struct ar724x_pci_controller *apc;
- void __iomem *base;
-- int offset;
- u32 t;
-
- apc = irq_data_get_irq_chip_data(d);
- base = apc->ctrl_base;
-- offset = apc->irq_base - d->irq;
-
-- switch (offset) {
-+ switch (irq_linear_revmap(apc->domain, d->irq)) {
- case 0:
- t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
- __raw_writel(t | AR724X_PCI_INT_DEV0,
-@@ -273,14 +275,12 @@ static void ar724x_pci_irq_mask(struct i
- {
- struct ar724x_pci_controller *apc;
- void __iomem *base;
-- int offset;
- u32 t;
-
- apc = irq_data_get_irq_chip_data(d);
- base = apc->ctrl_base;
-- offset = apc->irq_base - d->irq;
-
-- switch (offset) {
-+ switch (irq_linear_revmap(apc->domain, d->irq)) {
- case 0:
- t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
- __raw_writel(t & ~AR724X_PCI_INT_DEV0,
-@@ -305,26 +305,32 @@ static struct irq_chip ar724x_pci_irq_ch
- .irq_mask_ack = ar724x_pci_irq_mask,
- };
-
-+static int ar724x_pci_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ struct ar724x_pci_controller *apc = d->host_data;
-+
-+ irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);
-+ irq_set_chip_data(irq, apc);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops ar724x_pci_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = ar724x_pci_irq_map,
-+};
-+
- static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
- int id)
- {
- void __iomem *base;
-- int i;
-
- base = apc->ctrl_base;
-
- __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
- __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
-
-- apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
--
-- for (i = apc->irq_base;
-- i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
-- irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
-- handle_level_irq);
-- irq_set_chip_data(i, apc);
-- }
--
-+ apc->domain = irq_domain_add_linear(apc->np, 2, &ar724x_pci_domain_ops, apc);
- irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
- apc);
- }
-@@ -394,29 +400,11 @@ static int ar724x_pci_probe(struct platf
- if (apc->irq < 0)
- return -EINVAL;
-
-- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
-- if (!res)
-- return -EINVAL;
--
-- apc->io_res.parent = res;
-- apc->io_res.name = "PCI IO space";
-- apc->io_res.start = res->start;
-- apc->io_res.end = res->end;
-- apc->io_res.flags = IORESOURCE_IO;
--
-- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
-- if (!res)
-- return -EINVAL;
--
-- apc->mem_res.parent = res;
-- apc->mem_res.name = "PCI memory space";
-- apc->mem_res.start = res->start;
-- apc->mem_res.end = res->end;
-- apc->mem_res.flags = IORESOURCE_MEM;
--
-+ apc->np = pdev->dev.of_node;
- apc->pci_controller.pci_ops = &ar724x_pci_ops;
- apc->pci_controller.io_resource = &apc->io_res;
- apc->pci_controller.mem_resource = &apc->mem_res;
-+ pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);
-
- /*
- * Do the full PCIE Root Complex Initialization Sequence if the PCIe
-@@ -438,10 +426,16 @@ static int ar724x_pci_probe(struct platf
- return 0;
- }
-
-+static const struct of_device_id ar724x_pci_ids[] = {
-+ { .compatible = "qcom,ar7240-pci" },
-+ {},
-+};
-+
- static struct platform_driver ar724x_pci_driver = {
- .probe = ar724x_pci_probe,
- .driver = {
- .name = "ar724x-pci",
-+ .of_match_table = of_match_ptr(ar724x_pci_ids),
- },
- };
-
+++ /dev/null
-From f4128f3224df2309262ef8d1275d928717ebefd0 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 09:21:46 +0100
-Subject: [PATCH 22/27] MIPS: ath79: drop pci.c
-
-This patch drops pci.c fromt he ath79 folder and moves the the pcibios
-callbacks to a new fixup file.
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/ath79/Makefile | 1 -
- arch/mips/ath79/pci.c | 285 --------------------------------------------
- arch/mips/pci/Makefile | 1 +
- arch/mips/pci/fixup-ath79.c | 21 ++++
- 4 files changed, 22 insertions(+), 286 deletions(-)
- delete mode 100644 arch/mips/ath79/pci.c
- create mode 100644 arch/mips/pci/fixup-ath79.c
-
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -11,7 +11,6 @@
- obj-y := prom.o setup.o irq.o common.o clock.o
-
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
--obj-$(CONFIG_PCI) += pci.o
-
- #
- # Devices
---- a/arch/mips/ath79/pci.c
-+++ /dev/null
-@@ -1,285 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X specific PCI setup code
-- *
-- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * Parts of this file are based on Atheros' 2.6.15 BSP
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/pci.h>
--#include <linux/resource.h>
--#include <linux/platform_device.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/irq.h>
--#include "pci.h"
--
--static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
--static const struct ath79_pci_irq *ath79_pci_irq_map;
--static unsigned ath79_pci_nr_irqs;
--
--static const struct ath79_pci_irq ar71xx_pci_irq_map[] = {
-- {
-- .slot = 17,
-- .pin = 1,
-- .irq = ATH79_PCI_IRQ(0),
-- }, {
-- .slot = 18,
-- .pin = 1,
-- .irq = ATH79_PCI_IRQ(1),
-- }, {
-- .slot = 19,
-- .pin = 1,
-- .irq = ATH79_PCI_IRQ(2),
-- }
--};
--
--static const struct ath79_pci_irq ar724x_pci_irq_map[] = {
-- {
-- .slot = 0,
-- .pin = 1,
-- .irq = ATH79_PCI_IRQ(0),
-- }
--};
--
--static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
-- {
-- .bus = 0,
-- .slot = 0,
-- .pin = 1,
-- .irq = ATH79_PCI_IRQ(0),
-- },
-- {
-- .bus = 1,
-- .slot = 0,
-- .pin = 1,
-- .irq = ATH79_PCI_IRQ(1),
-- },
--};
--
--int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
--{
-- int irq = -1;
-- int i;
--
-- if (ath79_pci_nr_irqs == 0 ||
-- ath79_pci_irq_map == NULL) {
-- if (soc_is_ar71xx()) {
-- ath79_pci_irq_map = ar71xx_pci_irq_map;
-- ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
-- } else if (soc_is_ar724x() ||
-- soc_is_ar9342() ||
-- soc_is_ar9344()) {
-- ath79_pci_irq_map = ar724x_pci_irq_map;
-- ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
-- } else if (soc_is_qca955x()) {
-- ath79_pci_irq_map = qca955x_pci_irq_map;
-- ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
-- } else if (soc_is_qca956x()) {
-- ath79_pci_irq_map = qca956x_pci_irq_map;
-- ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
-- } else {
-- pr_crit("pci %s: invalid irq map\n",
-- pci_name((struct pci_dev *) dev));
-- return irq;
-- }
-- }
--
-- for (i = 0; i < ath79_pci_nr_irqs; i++) {
-- const struct ath79_pci_irq *entry;
--
-- entry = &ath79_pci_irq_map[i];
-- if (entry->bus == dev->bus->number &&
-- entry->slot == slot &&
-- entry->pin == pin) {
-- irq = entry->irq;
-- break;
-- }
-- }
--
-- if (irq < 0)
-- pr_crit("pci %s: no irq found for pin %u\n",
-- pci_name((struct pci_dev *) dev), pin);
-- else
-- pr_info("pci %s: using irq %d for pin %u\n",
-- pci_name((struct pci_dev *) dev), irq, pin);
--
-- return irq;
--}
--
--int pcibios_plat_dev_init(struct pci_dev *dev)
--{
-- if (ath79_pci_plat_dev_init)
-- return ath79_pci_plat_dev_init(dev);
--
-- return 0;
--}
--
--void __init ath79_pci_set_irq_map(unsigned nr_irqs,
-- const struct ath79_pci_irq *map)
--{
-- ath79_pci_nr_irqs = nr_irqs;
-- ath79_pci_irq_map = map;
--}
--
--void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
--{
-- ath79_pci_plat_dev_init = func;
--}
--
--static struct platform_device *
--ath79_register_pci_ar71xx(void)
--{
-- struct platform_device *pdev;
-- struct resource res[4];
--
-- memset(res, 0, sizeof(res));
--
-- res[0].name = "cfg_base";
-- res[0].flags = IORESOURCE_MEM;
-- res[0].start = AR71XX_PCI_CFG_BASE;
-- res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
--
-- res[1].flags = IORESOURCE_IRQ;
-- res[1].start = ATH79_CPU_IRQ(2);
-- res[1].end = ATH79_CPU_IRQ(2);
--
-- res[2].name = "io_base";
-- res[2].flags = IORESOURCE_IO;
-- res[2].start = 0;
-- res[2].end = 0;
--
-- res[3].name = "mem_base";
-- res[3].flags = IORESOURCE_MEM;
-- res[3].start = AR71XX_PCI_MEM_BASE;
-- res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
--
-- pdev = platform_device_register_simple("ar71xx-pci", -1,
-- res, ARRAY_SIZE(res));
-- return pdev;
--}
--
--static struct platform_device *
--ath79_register_pci_ar724x(int id,
-- unsigned long cfg_base,
-- unsigned long ctrl_base,
-- unsigned long crp_base,
-- unsigned long mem_base,
-- unsigned long mem_size,
-- unsigned long io_base,
-- int irq)
--{
-- struct platform_device *pdev;
-- struct resource res[6];
--
-- memset(res, 0, sizeof(res));
--
-- res[0].name = "cfg_base";
-- res[0].flags = IORESOURCE_MEM;
-- res[0].start = cfg_base;
-- res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
--
-- res[1].name = "ctrl_base";
-- res[1].flags = IORESOURCE_MEM;
-- res[1].start = ctrl_base;
-- res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
--
-- res[2].flags = IORESOURCE_IRQ;
-- res[2].start = irq;
-- res[2].end = irq;
--
-- res[3].name = "mem_base";
-- res[3].flags = IORESOURCE_MEM;
-- res[3].start = mem_base;
-- res[3].end = mem_base + mem_size - 1;
--
-- res[4].name = "io_base";
-- res[4].flags = IORESOURCE_IO;
-- res[4].start = io_base;
-- res[4].end = io_base;
--
-- res[5].name = "crp_base";
-- res[5].flags = IORESOURCE_MEM;
-- res[5].start = crp_base;
-- res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
--
-- pdev = platform_device_register_simple("ar724x-pci", id,
-- res, ARRAY_SIZE(res));
-- return pdev;
--}
--
--int __init ath79_register_pci(void)
--{
-- struct platform_device *pdev = NULL;
--
-- if (soc_is_ar71xx()) {
-- pdev = ath79_register_pci_ar71xx();
-- } else if (soc_is_ar724x()) {
-- pdev = ath79_register_pci_ar724x(-1,
-- AR724X_PCI_CFG_BASE,
-- AR724X_PCI_CTRL_BASE,
-- AR724X_PCI_CRP_BASE,
-- AR724X_PCI_MEM_BASE,
-- AR724X_PCI_MEM_SIZE,
-- 0,
-- ATH79_CPU_IRQ(2));
-- } else if (soc_is_ar9342() ||
-- soc_is_ar9344()) {
-- u32 bootstrap;
--
-- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-- if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
-- return -ENODEV;
--
-- pdev = ath79_register_pci_ar724x(-1,
-- AR724X_PCI_CFG_BASE,
-- AR724X_PCI_CTRL_BASE,
-- AR724X_PCI_CRP_BASE,
-- AR724X_PCI_MEM_BASE,
-- AR724X_PCI_MEM_SIZE,
-- 0,
-- ATH79_IP2_IRQ(0));
-- } else if (soc_is_qca9558()) {
-- pdev = ath79_register_pci_ar724x(0,
-- QCA955X_PCI_CFG_BASE0,
-- QCA955X_PCI_CTRL_BASE0,
-- QCA955X_PCI_CRP_BASE0,
-- QCA955X_PCI_MEM_BASE0,
-- QCA955X_PCI_MEM_SIZE,
-- 0,
-- ATH79_IP2_IRQ(0));
--
-- pdev = ath79_register_pci_ar724x(1,
-- QCA955X_PCI_CFG_BASE1,
-- QCA955X_PCI_CTRL_BASE1,
-- QCA955X_PCI_CRP_BASE1,
-- QCA955X_PCI_MEM_BASE1,
-- QCA955X_PCI_MEM_SIZE,
-- 1,
-- ATH79_IP3_IRQ(2));
-- } else if (soc_is_qca956x()) {
-- pdev = ath79_register_pci_ar724x(0,
-- QCA956X_PCI_CFG_BASE1,
-- QCA956X_PCI_CTRL_BASE1,
-- QCA956X_PCI_CRP_BASE1,
-- QCA956X_PCI_MEM_BASE1,
-- QCA956X_PCI_MEM_SIZE,
-- 1,
-- ATH79_IP3_IRQ(2));
-- } else {
-- /* No PCI support */
-- return -ENODEV;
-- }
--
-- if (!pdev)
-- pr_err("unable to register PCI controller device\n");
--
-- return pdev ? 0 : -ENODEV;
--}
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -29,6 +29,7 @@ obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-vir
- #
- # These are still pretty much in the old state, watch, go blind.
- #
-+obj-$(CONFIG_ATH79) += fixup-ath79.o
- obj-$(CONFIG_LASAT) += pci-lasat.o
- obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
- obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
---- /dev/null
-+++ b/arch/mips/pci/fixup-ath79.c
-@@ -0,0 +1,21 @@
-+/*
-+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/pci.h>
-+//#include <linux/of_irq.h>
-+#include <linux/of_pci.h>
-+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ return of_irq_parse_and_map_pci(dev, slot, pin);
-+}
--- /dev/null
+From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 6 Mar 2018 13:22:43 +0100
+Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
+ out of soc init
+
+Preparation for reusing functions for DT
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/clock.c | 38 +++++++++++++++++---------------------
+ 1 file changed, 17 insertions(+), 21 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+- clk_add_alias("wdt", NULL, "ahb", NULL);
+- clk_add_alias("uart", NULL, "ahb", NULL);
+ }
+
+ static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+@@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo
+ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
+
+ ar724x_clk_init(ref_clk, ath79_pll_base);
+-
+- clk_add_alias("wdt", NULL, "ahb", NULL);
+- clk_add_alias("uart", NULL, "ahb", NULL);
+ }
+
+ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+@@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo
+ ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
+
+ ar9330_clk_init(ref_clk, ath79_pll_base);
+-
+- clk_add_alias("wdt", NULL, "ahb", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+ }
+
+ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
+@@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+
+- clk_add_alias("wdt", NULL, "ref", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+-
+ iounmap(dpll_base);
+ }
+
+@@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+- clk_add_alias("wdt", NULL, "ref", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+ }
+
+ static void __init qca955x_clocks_init(void)
+@@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+- clk_add_alias("wdt", NULL, "ref", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+ }
+
+ static void __init qca956x_clocks_init(void)
+@@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+- clk_add_alias("wdt", NULL, "ref", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+ }
+
+ void __init ath79_clocks_init(void)
+ {
++ const char *wdt;
++ const char *uart;
++
+ if (soc_is_ar71xx())
+ ar71xx_clocks_init();
+ else if (soc_is_ar724x() || soc_is_ar913x())
+@@ -651,6 +633,20 @@ void __init ath79_clocks_init(void)
+ qca956x_clocks_init();
+ else
+ BUG();
++
++ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
++ wdt = "ahb";
++ uart = "ahb";
++ } else if (soc_is_ar933x()) {
++ wdt = "ahb";
++ uart = "ref";
++ } else {
++ wdt = "ref";
++ uart = "ref";
++ }
++
++ clk_add_alias("wdt", NULL, wdt, NULL);
++ clk_add_alias("uart", NULL, uart, NULL);
+ }
+
+ unsigned long __init
+++ /dev/null
-From 6e38a86d50dba5cc1da9bfd07969d76dd3ac2dda Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 09:28:13 +0100
-Subject: [PATCH 23/27] MIPS: ath79: drop mach files
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/ath79/Kconfig | 73 -------------------
- arch/mips/ath79/Makefile | 10 ---
- arch/mips/ath79/mach-ap121.c | 92 ------------------------
- arch/mips/ath79/mach-ap136.c | 156 -----------------------------------------
- arch/mips/ath79/mach-ap81.c | 100 --------------------------
- arch/mips/ath79/mach-db120.c | 136 -----------------------------------
- arch/mips/ath79/mach-pb44.c | 128 ---------------------------------
- arch/mips/ath79/mach-ubnt-xm.c | 126 ---------------------------------
- 8 files changed, 821 deletions(-)
- delete mode 100644 arch/mips/ath79/mach-ap121.c
- delete mode 100644 arch/mips/ath79/mach-ap136.c
- delete mode 100644 arch/mips/ath79/mach-ap81.c
- delete mode 100644 arch/mips/ath79/mach-db120.c
- delete mode 100644 arch/mips/ath79/mach-pb44.c
- delete mode 100644 arch/mips/ath79/mach-ubnt-xm.c
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -1,79 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
- if ATH79
-
--menu "Atheros AR71XX/AR724X/AR913X machine selection"
--
--config ATH79_MACH_AP121
-- bool "Atheros AP121 reference board"
-- select SOC_AR933X
-- select ATH79_DEV_GPIO_BUTTONS
-- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-- select ATH79_DEV_USB
-- select ATH79_DEV_WMAC
-- help
-- Say 'Y' here if you want your kernel to support the
-- Atheros AP121 reference board.
--
--config ATH79_MACH_AP136
-- bool "Atheros AP136 reference board"
-- select SOC_QCA955X
-- select ATH79_DEV_GPIO_BUTTONS
-- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-- select ATH79_DEV_USB
-- select ATH79_DEV_WMAC
-- help
-- Say 'Y' here if you want your kernel to support the
-- Atheros AP136 reference board.
--
--config ATH79_MACH_AP81
-- bool "Atheros AP81 reference board"
-- select SOC_AR913X
-- select ATH79_DEV_GPIO_BUTTONS
-- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-- select ATH79_DEV_USB
-- select ATH79_DEV_WMAC
-- help
-- Say 'Y' here if you want your kernel to support the
-- Atheros AP81 reference board.
--
--config ATH79_MACH_DB120
-- bool "Atheros DB120 reference board"
-- select SOC_AR934X
-- select ATH79_DEV_GPIO_BUTTONS
-- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-- select ATH79_DEV_USB
-- select ATH79_DEV_WMAC
-- help
-- Say 'Y' here if you want your kernel to support the
-- Atheros DB120 reference board.
--
--config ATH79_MACH_PB44
-- bool "Atheros PB44 reference board"
-- select SOC_AR71XX
-- select ATH79_DEV_GPIO_BUTTONS
-- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-- select ATH79_DEV_USB
-- help
-- Say 'Y' here if you want your kernel to support the
-- Atheros PB44 reference board.
--
--config ATH79_MACH_UBNT_XM
-- bool "Ubiquiti Networks XM (rev 1.0) board"
-- select SOC_AR724X
-- select ATH79_DEV_GPIO_BUTTONS
-- select ATH79_DEV_LEDS_GPIO
-- select ATH79_DEV_SPI
-- help
-- Say 'Y' here if you want your kernel to support the
-- Ubiquiti Networks XM (rev 1.0) board.
--
--endmenu
--
- config SOC_AR71XX
- select HW_HAS_PCI
- def_bool n
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -21,13 +21,3 @@ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev
- obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
- obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
- obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
--
--#
--# Machines
--#
--obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
--obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
--obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
--obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
--obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
--obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
---- a/arch/mips/ath79/mach-ap121.c
-+++ /dev/null
-@@ -1,92 +0,0 @@
--/*
-- * Atheros AP121 board support
-- *
-- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include "machtypes.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--#include "dev-wmac.h"
--
--#define AP121_GPIO_LED_WLAN 0
--#define AP121_GPIO_LED_USB 1
--
--#define AP121_GPIO_BTN_JUMPSTART 11
--#define AP121_GPIO_BTN_RESET 12
--
--#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
--#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
--
--#define AP121_CAL_DATA_ADDR 0x1fff1000
--
--static struct gpio_led ap121_leds_gpio[] __initdata = {
-- {
-- .name = "ap121:green:usb",
-- .gpio = AP121_GPIO_LED_USB,
-- .active_low = 0,
-- },
-- {
-- .name = "ap121:green:wlan",
-- .gpio = AP121_GPIO_LED_WLAN,
-- .active_low = 0,
-- },
--};
--
--static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
-- {
-- .desc = "jumpstart button",
-- .type = EV_KEY,
-- .code = KEY_WPS_BUTTON,
-- .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
-- .gpio = AP121_GPIO_BTN_JUMPSTART,
-- .active_low = 1,
-- },
-- {
-- .desc = "reset button",
-- .type = EV_KEY,
-- .code = KEY_RESTART,
-- .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
-- .gpio = AP121_GPIO_BTN_RESET,
-- .active_low = 1,
-- }
--};
--
--static struct spi_board_info ap121_spi_info[] = {
-- {
-- .bus_num = 0,
-- .chip_select = 0,
-- .max_speed_hz = 25000000,
-- .modalias = "mx25l1606e",
-- }
--};
--
--static struct ath79_spi_platform_data ap121_spi_data = {
-- .bus_num = 0,
-- .num_chipselect = 1,
--};
--
--static void __init ap121_setup(void)
--{
-- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
--
-- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
-- ap121_leds_gpio);
-- ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
-- ARRAY_SIZE(ap121_gpio_keys),
-- ap121_gpio_keys);
--
-- ath79_register_spi(&ap121_spi_data, ap121_spi_info,
-- ARRAY_SIZE(ap121_spi_info));
-- ath79_register_usb();
-- ath79_register_wmac(cal_data);
--}
--
--MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
-- ap121_setup);
---- a/arch/mips/ath79/mach-ap136.c
-+++ /dev/null
-@@ -1,156 +0,0 @@
--/*
-- * Qualcomm Atheros AP136 reference board support
-- *
-- * Copyright (c) 2012 Qualcomm Atheros
-- * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-- *
-- */
--
--#include <linux/pci.h>
--#include <linux/ath9k_platform.h>
--
--#include "machtypes.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--#include "dev-wmac.h"
--#include "pci.h"
--
--#define AP136_GPIO_LED_STATUS_RED 14
--#define AP136_GPIO_LED_STATUS_GREEN 19
--#define AP136_GPIO_LED_USB 4
--#define AP136_GPIO_LED_WLAN_2G 13
--#define AP136_GPIO_LED_WLAN_5G 12
--#define AP136_GPIO_LED_WPS_RED 15
--#define AP136_GPIO_LED_WPS_GREEN 20
--
--#define AP136_GPIO_BTN_WPS 16
--#define AP136_GPIO_BTN_RFKILL 21
--
--#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
--#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
--
--#define AP136_WMAC_CALDATA_OFFSET 0x1000
--#define AP136_PCIE_CALDATA_OFFSET 0x5000
--
--static struct gpio_led ap136_leds_gpio[] __initdata = {
-- {
-- .name = "qca:green:status",
-- .gpio = AP136_GPIO_LED_STATUS_GREEN,
-- .active_low = 1,
-- },
-- {
-- .name = "qca:red:status",
-- .gpio = AP136_GPIO_LED_STATUS_RED,
-- .active_low = 1,
-- },
-- {
-- .name = "qca:green:wps",
-- .gpio = AP136_GPIO_LED_WPS_GREEN,
-- .active_low = 1,
-- },
-- {
-- .name = "qca:red:wps",
-- .gpio = AP136_GPIO_LED_WPS_RED,
-- .active_low = 1,
-- },
-- {
-- .name = "qca:red:wlan-2g",
-- .gpio = AP136_GPIO_LED_WLAN_2G,
-- .active_low = 1,
-- },
-- {
-- .name = "qca:red:usb",
-- .gpio = AP136_GPIO_LED_USB,
-- .active_low = 1,
-- }
--};
--
--static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
-- {
-- .desc = "WPS button",
-- .type = EV_KEY,
-- .code = KEY_WPS_BUTTON,
-- .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
-- .gpio = AP136_GPIO_BTN_WPS,
-- .active_low = 1,
-- },
-- {
-- .desc = "RFKILL button",
-- .type = EV_KEY,
-- .code = KEY_RFKILL,
-- .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
-- .gpio = AP136_GPIO_BTN_RFKILL,
-- .active_low = 1,
-- },
--};
--
--static struct spi_board_info ap136_spi_info[] = {
-- {
-- .bus_num = 0,
-- .chip_select = 0,
-- .max_speed_hz = 25000000,
-- .modalias = "mx25l6405d",
-- }
--};
--
--static struct ath79_spi_platform_data ap136_spi_data = {
-- .bus_num = 0,
-- .num_chipselect = 1,
--};
--
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data ap136_ath9k_data;
--
--static int ap136_pci_plat_dev_init(struct pci_dev *dev)
--{
-- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
-- dev->dev.platform_data = &ap136_ath9k_data;
--
-- return 0;
--}
--
--static void __init ap136_pci_init(u8 *eeprom)
--{
-- memcpy(ap136_ath9k_data.eeprom_data, eeprom,
-- sizeof(ap136_ath9k_data.eeprom_data));
--
-- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
-- ath79_register_pci();
--}
--#else
--static inline void ap136_pci_init(u8 *eeprom) {}
--#endif /* CONFIG_PCI */
--
--static void __init ap136_setup(void)
--{
-- u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
--
-- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
-- ap136_leds_gpio);
-- ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
-- ARRAY_SIZE(ap136_gpio_keys),
-- ap136_gpio_keys);
-- ath79_register_spi(&ap136_spi_data, ap136_spi_info,
-- ARRAY_SIZE(ap136_spi_info));
-- ath79_register_usb();
-- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
-- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
--}
--
--MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
-- "Atheros AP136-010 reference board",
-- ap136_setup);
---- a/arch/mips/ath79/mach-ap81.c
-+++ /dev/null
-@@ -1,100 +0,0 @@
--/*
-- * Atheros AP81 board support
-- *
-- * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include "machtypes.h"
--#include "dev-wmac.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--
--#define AP81_GPIO_LED_STATUS 1
--#define AP81_GPIO_LED_AOSS 3
--#define AP81_GPIO_LED_WLAN 6
--#define AP81_GPIO_LED_POWER 14
--
--#define AP81_GPIO_BTN_SW4 12
--#define AP81_GPIO_BTN_SW1 21
--
--#define AP81_KEYS_POLL_INTERVAL 20 /* msecs */
--#define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL)
--
--#define AP81_CAL_DATA_ADDR 0x1fff1000
--
--static struct gpio_led ap81_leds_gpio[] __initdata = {
-- {
-- .name = "ap81:green:status",
-- .gpio = AP81_GPIO_LED_STATUS,
-- .active_low = 1,
-- }, {
-- .name = "ap81:amber:aoss",
-- .gpio = AP81_GPIO_LED_AOSS,
-- .active_low = 1,
-- }, {
-- .name = "ap81:green:wlan",
-- .gpio = AP81_GPIO_LED_WLAN,
-- .active_low = 1,
-- }, {
-- .name = "ap81:green:power",
-- .gpio = AP81_GPIO_LED_POWER,
-- .active_low = 1,
-- }
--};
--
--static struct gpio_keys_button ap81_gpio_keys[] __initdata = {
-- {
-- .desc = "sw1",
-- .type = EV_KEY,
-- .code = BTN_0,
-- .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL,
-- .gpio = AP81_GPIO_BTN_SW1,
-- .active_low = 1,
-- } , {
-- .desc = "sw4",
-- .type = EV_KEY,
-- .code = BTN_1,
-- .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL,
-- .gpio = AP81_GPIO_BTN_SW4,
-- .active_low = 1,
-- }
--};
--
--static struct spi_board_info ap81_spi_info[] = {
-- {
-- .bus_num = 0,
-- .chip_select = 0,
-- .max_speed_hz = 25000000,
-- .modalias = "m25p64",
-- }
--};
--
--static struct ath79_spi_platform_data ap81_spi_data = {
-- .bus_num = 0,
-- .num_chipselect = 1,
--};
--
--static void __init ap81_setup(void)
--{
-- u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
--
-- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio),
-- ap81_leds_gpio);
-- ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
-- ARRAY_SIZE(ap81_gpio_keys),
-- ap81_gpio_keys);
-- ath79_register_spi(&ap81_spi_data, ap81_spi_info,
-- ARRAY_SIZE(ap81_spi_info));
-- ath79_register_wmac(cal_data);
-- ath79_register_usb();
--}
--
--MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
-- ap81_setup);
---- a/arch/mips/ath79/mach-db120.c
-+++ /dev/null
-@@ -1,136 +0,0 @@
--/*
-- * Atheros DB120 reference board support
-- *
-- * Copyright (c) 2011 Qualcomm Atheros
-- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-- *
-- */
--
--#include <linux/pci.h>
--#include <linux/ath9k_platform.h>
--
--#include "machtypes.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--#include "dev-wmac.h"
--#include "pci.h"
--
--#define DB120_GPIO_LED_WLAN_5G 12
--#define DB120_GPIO_LED_WLAN_2G 13
--#define DB120_GPIO_LED_STATUS 14
--#define DB120_GPIO_LED_WPS 15
--
--#define DB120_GPIO_BTN_WPS 16
--
--#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
--#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
--
--#define DB120_WMAC_CALDATA_OFFSET 0x1000
--#define DB120_PCIE_CALDATA_OFFSET 0x5000
--
--static struct gpio_led db120_leds_gpio[] __initdata = {
-- {
-- .name = "db120:green:status",
-- .gpio = DB120_GPIO_LED_STATUS,
-- .active_low = 1,
-- },
-- {
-- .name = "db120:green:wps",
-- .gpio = DB120_GPIO_LED_WPS,
-- .active_low = 1,
-- },
-- {
-- .name = "db120:green:wlan-5g",
-- .gpio = DB120_GPIO_LED_WLAN_5G,
-- .active_low = 1,
-- },
-- {
-- .name = "db120:green:wlan-2g",
-- .gpio = DB120_GPIO_LED_WLAN_2G,
-- .active_low = 1,
-- },
--};
--
--static struct gpio_keys_button db120_gpio_keys[] __initdata = {
-- {
-- .desc = "WPS button",
-- .type = EV_KEY,
-- .code = KEY_WPS_BUTTON,
-- .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
-- .gpio = DB120_GPIO_BTN_WPS,
-- .active_low = 1,
-- },
--};
--
--static struct spi_board_info db120_spi_info[] = {
-- {
-- .bus_num = 0,
-- .chip_select = 0,
-- .max_speed_hz = 25000000,
-- .modalias = "s25sl064a",
-- }
--};
--
--static struct ath79_spi_platform_data db120_spi_data = {
-- .bus_num = 0,
-- .num_chipselect = 1,
--};
--
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data db120_ath9k_data;
--
--static int db120_pci_plat_dev_init(struct pci_dev *dev)
--{
-- switch (PCI_SLOT(dev->devfn)) {
-- case 0:
-- dev->dev.platform_data = &db120_ath9k_data;
-- break;
-- }
--
-- return 0;
--}
--
--static void __init db120_pci_init(u8 *eeprom)
--{
-- memcpy(db120_ath9k_data.eeprom_data, eeprom,
-- sizeof(db120_ath9k_data.eeprom_data));
--
-- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
-- ath79_register_pci();
--}
--#else
--static inline void db120_pci_init(u8 *eeprom) {}
--#endif /* CONFIG_PCI */
--
--static void __init db120_setup(void)
--{
-- u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
--
-- ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
-- db120_leds_gpio);
-- ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
-- ARRAY_SIZE(db120_gpio_keys),
-- db120_gpio_keys);
-- ath79_register_spi(&db120_spi_data, db120_spi_info,
-- ARRAY_SIZE(db120_spi_info));
-- ath79_register_usb();
-- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
-- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
--}
--
--MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
-- db120_setup);
---- a/arch/mips/ath79/mach-pb44.c
-+++ /dev/null
-@@ -1,122 +0,0 @@
--/*
-- * Atheros PB44 reference board support
-- *
-- * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/platform_device.h>
--#include <linux/i2c.h>
--#include <linux/i2c-gpio.h>
--#include <linux/platform_data/pcf857x.h>
--
--#include "machtypes.h"
--#include "dev-gpio-buttons.h"
--#include "dev-leds-gpio.h"
--#include "dev-spi.h"
--#include "dev-usb.h"
--#include "pci.h"
--
--#define PB44_GPIO_I2C_SCL 0
--#define PB44_GPIO_I2C_SDA 1
--
--#define PB44_GPIO_EXP_BASE 16
--#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
--#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
--#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
--#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10)
--
--#define PB44_KEYS_POLL_INTERVAL 20 /* msecs */
--#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL)
--
--static struct i2c_gpio_platform_data pb44_i2c_gpio_data = {
-- .sda_pin = PB44_GPIO_I2C_SDA,
-- .scl_pin = PB44_GPIO_I2C_SCL,
--};
--
--static struct platform_device pb44_i2c_gpio_device = {
-- .name = "i2c-gpio",
-- .id = 0,
-- .dev = {
-- .platform_data = &pb44_i2c_gpio_data,
-- }
--};
--
--static struct pcf857x_platform_data pb44_pcf857x_data = {
-- .gpio_base = PB44_GPIO_EXP_BASE,
--};
--
--static struct i2c_board_info pb44_i2c_board_info[] __initdata = {
-- {
-- I2C_BOARD_INFO("pcf8575", 0x20),
-- .platform_data = &pb44_pcf857x_data,
-- },
--};
--
--static struct gpio_led pb44_leds_gpio[] __initdata = {
-- {
-- .name = "pb44:amber:jump1",
-- .gpio = PB44_GPIO_LED_JUMP1,
-- .active_low = 1,
-- }, {
-- .name = "pb44:green:jump2",
-- .gpio = PB44_GPIO_LED_JUMP2,
-- .active_low = 1,
-- },
--};
--
--static struct gpio_keys_button pb44_gpio_keys[] __initdata = {
-- {
-- .desc = "soft_reset",
-- .type = EV_KEY,
-- .code = KEY_RESTART,
-- .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL,
-- .gpio = PB44_GPIO_SW_RESET,
-- .active_low = 1,
-- } , {
-- .desc = "jumpstart",
-- .type = EV_KEY,
-- .code = KEY_WPS_BUTTON,
-- .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL,
-- .gpio = PB44_GPIO_SW_JUMP,
-- .active_low = 1,
-- }
--};
--
--static struct spi_board_info pb44_spi_info[] = {
-- {
-- .bus_num = 0,
-- .chip_select = 0,
-- .max_speed_hz = 25000000,
-- .modalias = "m25p64",
-- },
--};
--
--static struct ath79_spi_platform_data pb44_spi_data = {
-- .bus_num = 0,
-- .num_chipselect = 1,
--};
--
--static void __init pb44_init(void)
--{
-- i2c_register_board_info(0, pb44_i2c_board_info,
-- ARRAY_SIZE(pb44_i2c_board_info));
-- platform_device_register(&pb44_i2c_gpio_device);
--
-- ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio),
-- pb44_leds_gpio);
-- ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL,
-- ARRAY_SIZE(pb44_gpio_keys),
-- pb44_gpio_keys);
-- ath79_register_spi(&pb44_spi_data, pb44_spi_info,
-- ARRAY_SIZE(pb44_spi_info));
-- ath79_register_usb();
-- ath79_register_pci();
--}
--
--MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
-- pb44_init);
--- /dev/null
+From 6350b2c36c522fecbc91a80b63f49319dafd2a72 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 6 Mar 2018 13:23:20 +0100
+Subject: [PATCH 23/33] MIPS: ath79: pass PLL base to clock init functions
+
+Preparation for passing the mapped base via DT
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/clock.c | 60 ++++++++++++++++++++++++-------------------------
+ 1 file changed, 30 insertions(+), 30 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -80,7 +80,7 @@ static struct clk * __init ath79_set_ff_
+ return clk;
+ }
+
+-static void __init ar71xx_clocks_init(void)
++static void __init ar71xx_clocks_init(void __iomem *pll_base)
+ {
+ unsigned long ref_rate;
+ unsigned long cpu_rate;
+@@ -92,7 +92,7 @@ static void __init ar71xx_clocks_init(vo
+
+ ref_rate = AR71XX_BASE_FREQ;
+
+- pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
++ pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
+
+ div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
+ freq = div * ref_rate;
+@@ -130,13 +130,13 @@ static void __init ar724x_clk_init(struc
+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
+ }
+
+-static void __init ar724x_clocks_init(void)
++static void __init ar724x_clocks_init(void __iomem *pll_base)
+ {
+ struct clk *ref_clk;
+
+ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
+
+- ar724x_clk_init(ref_clk, ath79_pll_base);
++ ar724x_clk_init(ref_clk, pll_base);
+ }
+
+ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+@@ -197,7 +197,7 @@ static void __init ar9330_clk_init(struc
+ ref_div * out_div * ahb_div);
+ }
+
+-static void __init ar933x_clocks_init(void)
++static void __init ar933x_clocks_init(void __iomem *pll_base)
+ {
+ struct clk *ref_clk;
+ unsigned long ref_rate;
+@@ -234,7 +234,7 @@ static u32 __init ar934x_get_pll_freq(u3
+ return ret;
+ }
+
+-static void __init ar934x_clocks_init(void)
++static void __init ar934x_clocks_init(void __iomem *pll_base)
+ {
+ unsigned long ref_rate;
+ unsigned long cpu_rate;
+@@ -265,7 +265,7 @@ static void __init ar934x_clocks_init(vo
+ AR934X_SRIF_DPLL1_REFDIV_MASK;
+ frac = 1 << 18;
+ } else {
+- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
++ pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+@@ -292,7 +292,7 @@ static void __init ar934x_clocks_init(vo
+ AR934X_SRIF_DPLL1_REFDIV_MASK;
+ frac = 1 << 18;
+ } else {
+- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
++ pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
+ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+@@ -307,7 +307,7 @@ static void __init ar934x_clocks_init(vo
+ ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
+ nfrac, frac, out_div);
+
+- clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
++ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+
+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
+@@ -347,7 +347,7 @@ static void __init ar934x_clocks_init(vo
+ iounmap(dpll_base);
+ }
+
+-static void __init qca953x_clocks_init(void)
++static void __init qca953x_clocks_init(void __iomem *pll_base)
+ {
+ unsigned long ref_rate;
+ unsigned long cpu_rate;
+@@ -363,7 +363,7 @@ static void __init qca953x_clocks_init(v
+ else
+ ref_rate = 25 * 1000 * 1000;
+
+- pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
++ pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+@@ -377,7 +377,7 @@ static void __init qca953x_clocks_init(v
+ cpu_pll += frac * (ref_rate >> 6) / ref_div;
+ cpu_pll /= (1 << out_div);
+
+- pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
++ pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+@@ -391,7 +391,7 @@ static void __init qca953x_clocks_init(v
+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
+ ddr_pll /= (1 << out_div);
+
+- clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
++ clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
+
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+@@ -429,7 +429,7 @@ static void __init qca953x_clocks_init(v
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+ }
+
+-static void __init qca955x_clocks_init(void)
++static void __init qca955x_clocks_init(void __iomem *pll_base)
+ {
+ unsigned long ref_rate;
+ unsigned long cpu_rate;
+@@ -445,7 +445,7 @@ static void __init qca955x_clocks_init(v
+ else
+ ref_rate = 25 * 1000 * 1000;
+
+- pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
++ pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+@@ -459,7 +459,7 @@ static void __init qca955x_clocks_init(v
+ cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
+ cpu_pll /= (1 << out_div);
+
+- pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
++ pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
+ out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+@@ -473,7 +473,7 @@ static void __init qca955x_clocks_init(v
+ ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
+ ddr_pll /= (1 << out_div);
+
+- clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
++ clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
+
+ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+@@ -511,7 +511,7 @@ static void __init qca955x_clocks_init(v
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+ }
+
+-static void __init qca956x_clocks_init(void)
++static void __init qca956x_clocks_init(void __iomem *pll_base)
+ {
+ unsigned long ref_rate;
+ unsigned long cpu_rate;
+@@ -537,13 +537,13 @@ static void __init qca956x_clocks_init(v
+ else
+ ref_rate = 25 * 1000 * 1000;
+
+- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
++ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
+
+- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
++ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
+@@ -556,12 +556,12 @@ static void __init qca956x_clocks_init(v
+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
+ cpu_pll /= (1 << out_div);
+
+- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
++ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
+- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
++ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
+@@ -574,7 +574,7 @@ static void __init qca956x_clocks_init(v
+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
+ ddr_pll /= (1 << out_div);
+
+- clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
++ clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
+
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+@@ -618,19 +618,19 @@ void __init ath79_clocks_init(void)
+ const char *uart;
+
+ if (soc_is_ar71xx())
+- ar71xx_clocks_init();
++ ar71xx_clocks_init(ath79_pll_base);
+ else if (soc_is_ar724x() || soc_is_ar913x())
+- ar724x_clocks_init();
++ ar724x_clocks_init(ath79_pll_base);
+ else if (soc_is_ar933x())
+- ar933x_clocks_init();
++ ar933x_clocks_init(ath79_pll_base);
+ else if (soc_is_ar934x())
+- ar934x_clocks_init();
++ ar934x_clocks_init(ath79_pll_base);
+ else if (soc_is_qca953x())
+- qca953x_clocks_init();
++ qca953x_clocks_init(ath79_pll_base);
+ else if (soc_is_qca955x())
+- qca955x_clocks_init();
++ qca955x_clocks_init(ath79_pll_base);
+ else if (soc_is_qca956x() || soc_is_tp9343())
+- qca956x_clocks_init();
++ qca956x_clocks_init(ath79_pll_base);
+ else
+ BUG();
+
+++ /dev/null
-From 4267880319bc1a2270d352e0ded6d6386242a7ef Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 12 Aug 2014 20:49:27 +0200
-Subject: [PATCH 24/53] GPIO: add named gpio exports
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
- drivers/gpio/gpiolib-sysfs.c | 10 +++++-
- include/asm-generic/gpio.h | 6 ++++
- include/linux/gpio/consumer.h | 8 +++++
- 4 files changed, 91 insertions(+), 1 deletion(-)
-
---- a/drivers/gpio/gpiolib-of.c
-+++ b/drivers/gpio/gpiolib-of.c
-@@ -23,6 +23,8 @@
- #include <linux/pinctrl/pinctrl.h>
- #include <linux/slab.h>
- #include <linux/gpio/machine.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-
- #include "gpiolib.h"
-
-@@ -506,3 +508,68 @@ void of_gpiochip_remove(struct gpio_chip
- gpiochip_remove_pin_ranges(chip);
- of_node_put(chip->of_node);
- }
-+
-+static struct of_device_id gpio_export_ids[] = {
-+ { .compatible = "gpio-export" },
-+ { /* sentinel */ }
-+};
-+
-+static int of_gpio_export_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct device_node *cnp;
-+ u32 val;
-+ int nb = 0;
-+
-+ for_each_child_of_node(np, cnp) {
-+ const char *name = NULL;
-+ int gpio;
-+ bool dmc;
-+ int max_gpio = 1;
-+ int i;
-+
-+ of_property_read_string(cnp, "gpio-export,name", &name);
-+
-+ if (!name)
-+ max_gpio = of_gpio_count(cnp);
-+
-+ for (i = 0; i < max_gpio; i++) {
-+ unsigned flags = 0;
-+ enum of_gpio_flags of_flags;
-+
-+ gpio = of_get_gpio_flags(cnp, i, &of_flags);
-+ if (!gpio_is_valid(gpio))
-+ return gpio;
-+
-+ if (of_flags == OF_GPIO_ACTIVE_LOW)
-+ flags |= GPIOF_ACTIVE_LOW;
-+
-+ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
-+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
-+ else
-+ flags |= GPIOF_IN;
-+
-+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
-+ continue;
-+
-+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
-+ gpio_export_with_name(gpio, dmc, name);
-+ nb++;
-+ }
-+ }
-+
-+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver gpio_export_driver = {
-+ .driver = {
-+ .name = "gpio-export",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(gpio_export_ids),
-+ },
-+ .probe = of_gpio_export_probe,
-+};
-+
-+module_platform_driver(gpio_export_driver);
---- a/drivers/gpio/gpiolib-sysfs.c
-+++ b/drivers/gpio/gpiolib-sysfs.c
-@@ -553,7 +553,7 @@ static struct class gpio_class = {
- *
- * Returns zero on success, else an error.
- */
--int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
- {
- struct gpio_chip *chip;
- struct gpio_device *gdev;
-@@ -615,6 +615,8 @@ int gpiod_export(struct gpio_desc *desc,
- offset = gpio_chip_hwgpio(desc);
- if (chip->names && chip->names[offset])
- ioname = chip->names[offset];
-+ if (name)
-+ ioname = name;
-
- dev = device_create_with_groups(&gpio_class, &gdev->dev,
- MKDEV(0, 0), data, gpio_groups,
-@@ -636,6 +638,12 @@ err_unlock:
- gpiod_dbg(desc, "%s: status %d\n", __func__, status);
- return status;
- }
-+EXPORT_SYMBOL_GPL(__gpiod_export);
-+
-+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
-+{
-+ return __gpiod_export(desc, direction_may_change, NULL);
-+}
- EXPORT_SYMBOL_GPL(gpiod_export);
-
- static int match_export(struct device *dev, const void *desc)
---- a/include/asm-generic/gpio.h
-+++ b/include/asm-generic/gpio.h
-@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g
- return gpiod_export(gpio_to_desc(gpio), direction_may_change);
- }
-
-+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
-+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
-+{
-+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
-+}
-+
- static inline int gpio_export_link(struct device *dev, const char *name,
- unsigned gpio)
- {
---- a/include/linux/gpio/consumer.h
-+++ b/include/linux/gpio/consumer.h
-@@ -451,6 +451,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_
-
- #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
-
-+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
- int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
- int gpiod_export_link(struct device *dev, const char *name,
- struct gpio_desc *desc);
-@@ -458,6 +459,13 @@ void gpiod_unexport(struct gpio_desc *de
-
- #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
-
-+static inline int _gpiod_export(struct gpio_desc *desc,
-+ bool direction_may_change,
-+ const char *name)
-+{
-+ return -ENOSYS;
-+}
-+
- static inline int gpiod_export(struct gpio_desc *desc,
- bool direction_may_change)
- {
+++ /dev/null
-From c038250c16cdefd6d74ad61309ba84973eceb630 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 09:29:46 +0100
-Subject: [PATCH 24/27] MIPS: ath79: drop pdata helpers
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/ath79/dev-common.c | 168 -------------------------
- arch/mips/ath79/dev-common.h | 18 ---
- arch/mips/ath79/dev-gpio-buttons.c | 56 ---------
- arch/mips/ath79/dev-gpio-buttons.h | 23 ----
- arch/mips/ath79/dev-leds-gpio.c | 54 ---------
- arch/mips/ath79/dev-leds-gpio.h | 21 ----
- arch/mips/ath79/dev-spi.c | 38 ------
- arch/mips/ath79/dev-spi.h | 22 ----
- arch/mips/ath79/dev-usb.c | 242 -------------------------------------
- arch/mips/ath79/dev-usb.h | 17 ---
- arch/mips/ath79/dev-wmac.c | 155 ------------------------
- arch/mips/ath79/dev-wmac.h | 17 ---
- arch/mips/ath79/setup.c | 5 -
- 13 files changed, 836 deletions(-)
- delete mode 100644 arch/mips/ath79/dev-common.c
- delete mode 100644 arch/mips/ath79/dev-common.h
- delete mode 100644 arch/mips/ath79/dev-gpio-buttons.c
- delete mode 100644 arch/mips/ath79/dev-gpio-buttons.h
- delete mode 100644 arch/mips/ath79/dev-leds-gpio.c
- delete mode 100644 arch/mips/ath79/dev-leds-gpio.h
- delete mode 100644 arch/mips/ath79/dev-spi.c
- delete mode 100644 arch/mips/ath79/dev-spi.h
- delete mode 100644 arch/mips/ath79/dev-usb.c
- delete mode 100644 arch/mips/ath79/dev-usb.h
- delete mode 100644 arch/mips/ath79/dev-wmac.c
- delete mode 100644 arch/mips/ath79/dev-wmac.h
-
---- a/arch/mips/ath79/dev-common.c
-+++ /dev/null
-@@ -1,168 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X common devices
-- *
-- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * Parts of this file are based on Atheros' 2.6.15 BSP
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/kernel.h>
--#include <linux/init.h>
--#include <linux/platform_device.h>
--#include <linux/platform_data/gpio-ath79.h>
--#include <linux/serial_8250.h>
--#include <linux/clk.h>
--#include <linux/err.h>
--
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "common.h"
--#include "dev-common.h"
--
--static struct resource ath79_uart_resources[] = {
-- {
-- .start = AR71XX_UART_BASE,
-- .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
-- .flags = IORESOURCE_MEM,
-- },
--};
--
--#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
--static struct plat_serial8250_port ath79_uart_data[] = {
-- {
-- .mapbase = AR71XX_UART_BASE,
-- .irq = ATH79_MISC_IRQ(3),
-- .flags = AR71XX_UART_FLAGS,
-- .iotype = UPIO_MEM32,
-- .regshift = 2,
-- }, {
-- /* terminating entry */
-- }
--};
--
--static struct platform_device ath79_uart_device = {
-- .name = "serial8250",
-- .id = PLAT8250_DEV_PLATFORM,
-- .resource = ath79_uart_resources,
-- .num_resources = ARRAY_SIZE(ath79_uart_resources),
-- .dev = {
-- .platform_data = ath79_uart_data
-- },
--};
--
--static struct resource ar933x_uart_resources[] = {
-- {
-- .start = AR933X_UART_BASE,
-- .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
-- .flags = IORESOURCE_MEM,
-- },
-- {
-- .start = ATH79_MISC_IRQ(3),
-- .end = ATH79_MISC_IRQ(3),
-- .flags = IORESOURCE_IRQ,
-- },
--};
--
--static struct platform_device ar933x_uart_device = {
-- .name = "ar933x-uart",
-- .id = -1,
-- .resource = ar933x_uart_resources,
-- .num_resources = ARRAY_SIZE(ar933x_uart_resources),
--};
--
--void __init ath79_register_uart(void)
--{
-- unsigned long uart_clk_rate;
--
-- uart_clk_rate = ath79_get_sys_clk_rate("uart");
--
-- if (soc_is_ar71xx() ||
-- soc_is_ar724x() ||
-- soc_is_ar913x() ||
-- soc_is_ar934x() ||
-- soc_is_qca953x() ||
-- soc_is_qca955x() ||
-- soc_is_qca956x() ||
-- soc_is_tp9343()) {
-- ath79_uart_data[0].uartclk = uart_clk_rate;
-- platform_device_register(&ath79_uart_device);
-- } else if (soc_is_ar933x()) {
-- platform_device_register(&ar933x_uart_device);
-- } else {
-- BUG();
-- }
--}
--
--void __init ath79_register_wdt(void)
--{
-- struct resource res;
--
-- memset(&res, 0, sizeof(res));
--
-- res.flags = IORESOURCE_MEM;
-- res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL;
-- res.end = res.start + 0x8 - 1;
--
-- platform_device_register_simple("ath79-wdt", -1, &res, 1);
--}
--
--static struct ath79_gpio_platform_data ath79_gpio_pdata;
--
--static struct resource ath79_gpio_resources[] = {
-- {
-- .flags = IORESOURCE_MEM,
-- .start = AR71XX_GPIO_BASE,
-- .end = AR71XX_GPIO_BASE + AR71XX_GPIO_SIZE - 1,
-- },
-- {
-- .start = ATH79_MISC_IRQ(2),
-- .end = ATH79_MISC_IRQ(2),
-- .flags = IORESOURCE_IRQ,
-- },
--};
--
--static struct platform_device ath79_gpio_device = {
-- .name = "ath79-gpio",
-- .id = -1,
-- .resource = ath79_gpio_resources,
-- .num_resources = ARRAY_SIZE(ath79_gpio_resources),
-- .dev = {
-- .platform_data = &ath79_gpio_pdata
-- },
--};
--
--void __init ath79_gpio_init(void)
--{
-- if (soc_is_ar71xx()) {
-- ath79_gpio_pdata.ngpios = AR71XX_GPIO_COUNT;
-- } else if (soc_is_ar7240()) {
-- ath79_gpio_pdata.ngpios = AR7240_GPIO_COUNT;
-- } else if (soc_is_ar7241() || soc_is_ar7242()) {
-- ath79_gpio_pdata.ngpios = AR7241_GPIO_COUNT;
-- } else if (soc_is_ar913x()) {
-- ath79_gpio_pdata.ngpios = AR913X_GPIO_COUNT;
-- } else if (soc_is_ar933x()) {
-- ath79_gpio_pdata.ngpios = AR933X_GPIO_COUNT;
-- } else if (soc_is_ar934x()) {
-- ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
-- ath79_gpio_pdata.oe_inverted = 1;
-- } else if (soc_is_qca953x()) {
-- ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
-- ath79_gpio_pdata.oe_inverted = 1;
-- } else if (soc_is_qca955x()) {
-- ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
-- ath79_gpio_pdata.oe_inverted = 1;
-- } else if (soc_is_qca956x() || soc_is_tp9343()) {
-- ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT;
-- ath79_gpio_pdata.oe_inverted = 1;
-- } else {
-- BUG();
-- }
--
-- platform_device_register(&ath79_gpio_device);
--}
---- a/arch/mips/ath79/dev-common.h
-+++ /dev/null
-@@ -1,18 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X common devices
-- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_COMMON_H
--#define _ATH79_DEV_COMMON_H
--
--void ath79_register_uart(void);
--void ath79_register_wdt(void);
--
--#endif /* _ATH79_DEV_COMMON_H */
---- a/arch/mips/ath79/dev-gpio-buttons.c
-+++ /dev/null
-@@ -1,56 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X GPIO button support
-- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include "linux/init.h"
--#include "linux/slab.h"
--#include <linux/platform_device.h>
--
--#include "dev-gpio-buttons.h"
--
--void __init ath79_register_gpio_keys_polled(int id,
-- unsigned poll_interval,
-- unsigned nbuttons,
-- struct gpio_keys_button *buttons)
--{
-- struct platform_device *pdev;
-- struct gpio_keys_platform_data pdata;
-- struct gpio_keys_button *p;
-- int err;
--
-- p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL);
-- if (!p)
-- return;
--
-- pdev = platform_device_alloc("gpio-keys-polled", id);
-- if (!pdev)
-- goto err_free_buttons;
--
-- memset(&pdata, 0, sizeof(pdata));
-- pdata.poll_interval = poll_interval;
-- pdata.nbuttons = nbuttons;
-- pdata.buttons = p;
--
-- err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
-- if (err)
-- goto err_put_pdev;
--
-- err = platform_device_add(pdev);
-- if (err)
-- goto err_put_pdev;
--
-- return;
--
--err_put_pdev:
-- platform_device_put(pdev);
--
--err_free_buttons:
-- kfree(p);
--}
---- a/arch/mips/ath79/dev-gpio-buttons.h
-+++ /dev/null
-@@ -1,23 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X GPIO button support
-- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_GPIO_BUTTONS_H
--#define _ATH79_DEV_GPIO_BUTTONS_H
--
--#include <linux/input.h>
--#include <linux/gpio_keys.h>
--
--void ath79_register_gpio_keys_polled(int id,
-- unsigned poll_interval,
-- unsigned nbuttons,
-- struct gpio_keys_button *buttons);
--
--#endif /* _ATH79_DEV_GPIO_BUTTONS_H */
---- a/arch/mips/ath79/dev-leds-gpio.c
-+++ /dev/null
-@@ -1,54 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support
-- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/slab.h>
--#include <linux/platform_device.h>
--
--#include "dev-leds-gpio.h"
--
--void __init ath79_register_leds_gpio(int id,
-- unsigned num_leds,
-- struct gpio_led *leds)
--{
-- struct platform_device *pdev;
-- struct gpio_led_platform_data pdata;
-- struct gpio_led *p;
-- int err;
--
-- p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL);
-- if (!p)
-- return;
--
-- pdev = platform_device_alloc("leds-gpio", id);
-- if (!pdev)
-- goto err_free_leds;
--
-- memset(&pdata, 0, sizeof(pdata));
-- pdata.num_leds = num_leds;
-- pdata.leds = p;
--
-- err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
-- if (err)
-- goto err_put_pdev;
--
-- err = platform_device_add(pdev);
-- if (err)
-- goto err_put_pdev;
--
-- return;
--
--err_put_pdev:
-- platform_device_put(pdev);
--
--err_free_leds:
-- kfree(p);
--}
---- a/arch/mips/ath79/dev-leds-gpio.h
-+++ /dev/null
-@@ -1,21 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support
-- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_LEDS_GPIO_H
--#define _ATH79_DEV_LEDS_GPIO_H
--
--#include <linux/leds.h>
--
--void ath79_register_leds_gpio(int id,
-- unsigned num_leds,
-- struct gpio_led *leds);
--
--#endif /* _ATH79_DEV_LEDS_GPIO_H */
---- a/arch/mips/ath79/dev-spi.c
-+++ /dev/null
-@@ -1,38 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X SPI controller device
-- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/platform_device.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "dev-spi.h"
--
--static struct resource ath79_spi_resources[] = {
-- {
-- .start = AR71XX_SPI_BASE,
-- .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
-- .flags = IORESOURCE_MEM,
-- },
--};
--
--static struct platform_device ath79_spi_device = {
-- .name = "ath79-spi",
-- .id = -1,
-- .resource = ath79_spi_resources,
-- .num_resources = ARRAY_SIZE(ath79_spi_resources),
--};
--
--void __init ath79_register_spi(struct ath79_spi_platform_data *pdata,
-- struct spi_board_info const *info,
-- unsigned n)
--{
-- spi_register_board_info(info, n);
-- ath79_spi_device.dev.platform_data = pdata;
-- platform_device_register(&ath79_spi_device);
--}
---- a/arch/mips/ath79/dev-spi.h
-+++ /dev/null
-@@ -1,22 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X SPI controller device
-- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_SPI_H
--#define _ATH79_DEV_SPI_H
--
--#include <linux/spi/spi.h>
--#include <asm/mach-ath79/ath79_spi_platform.h>
--
--void ath79_register_spi(struct ath79_spi_platform_data *pdata,
-- struct spi_board_info const *info,
-- unsigned n);
--
--#endif /* _ATH79_DEV_SPI_H */
---- a/arch/mips/ath79/dev-usb.c
-+++ /dev/null
-@@ -1,242 +0,0 @@
--/*
-- * Atheros AR7XXX/AR9XXX USB Host Controller device
-- *
-- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * Parts of this file are based on Atheros' 2.6.15 BSP
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/kernel.h>
--#include <linux/init.h>
--#include <linux/delay.h>
--#include <linux/irq.h>
--#include <linux/dma-mapping.h>
--#include <linux/platform_device.h>
--#include <linux/usb/ehci_pdriver.h>
--#include <linux/usb/ohci_pdriver.h>
--
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "common.h"
--#include "dev-usb.h"
--
--static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
--
--static struct usb_ohci_pdata ath79_ohci_pdata = {
--};
--
--static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
-- .has_synopsys_hc_bug = 1,
--};
--
--static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
-- .caps_offset = 0x100,
-- .has_tt = 1,
--};
--
--static void __init ath79_usb_register(const char *name, int id,
-- unsigned long base, unsigned long size,
-- int irq, const void *data,
-- size_t data_size)
--{
-- struct resource res[2];
-- struct platform_device *pdev;
--
-- memset(res, 0, sizeof(res));
--
-- res[0].flags = IORESOURCE_MEM;
-- res[0].start = base;
-- res[0].end = base + size - 1;
--
-- res[1].flags = IORESOURCE_IRQ;
-- res[1].start = irq;
-- res[1].end = irq;
--
-- pdev = platform_device_register_resndata(NULL, name, id,
-- res, ARRAY_SIZE(res),
-- data, data_size);
--
-- if (IS_ERR(pdev)) {
-- pr_err("ath79: unable to register USB at %08lx, err=%d\n",
-- base, (int) PTR_ERR(pdev));
-- return;
-- }
--
-- pdev->dev.dma_mask = &ath79_usb_dmamask;
-- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
--}
--
--#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
-- AR71XX_RESET_USB_PHY | \
-- AR71XX_RESET_USB_OHCI_DLL)
--
--static void __init ath79_usb_setup(void)
--{
-- void __iomem *usb_ctrl_base;
--
-- ath79_device_reset_set(AR71XX_USB_RESET_MASK);
-- mdelay(1000);
-- ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
--
-- usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
--
-- /* Turning on the Buff and Desc swap bits */
-- __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
--
-- /* WAR for HW bug. Here it adjusts the duration between two SOFS */
-- __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
--
-- iounmap(usb_ctrl_base);
--
-- mdelay(900);
--
-- ath79_usb_register("ohci-platform", -1,
-- AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
-- ATH79_MISC_IRQ(6),
-- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
--
-- ath79_usb_register("ehci-platform", -1,
-- AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
-- ATH79_CPU_IRQ(3),
-- &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
--}
--
--static void __init ar7240_usb_setup(void)
--{
-- void __iomem *usb_ctrl_base;
--
-- ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
-- ath79_device_reset_set(AR7240_RESET_USB_HOST);
--
-- mdelay(1000);
--
-- ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
-- ath79_device_reset_clear(AR7240_RESET_USB_HOST);
--
-- usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
--
-- /* WAR for HW bug. Here it adjusts the duration between two SOFS */
-- __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
--
-- iounmap(usb_ctrl_base);
--
-- ath79_usb_register("ohci-platform", -1,
-- AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
-- ATH79_CPU_IRQ(3),
-- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
--}
--
--static void __init ar724x_usb_setup(void)
--{
-- ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
-- mdelay(10);
--
-- ath79_device_reset_clear(AR724X_RESET_USB_HOST);
-- mdelay(10);
--
-- ath79_device_reset_clear(AR724X_RESET_USB_PHY);
-- mdelay(10);
--
-- ath79_usb_register("ehci-platform", -1,
-- AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
-- ATH79_CPU_IRQ(3),
-- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--static void __init ar913x_usb_setup(void)
--{
-- ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
-- mdelay(10);
--
-- ath79_device_reset_clear(AR913X_RESET_USB_HOST);
-- mdelay(10);
--
-- ath79_device_reset_clear(AR913X_RESET_USB_PHY);
-- mdelay(10);
--
-- ath79_usb_register("ehci-platform", -1,
-- AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
-- ATH79_CPU_IRQ(3),
-- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--static void __init ar933x_usb_setup(void)
--{
-- ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
-- mdelay(10);
--
-- ath79_device_reset_clear(AR933X_RESET_USB_HOST);
-- mdelay(10);
--
-- ath79_device_reset_clear(AR933X_RESET_USB_PHY);
-- mdelay(10);
--
-- ath79_usb_register("ehci-platform", -1,
-- AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
-- ATH79_CPU_IRQ(3),
-- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--static void __init ar934x_usb_setup(void)
--{
-- u32 bootstrap;
--
-- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
-- return;
--
-- ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
-- udelay(1000);
--
-- ath79_device_reset_clear(AR934X_RESET_USB_PHY);
-- udelay(1000);
--
-- ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
-- udelay(1000);
--
-- ath79_device_reset_clear(AR934X_RESET_USB_HOST);
-- udelay(1000);
--
-- ath79_usb_register("ehci-platform", -1,
-- AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
-- ATH79_CPU_IRQ(3),
-- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--static void __init qca955x_usb_setup(void)
--{
-- ath79_usb_register("ehci-platform", 0,
-- QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
-- ATH79_IP3_IRQ(0),
-- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--
-- ath79_usb_register("ehci-platform", 1,
-- QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
-- ATH79_IP3_IRQ(1),
-- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
--}
--
--void __init ath79_register_usb(void)
--{
-- if (soc_is_ar71xx())
-- ath79_usb_setup();
-- else if (soc_is_ar7240())
-- ar7240_usb_setup();
-- else if (soc_is_ar7241() || soc_is_ar7242())
-- ar724x_usb_setup();
-- else if (soc_is_ar913x())
-- ar913x_usb_setup();
-- else if (soc_is_ar933x())
-- ar933x_usb_setup();
-- else if (soc_is_ar934x())
-- ar934x_usb_setup();
-- else if (soc_is_qca955x())
-- qca955x_usb_setup();
-- else
-- BUG();
--}
---- a/arch/mips/ath79/dev-usb.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X USB Host Controller support
-- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_USB_H
--#define _ATH79_DEV_USB_H
--
--void ath79_register_usb(void);
--
--#endif /* _ATH79_DEV_USB_H */
---- a/arch/mips/ath79/dev-wmac.c
-+++ /dev/null
-@@ -1,155 +0,0 @@
--/*
-- * Atheros AR913X/AR933X SoC built-in WMAC device support
-- *
-- * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
-- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/init.h>
--#include <linux/delay.h>
--#include <linux/irq.h>
--#include <linux/platform_device.h>
--#include <linux/ath9k_platform.h>
--
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "dev-wmac.h"
--
--static struct ath9k_platform_data ath79_wmac_data;
--
--static struct resource ath79_wmac_resources[] = {
-- {
-- /* .start and .end fields are filled dynamically */
-- .flags = IORESOURCE_MEM,
-- }, {
-- /* .start and .end fields are filled dynamically */
-- .flags = IORESOURCE_IRQ,
-- },
--};
--
--static struct platform_device ath79_wmac_device = {
-- .name = "ath9k",
-- .id = -1,
-- .resource = ath79_wmac_resources,
-- .num_resources = ARRAY_SIZE(ath79_wmac_resources),
-- .dev = {
-- .platform_data = &ath79_wmac_data,
-- },
--};
--
--static void __init ar913x_wmac_setup(void)
--{
-- /* reset the WMAC */
-- ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
-- mdelay(10);
--
-- ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
-- mdelay(10);
--
-- ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
-- ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
-- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
-- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
--}
--
--
--static int ar933x_wmac_reset(void)
--{
-- ath79_device_reset_set(AR933X_RESET_WMAC);
-- ath79_device_reset_clear(AR933X_RESET_WMAC);
--
-- return 0;
--}
--
--static int ar933x_r1_get_wmac_revision(void)
--{
-- return ath79_soc_rev;
--}
--
--static void __init ar933x_wmac_setup(void)
--{
-- u32 t;
--
-- ar933x_wmac_reset();
--
-- ath79_wmac_device.name = "ar933x_wmac";
--
-- ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
-- ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
-- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
-- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
--
-- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
-- ath79_wmac_data.is_clk_25mhz = false;
-- else
-- ath79_wmac_data.is_clk_25mhz = true;
--
-- if (ath79_soc_rev == 1)
-- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
--
-- ath79_wmac_data.external_reset = ar933x_wmac_reset;
--}
--
--static void ar934x_wmac_setup(void)
--{
-- u32 t;
--
-- ath79_wmac_device.name = "ar934x_wmac";
--
-- ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
-- ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
-- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
-- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
--
-- t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-- if (t & AR934X_BOOTSTRAP_REF_CLK_40)
-- ath79_wmac_data.is_clk_25mhz = false;
-- else
-- ath79_wmac_data.is_clk_25mhz = true;
--}
--
--static void qca955x_wmac_setup(void)
--{
-- u32 t;
--
-- ath79_wmac_device.name = "qca955x_wmac";
--
-- ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
-- ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
-- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
-- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
--
-- t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
-- if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
-- ath79_wmac_data.is_clk_25mhz = false;
-- else
-- ath79_wmac_data.is_clk_25mhz = true;
--}
--
--void __init ath79_register_wmac(u8 *cal_data)
--{
-- if (soc_is_ar913x())
-- ar913x_wmac_setup();
-- else if (soc_is_ar933x())
-- ar933x_wmac_setup();
-- else if (soc_is_ar934x())
-- ar934x_wmac_setup();
-- else if (soc_is_qca955x())
-- qca955x_wmac_setup();
-- else
-- BUG();
--
-- if (cal_data)
-- memcpy(ath79_wmac_data.eeprom_data, cal_data,
-- sizeof(ath79_wmac_data.eeprom_data));
--
-- platform_device_register(&ath79_wmac_device);
--}
---- a/arch/mips/ath79/dev-wmac.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/*
-- * Atheros AR913X/AR933X SoC built-in WMAC device support
-- *
-- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_DEV_WMAC_H
--#define _ATH79_DEV_WMAC_H
--
--void ath79_register_wmac(u8 *cal_data);
--
--#endif /* _ATH79_DEV_WMAC_H */
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -31,7 +31,6 @@
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include "common.h"
--#include "dev-common.h"
- #include "machtypes.h"
-
- #define ATH79_SYS_TYPE_LEN 64
-@@ -316,10 +315,6 @@ static int __init ath79_setup(void)
- if (mips_machtype == ATH79_MACH_GENERIC_OF)
- return 0;
-
-- ath79_gpio_init();
-- ath79_register_uart();
-- ath79_register_wdt();
--
- mips_machine_setup();
-
- return 0;
--- /dev/null
+From 5fadb2544ed0bb72ddddd846aa303bb9ed2d211c Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 6 Mar 2018 13:24:07 +0100
+Subject: [PATCH 24/33] MIPS: ath79: make specifying the reference clock in DT
+ optional
+
+It can be autodetected for many SoCs using the strapping options.
+If the clock is specified in DT, the autodetected value is ignored
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/clock.c | 84 +++++++++++++++++++++++--------------------------
+ 1 file changed, 40 insertions(+), 44 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_
+ return clk;
+ }
+
++static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
++{
++ struct clk *clk = clks[ATH79_CLK_REF];
++
++ if (clk)
++ rate = clk_get_rate(clk);
++ else
++ clk = ath79_set_clk(ATH79_CLK_REF, rate);
++
++ return rate;
++}
++
+ static void __init ar71xx_clocks_init(void __iomem *pll_base)
+ {
+ unsigned long ref_rate;
+@@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(vo
+ u32 freq;
+ u32 div;
+
+- ref_rate = AR71XX_BASE_FREQ;
++ ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
+
+ pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
+
+@@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(vo
+ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
+ ahb_rate = cpu_rate / div;
+
+- ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+ }
+
+-static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
++static void __init ar724x_clocks_init(void __iomem *pll_base)
+ {
+- u32 pll;
+ u32 mult, div, ddr_div, ahb_div;
++ u32 pll;
++
++ ath79_setup_ref_clk(AR71XX_BASE_FREQ);
+
+ pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
+
+@@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struc
+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
+ }
+
+-static void __init ar724x_clocks_init(void __iomem *pll_base)
+-{
+- struct clk *ref_clk;
+-
+- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
+-
+- ar724x_clk_init(ref_clk, pll_base);
+-}
+-
+-static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
++static void __init ar933x_clocks_init(void __iomem *pll_base)
+ {
++ unsigned long ref_rate;
+ u32 clock_ctrl;
+ u32 ref_div;
+ u32 ninit_mul;
+@@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struc
+ u32 cpu_div;
+ u32 ddr_div;
+ u32 ahb_div;
++ u32 t;
++
++ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
++ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
++ ref_rate = (40 * 1000 * 1000);
++ else
++ ref_rate = (25 * 1000 * 1000);
++
++ ath79_setup_ref_clk(ref_rate);
+
+ clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
+ if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
+@@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struc
+ ref_div * out_div * ahb_div);
+ }
+
+-static void __init ar933x_clocks_init(void __iomem *pll_base)
+-{
+- struct clk *ref_clk;
+- unsigned long ref_rate;
+- u32 t;
+-
+- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+- ref_rate = (40 * 1000 * 1000);
+- else
+- ref_rate = (25 * 1000 * 1000);
+-
+- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
+-
+- ar9330_clk_init(ref_clk, ath79_pll_base);
+-}
+-
+ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
+ u32 frac, u32 out_div)
+ {
+@@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(vo
+ else
+ ref_rate = 25 * 1000 * 1000;
+
++ ref_rate = ath79_setup_ref_clk(ref_rate);
++
+ pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
+ if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
+ out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
+@@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(vo
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+- ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+@@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(v
+ else
+ ref_rate = 25 * 1000 * 1000;
+
++ ref_rate = ath79_setup_ref_clk(ref_rate);
++
+ pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+@@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(v
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+- ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+@@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(v
+ else
+ ref_rate = 25 * 1000 * 1000;
+
++ ref_rate = ath79_setup_ref_clk(ref_rate);
++
+ pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
+@@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(v
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+- ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+@@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(v
+ else
+ ref_rate = 25 * 1000 * 1000;
+
++ ref_rate = ath79_setup_ref_clk(ref_rate);
++
+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
+@@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(v
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+- ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+@@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_
+ void __iomem *pll_base;
+
+ ref_clk = of_clk_get(np, 0);
+- if (IS_ERR(ref_clk)) {
+- pr_err("%pOF: of_clk_get failed\n", np);
+- goto err;
+- }
++ if (!IS_ERR(ref_clk))
++ clks[ATH79_CLK_REF] = ref_clk;
+
+ pll_base = of_iomap(np, 0);
+ if (!pll_base) {
+@@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_
+ }
+
+ if (of_device_is_compatible(np, "qca,ar9130-pll"))
+- ar724x_clk_init(ref_clk, pll_base);
++ ar724x_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,ar9330-pll"))
+- ar9330_clk_init(ref_clk, pll_base);
++ ar933x_clocks_init(pll_base);
+ else {
+ pr_err("%pOF: could not find any appropriate clk_init()\n", np);
+ goto err_iounmap;
+@@ -714,9 +713,6 @@ err_iounmap:
+
+ err_clk:
+ clk_put(ref_clk);
+-
+-err:
+- return;
+ }
+ CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
+ CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
+++ /dev/null
-From 08b9cad7da5d981d595fe6d76e9675f85e23e688 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 09:57:15 +0100
-Subject: [PATCH 25/27] MIPS: ath79: drop irq.c
-
-all IRQ init code will flow via OF based irq chips.
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/ath79/Makefile | 2 +-
- arch/mips/ath79/irq.c | 285 -----------------------------------------------
- arch/mips/ath79/setup.c | 6 +
- 3 files changed, 7 insertions(+), 286 deletions(-)
- delete mode 100644 arch/mips/ath79/irq.c
-
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -8,7 +8,7 @@
- # under the terms of the GNU General Public License version 2 as published
- # by the Free Software Foundation.
-
--obj-y := prom.o setup.o irq.o common.o clock.o
-+obj-y := prom.o setup.o common.o clock.o
-
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-
---- a/arch/mips/ath79/irq.c
-+++ /dev/null
-@@ -1,285 +0,0 @@
--/*
-- * Atheros AR71xx/AR724x/AR913x specific interrupt handling
-- *
-- * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
-- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#include <linux/kernel.h>
--#include <linux/init.h>
--#include <linux/interrupt.h>
--#include <linux/irqchip.h>
--#include <linux/of_irq.h>
--
--#include <asm/irq_cpu.h>
--#include <asm/mipsregs.h>
--
--#include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/ar71xx_regs.h>
--#include "common.h"
--#include "machtypes.h"
--
--
--static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
--{
-- u32 status;
--
-- status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
--
-- if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
-- ath79_ddr_wb_flush(3);
-- generic_handle_irq(ATH79_IP2_IRQ(0));
-- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
-- ath79_ddr_wb_flush(4);
-- generic_handle_irq(ATH79_IP2_IRQ(1));
-- } else {
-- spurious_interrupt();
-- }
--}
--
--static void ar934x_ip2_irq_init(void)
--{
-- int i;
--
-- for (i = ATH79_IP2_IRQ_BASE;
-- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-- irq_set_chip_and_handler(i, &dummy_irq_chip,
-- handle_level_irq);
--
-- irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
--}
--
--static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
--{
-- u32 status;
--
-- status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
--
-- if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
-- ath79_ddr_wb_flush(3);
-- generic_handle_irq(ATH79_IP2_IRQ(0));
-- } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
-- ath79_ddr_wb_flush(4);
-- generic_handle_irq(ATH79_IP2_IRQ(1));
-- } else {
-- spurious_interrupt();
-- }
--}
--
--static void qca953x_irq_init(void)
--{
-- int i;
--
-- for (i = ATH79_IP2_IRQ_BASE;
-- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
--
-- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
--}
--
--static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
--{
-- u32 status;
--
-- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
-- status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
--
-- if (status == 0) {
-- spurious_interrupt();
-- return;
-- }
--
-- if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
-- /* TODO: flush DDR? */
-- generic_handle_irq(ATH79_IP2_IRQ(0));
-- }
--
-- if (status & QCA955X_EXT_INT_WMAC_ALL) {
-- /* TODO: flush DDR? */
-- generic_handle_irq(ATH79_IP2_IRQ(1));
-- }
--}
--
--static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
--{
-- u32 status;
--
-- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
-- status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
-- QCA955X_EXT_INT_USB1 |
-- QCA955X_EXT_INT_USB2;
--
-- if (status == 0) {
-- spurious_interrupt();
-- return;
-- }
--
-- if (status & QCA955X_EXT_INT_USB1) {
-- /* TODO: flush DDR? */
-- generic_handle_irq(ATH79_IP3_IRQ(0));
-- }
--
-- if (status & QCA955X_EXT_INT_USB2) {
-- /* TODO: flush DDR? */
-- generic_handle_irq(ATH79_IP3_IRQ(1));
-- }
--
-- if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
-- /* TODO: flush DDR? */
-- generic_handle_irq(ATH79_IP3_IRQ(2));
-- }
--}
--
--static void qca955x_irq_init(void)
--{
-- int i;
--
-- for (i = ATH79_IP2_IRQ_BASE;
-- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-- irq_set_chip_and_handler(i, &dummy_irq_chip,
-- handle_level_irq);
--
-- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
--
-- for (i = ATH79_IP3_IRQ_BASE;
-- i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
-- irq_set_chip_and_handler(i, &dummy_irq_chip,
-- handle_level_irq);
--
-- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
--}
--
--static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
--{
-- u32 status;
--
-- status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
-- status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
--
-- if (status == 0) {
-- spurious_interrupt();
-- return;
-- }
--
-- if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
-- /* TODO: flush DDR? */
-- generic_handle_irq(ATH79_IP2_IRQ(0));
-- }
--
-- if (status & QCA956X_EXT_INT_WMAC_ALL) {
-- /* TODO: flsuh DDR? */
-- generic_handle_irq(ATH79_IP2_IRQ(1));
-- }
--}
--
--static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
--{
-- u32 status;
--
-- status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
-- status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
-- QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
--
-- if (status == 0) {
-- spurious_interrupt();
-- return;
-- }
--
-- if (status & QCA956X_EXT_INT_USB1) {
-- /* TODO: flush DDR? */
-- generic_handle_irq(ATH79_IP3_IRQ(0));
-- }
--
-- if (status & QCA956X_EXT_INT_USB2) {
-- /* TODO: flush DDR? */
-- generic_handle_irq(ATH79_IP3_IRQ(1));
-- }
--
-- if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
-- /* TODO: flush DDR? */
-- generic_handle_irq(ATH79_IP3_IRQ(2));
-- }
--}
--
--static void qca956x_enable_timer_cb(void) {
-- u32 misc;
--
-- misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
-- misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
-- ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
--}
--
--static void qca956x_irq_init(void)
--{
-- int i;
--
-- for (i = ATH79_IP2_IRQ_BASE;
-- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
--
-- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
--
-- for (i = ATH79_IP3_IRQ_BASE;
-- i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
-- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
--
-- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
--
-- /* QCA956x timer init workaround has to be applied right before setting
-- * up the clock. Else, there will be no jiffies */
-- late_time_init = &qca956x_enable_timer_cb;
--}
--
--void __init arch_init_irq(void)
--{
-- unsigned irq_wb_chan2 = -1;
-- unsigned irq_wb_chan3 = -1;
-- bool misc_is_ar71xx;
--
-- if (mips_machtype == ATH79_MACH_GENERIC_OF) {
-- irqchip_init();
-- return;
-- }
--
-- if (soc_is_ar71xx() || soc_is_ar724x() ||
-- soc_is_ar913x() || soc_is_ar933x()) {
-- irq_wb_chan2 = 3;
-- irq_wb_chan3 = 2;
-- } else if (soc_is_ar934x() || soc_is_qca953x()) {
-- irq_wb_chan3 = 2;
-- }
--
-- ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
--
-- if (soc_is_ar71xx() || soc_is_ar913x())
-- misc_is_ar71xx = true;
-- else if (soc_is_ar724x() ||
-- soc_is_ar933x() ||
-- soc_is_ar934x() ||
-- soc_is_qca953x() ||
-- soc_is_qca955x() ||
-- soc_is_qca956x() ||
-- soc_is_tp9343())
-- misc_is_ar71xx = false;
-- else
-- BUG();
-- ath79_misc_irq_init(
-- ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
-- ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
--
-- if (soc_is_ar934x())
-- ar934x_ip2_irq_init();
-- else if (soc_is_qca953x())
-- qca953x_irq_init();
-- else if (soc_is_qca955x())
-- qca955x_irq_init();
-- else if (soc_is_qca956x() || soc_is_tp9343())
-- qca956x_irq_init();
--}
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -19,6 +19,7 @@
- #include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/of_fdt.h>
-+#include <linux/irqchip.h>
-
- #include <asm/bootinfo.h>
- #include <asm/idle.h>
-@@ -310,6 +311,11 @@ void __init plat_time_init(void)
- mips_hpt_frequency = cpu_clk_rate / 2;
- }
-
-+void __init arch_init_irq(void)
-+{
-+ irqchip_init();
-+}
-+
- static int __init ath79_setup(void)
- {
- if (mips_machtype == ATH79_MACH_GENERIC_OF)
--- /dev/null
+From 6325626de001df98aebe51f3008b1aca05798d19 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 6 Mar 2018 13:26:27 +0100
+Subject: [PATCH 25/33] MIPS: ath79: support setting up clock via DT on all SoC
+ types
+
+Use the same functions as the legacy code
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/clock.c | 39 ++++++++++++++++++++++-----------------
+ 1 file changed, 22 insertions(+), 17 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -669,16 +669,6 @@ ath79_get_sys_clk_rate(const char *id)
+ #ifdef CONFIG_OF
+ static void __init ath79_clocks_init_dt(struct device_node *np)
+ {
+- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+-}
+-
+-CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
+-CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
+-CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
+-CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
+-
+-static void __init ath79_clocks_init_dt_ng(struct device_node *np)
+-{
+ struct clk *ref_clk;
+ void __iomem *pll_base;
+
+@@ -692,14 +682,21 @@ static void __init ath79_clocks_init_dt_
+ goto err_clk;
+ }
+
+- if (of_device_is_compatible(np, "qca,ar9130-pll"))
++ if (of_device_is_compatible(np, "qca,ar7100-pll"))
++ ar71xx_clocks_init(pll_base);
++ else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
++ of_device_is_compatible(np, "qca,ar9130-pll"))
+ ar724x_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,ar9330-pll"))
+ ar933x_clocks_init(pll_base);
+- else {
+- pr_err("%pOF: could not find any appropriate clk_init()\n", np);
+- goto err_iounmap;
+- }
++ else if (of_device_is_compatible(np, "qca,ar9340-pll"))
++ ar934x_clocks_init(pll_base);
++ else if (of_device_is_compatible(np, "qca,qca9530-pll"))
++ qca953x_clocks_init(pll_base);
++ else if (of_device_is_compatible(np, "qca,qca9550-pll"))
++ qca955x_clocks_init(pll_base);
++ else if (of_device_is_compatible(np, "qca,qca9560-pll"))
++ qca956x_clocks_init(pll_base);
+
+ if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
+ pr_err("%pOF: could not register clk provider\n", np);
+@@ -714,6 +711,14 @@ err_iounmap:
+ err_clk:
+ clk_put(ref_clk);
+ }
+-CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
+-CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
++
++CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
++CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
++CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
++CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
++CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
++CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
++CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
++CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
++
+ #endif
--- /dev/null
+From 78538d673801902108797f2c813e70cfbce280c9 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 6 Mar 2018 13:27:28 +0100
+Subject: [PATCH 26/33] MIPS: ath79: export switch MDIO reference clock
+
+On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
+clock. If that feature is not used, it defaults to the main reference
+clock, like on all other SoC.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/clock.c | 8 ++++++++
+ include/dt-bindings/clock/ath79-clk.h | 3 ++-
+ 2 files changed, 10 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
+ [ATH79_CLK_DDR] = "ddr",
+ [ATH79_CLK_AHB] = "ahb",
+ [ATH79_CLK_REF] = "ref",
++ [ATH79_CLK_MDIO] = "mdio",
+ };
+
+ static const char * __init ath79_clk_name(int type)
+@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(vo
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+
++ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
++ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
++ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
++
+ iounmap(dpll_base);
+ }
+
+@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(
+ else if (of_device_is_compatible(np, "qca,qca9560-pll"))
+ qca956x_clocks_init(pll_base);
+
++ if (!clks[ATH79_CLK_MDIO])
++ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
++
+ if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
+ pr_err("%pOF: could not register clk provider\n", np);
+ goto err_iounmap;
+--- a/include/dt-bindings/clock/ath79-clk.h
++++ b/include/dt-bindings/clock/ath79-clk.h
+@@ -14,7 +14,8 @@
+ #define ATH79_CLK_DDR 1
+ #define ATH79_CLK_AHB 2
+ #define ATH79_CLK_REF 3
++#define ATH79_CLK_MDIO 4
+
+-#define ATH79_CLK_END 4
++#define ATH79_CLK_END 5
+
+ #endif /* __DT_BINDINGS_ATH79_CLK_H */
+++ /dev/null
-From deda44895d289a72a235359fc21f8a62ea44dc1c Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 09:33:26 +0100
-Subject: [PATCH 26/27] MIPS: ath79: sanitize Kconfig symbols
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/Kconfig | 2 ++
- arch/mips/ath79/Kconfig | 48 +++++-------------------------------------------
- arch/mips/ath79/Makefile | 10 ----------
- arch/mips/pci/Makefile | 2 +-
- 4 files changed, 8 insertions(+), 54 deletions(-)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -203,6 +203,8 @@ config ATH79
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_MIPS16
- select SYS_SUPPORTS_ZBOOT_UART_PROM
-+ select HW_HAS_PCI
-+ select USB_ARCH_HAS_EHCI
- select USE_OF
- help
- Support for the Atheros AR71XX/AR724X/AR913X SoCs.
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -1,52 +1,14 @@
- # SPDX-License-Identifier: GPL-2.0
- if ATH79
-
--config SOC_AR71XX
-- select HW_HAS_PCI
-- def_bool n
--
--config SOC_AR724X
-- select HW_HAS_PCI
-- select PCI_AR724X if PCI
-- def_bool n
--
--config SOC_AR913X
-- def_bool n
--
--config SOC_AR933X
-- def_bool n
--
--config SOC_AR934X
-- select HW_HAS_PCI
-- select PCI_AR724X if PCI
-- def_bool n
--
--config SOC_QCA953X
-- select USB_ARCH_HAS_EHCI
-- def_bool n
--
--config SOC_QCA955X
-- select HW_HAS_PCI
-- select PCI_AR724X if PCI
-+config PCI_AR71XX
-+ bool "PCI support for AR7100 type SoCs"
-+ depends on PCI
- def_bool n
-
- config PCI_AR724X
-- def_bool n
--
--config ATH79_DEV_GPIO_BUTTONS
-- def_bool n
--
--config ATH79_DEV_LEDS_GPIO
-- def_bool n
--
--config ATH79_DEV_SPI
-- def_bool n
--
--config ATH79_DEV_USB
-- def_bool n
--
--config ATH79_DEV_WMAC
-- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
-+ bool "PCI support for AR724x type SoCs"
-+ depends on PCI
- def_bool n
-
- endif
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -11,13 +11,3 @@
- obj-y := prom.o setup.o common.o clock.o
-
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
--
--#
--# Devices
--#
--obj-y += dev-common.o
--obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
--obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
--obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
--obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
--obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -23,7 +23,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o
- ops-bcm63xx.o
- obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
- obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
--obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
-+obj-$(CONFIG_PCI_AR71XX) += pci-ar71xx.o
- obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
- obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
- #
--- /dev/null
+From 3765b1f79593a0a9098ed15e48074c95403a53ee Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:05:08 +0200
+Subject: [PATCH 27/33] MIPS: ath79: drop legacy IRQ code
+
+With the target now being fully OF based, we can drop the legacy IRQ code.
+All IRQs are now handled via the new irqchip drivers.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/Makefile | 2 +-
+ arch/mips/ath79/irq.c | 169 -------------------------------
+ arch/mips/ath79/setup.c | 6 ++
+ arch/mips/include/asm/mach-ath79/ath79.h | 4 -
+ 4 files changed, 7 insertions(+), 174 deletions(-)
+ delete mode 100644 arch/mips/ath79/irq.c
+
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -8,7 +8,7 @@
+ # under the terms of the GNU General Public License version 2 as published
+ # by the Free Software Foundation.
+
+-obj-y := prom.o setup.o irq.o common.o clock.o
++obj-y := prom.o setup.o common.o clock.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+ obj-$(CONFIG_PCI) += pci.o
+--- a/arch/mips/ath79/irq.c
++++ /dev/null
+@@ -1,169 +0,0 @@
+-/*
+- * Atheros AR71xx/AR724x/AR913x specific interrupt handling
+- *
+- * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/interrupt.h>
+-#include <linux/irqchip.h>
+-#include <linux/of_irq.h>
+-
+-#include <asm/irq_cpu.h>
+-#include <asm/mipsregs.h>
+-
+-#include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/ar71xx_regs.h>
+-#include "common.h"
+-#include "machtypes.h"
+-
+-
+-static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
+-{
+- u32 status;
+-
+- status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
+-
+- if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
+- ath79_ddr_wb_flush(3);
+- generic_handle_irq(ATH79_IP2_IRQ(0));
+- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
+- ath79_ddr_wb_flush(4);
+- generic_handle_irq(ATH79_IP2_IRQ(1));
+- } else {
+- spurious_interrupt();
+- }
+-}
+-
+-static void ar934x_ip2_irq_init(void)
+-{
+- int i;
+-
+- for (i = ATH79_IP2_IRQ_BASE;
+- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+- irq_set_chip_and_handler(i, &dummy_irq_chip,
+- handle_level_irq);
+-
+- irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+-}
+-
+-static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
+-{
+- u32 status;
+-
+- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
+- status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
+-
+- if (status == 0) {
+- spurious_interrupt();
+- return;
+- }
+-
+- if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
+- /* TODO: flush DDR? */
+- generic_handle_irq(ATH79_IP2_IRQ(0));
+- }
+-
+- if (status & QCA955X_EXT_INT_WMAC_ALL) {
+- /* TODO: flush DDR? */
+- generic_handle_irq(ATH79_IP2_IRQ(1));
+- }
+-}
+-
+-static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
+-{
+- u32 status;
+-
+- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
+- status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
+- QCA955X_EXT_INT_USB1 |
+- QCA955X_EXT_INT_USB2;
+-
+- if (status == 0) {
+- spurious_interrupt();
+- return;
+- }
+-
+- if (status & QCA955X_EXT_INT_USB1) {
+- /* TODO: flush DDR? */
+- generic_handle_irq(ATH79_IP3_IRQ(0));
+- }
+-
+- if (status & QCA955X_EXT_INT_USB2) {
+- /* TODO: flush DDR? */
+- generic_handle_irq(ATH79_IP3_IRQ(1));
+- }
+-
+- if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
+- /* TODO: flush DDR? */
+- generic_handle_irq(ATH79_IP3_IRQ(2));
+- }
+-}
+-
+-static void qca955x_irq_init(void)
+-{
+- int i;
+-
+- for (i = ATH79_IP2_IRQ_BASE;
+- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+- irq_set_chip_and_handler(i, &dummy_irq_chip,
+- handle_level_irq);
+-
+- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
+-
+- for (i = ATH79_IP3_IRQ_BASE;
+- i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
+- irq_set_chip_and_handler(i, &dummy_irq_chip,
+- handle_level_irq);
+-
+- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
+-}
+-
+-void __init arch_init_irq(void)
+-{
+- unsigned irq_wb_chan2 = -1;
+- unsigned irq_wb_chan3 = -1;
+- bool misc_is_ar71xx;
+-
+- if (mips_machtype == ATH79_MACH_GENERIC_OF) {
+- irqchip_init();
+- return;
+- }
+-
+- if (soc_is_ar71xx() || soc_is_ar724x() ||
+- soc_is_ar913x() || soc_is_ar933x()) {
+- irq_wb_chan2 = 3;
+- irq_wb_chan3 = 2;
+- } else if (soc_is_ar934x()) {
+- irq_wb_chan3 = 2;
+- }
+-
+- ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
+-
+- if (soc_is_ar71xx() || soc_is_ar913x())
+- misc_is_ar71xx = true;
+- else if (soc_is_ar724x() ||
+- soc_is_ar933x() ||
+- soc_is_ar934x() ||
+- soc_is_qca955x())
+- misc_is_ar71xx = false;
+- else
+- BUG();
+- ath79_misc_irq_init(
+- ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
+- ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
+-
+- if (soc_is_ar934x())
+- ar934x_ip2_irq_init();
+- else if (soc_is_qca955x())
+- qca955x_irq_init();
+-}
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -19,6 +19,7 @@
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
+ #include <linux/of_fdt.h>
++#include <linux/irqchip.h>
+
+ #include <asm/bootinfo.h>
+ #include <asm/idle.h>
+@@ -311,6 +312,11 @@ void __init plat_time_init(void)
+ mips_hpt_frequency = cpu_clk_rate / 2;
+ }
+
++void __init arch_init_irq(void)
++{
++ irqchip_init();
++}
++
+ static int __init ath79_setup(void)
+ {
+ if (mips_machtype == ATH79_MACH_GENERIC_OF)
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -178,8 +178,4 @@ static inline u32 ath79_reset_rr(unsigne
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
+
+-void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
+-void ath79_misc_irq_init(void __iomem *regs, int irq,
+- int irq_base, bool is_ar71xx);
+-
+ #endif /* __ASM_MACH_ATH79_H */
+++ /dev/null
-From e03edbc8e68063b3fca7457fa048d8abe0045f1f Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Tue, 6 Mar 2018 10:15:54 +0100
-Subject: [PATCH 27/27] MIPS: ath79: drop mips_machine support
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/Kconfig | 1 -
- arch/mips/ath79/machtypes.h | 28 -----------------
- arch/mips/ath79/setup.c | 74 ++++++---------------------------------------
- 3 files changed, 10 insertions(+), 93 deletions(-)
- delete mode 100644 arch/mips/ath79/machtypes.h
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -196,7 +196,6 @@ config ATH79
- select COMMON_CLK
- select CLKDEV_LOOKUP
- select IRQ_MIPS_CPU
-- select MIPS_MACHINE
- select SYS_HAS_CPU_MIPS32_R2
- select SYS_HAS_EARLY_PRINTK
- select SYS_SUPPORTS_32BIT_KERNEL
---- a/arch/mips/ath79/machtypes.h
-+++ /dev/null
-@@ -1,28 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X/AR913X machine type definitions
-- *
-- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef _ATH79_MACHTYPE_H
--#define _ATH79_MACHTYPE_H
--
--#include <asm/mips_machine.h>
--
--enum ath79_mach_type {
-- ATH79_MACH_GENERIC_OF = -1, /* Device tree board */
-- ATH79_MACH_GENERIC = 0,
-- ATH79_MACH_AP121, /* Atheros AP121 reference board */
-- ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
-- ATH79_MACH_AP81, /* Atheros AP81 reference board */
-- ATH79_MACH_DB120, /* Atheros DB120 reference board */
-- ATH79_MACH_PB44, /* Atheros PB44 reference board */
-- ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
--};
--
--#endif /* _ATH79_MACHTYPE_H */
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -32,7 +32,6 @@
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include "common.h"
--#include "machtypes.h"
-
- #define ATH79_SYS_TYPE_LEN 64
-
-@@ -235,25 +234,21 @@ void __init plat_mem_setup(void)
- else if (fw_passed_dtb)
- __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
-
-- if (mips_machtype != ATH79_MACH_GENERIC_OF) {
-- ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
-- AR71XX_RESET_SIZE);
-- ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
-- AR71XX_PLL_SIZE);
-- ath79_detect_sys_type();
-- ath79_ddr_ctrl_init();
-+ ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
-+ AR71XX_RESET_SIZE);
-+ ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
-+ AR71XX_PLL_SIZE);
-+ ath79_detect_sys_type();
-+ ath79_ddr_ctrl_init();
-
-- detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
--
-- /* OF machines should use the reset driver */
-- _machine_restart = ath79_restart;
-- }
-+ detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
-
-+ _machine_restart = ath79_restart;
- _machine_halt = ath79_halt;
- pm_power_off = ath79_halt;
- }
-
--static void __init ath79_of_plat_time_init(void)
-+void __init plat_time_init(void)
- {
- struct device_node *np;
- struct clk *clk;
-@@ -283,62 +278,12 @@ static void __init ath79_of_plat_time_in
- clk_put(clk);
- }
-
--void __init plat_time_init(void)
--{
-- unsigned long cpu_clk_rate;
-- unsigned long ahb_clk_rate;
-- unsigned long ddr_clk_rate;
-- unsigned long ref_clk_rate;
--
-- if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
-- ath79_of_plat_time_init();
-- return;
-- }
--
-- ath79_clocks_init();
--
-- cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
-- ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
-- ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
-- ref_clk_rate = ath79_get_sys_clk_rate("ref");
--
-- pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
-- cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
-- ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
-- ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
-- ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
--
-- mips_hpt_frequency = cpu_clk_rate / 2;
--}
--
- void __init arch_init_irq(void)
- {
- irqchip_init();
- }
-
--static int __init ath79_setup(void)
--{
-- if (mips_machtype == ATH79_MACH_GENERIC_OF)
-- return 0;
--
-- mips_machine_setup();
--
-- return 0;
--}
--
--arch_initcall(ath79_setup);
--
- void __init device_tree_init(void)
- {
- unflatten_and_copy_device_tree();
- }
--
--MIPS_MACHINE(ATH79_MACH_GENERIC,
-- "Generic",
-- "Generic AR71XX/AR724X/AR913X based board",
-- NULL);
--
--MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
-- "DTB",
-- "Generic AR71XX/AR724X/AR913X based board (DT)",
-- NULL);
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -26,7 +26,6 @@
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include "common.h"
--#include "machtypes.h"
-
- #define AR71XX_BASE_FREQ 40000000
- #define AR724X_BASE_FREQ 40000000
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Tue, 6 Mar 2018 13:19:26 +0100
-Subject: [PATCH] MIPS: ath79: add helpers for setting clocks and expose
- the ref clock
-
-Preparation for transitioning legacy the legacy clock setup code over
-to OF.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -36,20 +36,46 @@ static struct clk_onecell_data clk_data
- .clk_num = ARRAY_SIZE(clks),
- };
-
--static struct clk *__init ath79_add_sys_clkdev(
-- const char *id, unsigned long rate)
-+static const char * const clk_names[ATH79_CLK_END] = {
-+ [ATH79_CLK_CPU] = "cpu",
-+ [ATH79_CLK_DDR] = "ddr",
-+ [ATH79_CLK_AHB] = "ahb",
-+ [ATH79_CLK_REF] = "ref",
-+};
-+
-+static const char * __init ath79_clk_name(int type)
- {
-- struct clk *clk;
-- int err;
-+ BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
-+ return clk_names[type];
-+}
-
-- clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
-+static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
-+{
- if (IS_ERR(clk))
-- panic("failed to allocate %s clock structure", id);
-+ panic("failed to allocate %s clock structure", clk_names[type]);
-
-- err = clk_register_clkdev(clk, id, NULL);
-- if (err)
-- panic("unable to register %s clock device", id);
-+ clks[type] = clk;
-+ clk_register_clkdev(clk, name, NULL);
-+}
-
-+static struct clk * __init ath79_set_clk(int type, unsigned long rate)
-+{
-+ const char *name = ath79_clk_name(type);
-+ struct clk *clk;
-+
-+ clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
-+ __ath79_set_clk(type, name, clk);
-+ return clk;
-+}
-+
-+static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
-+ unsigned int mult, unsigned int div)
-+{
-+ const char *name = ath79_clk_name(type);
-+ struct clk *clk;
-+
-+ clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
-+ __ath79_set_clk(type, name, clk);
- return clk;
- }
-
-@@ -79,27 +105,15 @@ static void __init ar71xx_clocks_init(vo
- div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
- ahb_rate = cpu_rate / div;
-
-- ath79_add_sys_clkdev("ref", ref_rate);
-- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
-- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
-- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
-+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ahb", NULL);
- }
-
--static struct clk * __init ath79_reg_ffclk(const char *name,
-- const char *parent_name, unsigned int mult, unsigned int div)
--{
-- struct clk *clk;
--
-- clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
-- if (IS_ERR(clk))
-- panic("failed to allocate %s clock structure", name);
--
-- return clk;
--}
--
- static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
- {
- u32 pll;
-@@ -113,24 +127,19 @@ static void __init ar724x_clk_init(struc
- ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
- ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
-
-- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
-- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
-- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
-+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
-+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
-+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
- }
-
- static void __init ar724x_clocks_init(void)
- {
- struct clk *ref_clk;
-
-- ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
-+ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
-
- ar724x_clk_init(ref_clk, ath79_pll_base);
-
-- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
-- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
-- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
-- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
--
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ahb", NULL);
- }
-@@ -185,12 +194,12 @@ static void __init ar9330_clk_init(struc
- AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
- }
-
-- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
-- ninit_mul, ref_div * out_div * cpu_div);
-- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
-- ninit_mul, ref_div * out_div * ddr_div);
-- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
-- ninit_mul, ref_div * out_div * ahb_div);
-+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
-+ ref_div * out_div * cpu_div);
-+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
-+ ref_div * out_div * ddr_div);
-+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
-+ ref_div * out_div * ahb_div);
- }
-
- static void __init ar933x_clocks_init(void)
-@@ -205,15 +214,10 @@ static void __init ar933x_clocks_init(vo
- else
- ref_rate = (25 * 1000 * 1000);
-
-- ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
-+ ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
-
- ar9330_clk_init(ref_clk, ath79_pll_base);
-
-- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
-- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
-- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
-- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
--
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
- }
-@@ -343,10 +347,10 @@ static void __init ar934x_clocks_init(vo
- else
- ahb_rate = cpu_pll / (postdiv + 1);
-
-- ath79_add_sys_clkdev("ref", ref_rate);
-- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
-- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
-- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
-+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
-@@ -430,10 +434,10 @@ static void __init qca953x_clocks_init(v
- else
- ahb_rate = cpu_pll / (postdiv + 1);
-
-- ath79_add_sys_clkdev("ref", ref_rate);
-- ath79_add_sys_clkdev("cpu", cpu_rate);
-- ath79_add_sys_clkdev("ddr", ddr_rate);
-- ath79_add_sys_clkdev("ahb", ahb_rate);
-+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
-@@ -515,10 +519,10 @@ static void __init qca955x_clocks_init(v
- else
- ahb_rate = cpu_pll / (postdiv + 1);
-
-- ath79_add_sys_clkdev("ref", ref_rate);
-- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
-- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
-- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
-+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
-@@ -609,10 +613,10 @@ static void __init qca956x_clocks_init(v
- else
- ahb_rate = cpu_pll / (postdiv + 1);
-
-- ath79_add_sys_clkdev("ref", ref_rate);
-- ath79_add_sys_clkdev("cpu", cpu_rate);
-- ath79_add_sys_clkdev("ddr", ddr_rate);
-- ath79_add_sys_clkdev("ahb", ahb_rate);
-+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
-+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
-+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
-+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
---- a/include/dt-bindings/clock/ath79-clk.h
-+++ b/include/dt-bindings/clock/ath79-clk.h
-@@ -13,7 +13,8 @@
- #define ATH79_CLK_CPU 0
- #define ATH79_CLK_DDR 1
- #define ATH79_CLK_AHB 2
-+#define ATH79_CLK_REF 3
-
--#define ATH79_CLK_END 3
-+#define ATH79_CLK_END 4
-
- #endif /* __DT_BINDINGS_ATH79_CLK_H */
--- /dev/null
+From badf28957b6dc400dff27bd23ba2ae75d9514be5 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:04:09 +0200
+Subject: [PATCH 28/33] MIPS: ath79: drop machfiles
+
+With the target now being fully OF based, we can drop the legacy mach
+files. Boards can now boot fully of devicetree files.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/Kconfig | 1 -
+ arch/mips/ath79/Kconfig | 73 -------------------
+ arch/mips/ath79/Makefile | 10 ---
+ arch/mips/ath79/clock.c | 1 -
+ arch/mips/ath79/mach-ap121.c | 92 ------------------------
+ arch/mips/ath79/mach-ap136.c | 156 -----------------------------------------
+ arch/mips/ath79/mach-ap81.c | 100 --------------------------
+ arch/mips/ath79/mach-db120.c | 136 -----------------------------------
+ arch/mips/ath79/mach-pb44.c | 128 ---------------------------------
+ arch/mips/ath79/mach-ubnt-xm.c | 126 ---------------------------------
+ arch/mips/ath79/machtypes.h | 28 --------
+ arch/mips/ath79/setup.c | 77 +++-----------------
+ 12 files changed, 9 insertions(+), 919 deletions(-)
+ delete mode 100644 arch/mips/ath79/mach-ap121.c
+ delete mode 100644 arch/mips/ath79/mach-ap136.c
+ delete mode 100644 arch/mips/ath79/mach-ap81.c
+ delete mode 100644 arch/mips/ath79/mach-db120.c
+ delete mode 100644 arch/mips/ath79/mach-pb44.c
+ delete mode 100644 arch/mips/ath79/mach-ubnt-xm.c
+ delete mode 100644 arch/mips/ath79/machtypes.h
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -196,7 +196,6 @@ config ATH79
+ select COMMON_CLK
+ select CLKDEV_LOOKUP
+ select IRQ_MIPS_CPU
+- select MIPS_MACHINE
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_HAS_EARLY_PRINTK
+ select SYS_SUPPORTS_32BIT_KERNEL
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -1,79 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ if ATH79
+
+-menu "Atheros AR71XX/AR724X/AR913X machine selection"
+-
+-config ATH79_MACH_AP121
+- bool "Atheros AP121 reference board"
+- select SOC_AR933X
+- select ATH79_DEV_GPIO_BUTTONS
+- select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
+- select ATH79_DEV_USB
+- select ATH79_DEV_WMAC
+- help
+- Say 'Y' here if you want your kernel to support the
+- Atheros AP121 reference board.
+-
+-config ATH79_MACH_AP136
+- bool "Atheros AP136 reference board"
+- select SOC_QCA955X
+- select ATH79_DEV_GPIO_BUTTONS
+- select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
+- select ATH79_DEV_USB
+- select ATH79_DEV_WMAC
+- help
+- Say 'Y' here if you want your kernel to support the
+- Atheros AP136 reference board.
+-
+-config ATH79_MACH_AP81
+- bool "Atheros AP81 reference board"
+- select SOC_AR913X
+- select ATH79_DEV_GPIO_BUTTONS
+- select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
+- select ATH79_DEV_USB
+- select ATH79_DEV_WMAC
+- help
+- Say 'Y' here if you want your kernel to support the
+- Atheros AP81 reference board.
+-
+-config ATH79_MACH_DB120
+- bool "Atheros DB120 reference board"
+- select SOC_AR934X
+- select ATH79_DEV_GPIO_BUTTONS
+- select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
+- select ATH79_DEV_USB
+- select ATH79_DEV_WMAC
+- help
+- Say 'Y' here if you want your kernel to support the
+- Atheros DB120 reference board.
+-
+-config ATH79_MACH_PB44
+- bool "Atheros PB44 reference board"
+- select SOC_AR71XX
+- select ATH79_DEV_GPIO_BUTTONS
+- select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
+- select ATH79_DEV_USB
+- help
+- Say 'Y' here if you want your kernel to support the
+- Atheros PB44 reference board.
+-
+-config ATH79_MACH_UBNT_XM
+- bool "Ubiquiti Networks XM (rev 1.0) board"
+- select SOC_AR724X
+- select ATH79_DEV_GPIO_BUTTONS
+- select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
+- help
+- Say 'Y' here if you want your kernel to support the
+- Ubiquiti Networks XM (rev 1.0) board.
+-
+-endmenu
+-
+ config SOC_AR71XX
+ select HW_HAS_PCI
+ def_bool n
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -22,13 +22,3 @@ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev
+ obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
+ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
+ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
+-
+-#
+-# Machines
+-#
+-obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
+-obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
+-obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
+-obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
+-obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
+-obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -26,7 +26,6 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "common.h"
+-#include "machtypes.h"
+
+ #define AR71XX_BASE_FREQ 40000000
+ #define AR724X_BASE_FREQ 40000000
+--- a/arch/mips/ath79/mach-ap121.c
++++ /dev/null
+@@ -1,92 +0,0 @@
+-/*
+- * Atheros AP121 board support
+- *
+- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include "machtypes.h"
+-#include "dev-gpio-buttons.h"
+-#include "dev-leds-gpio.h"
+-#include "dev-spi.h"
+-#include "dev-usb.h"
+-#include "dev-wmac.h"
+-
+-#define AP121_GPIO_LED_WLAN 0
+-#define AP121_GPIO_LED_USB 1
+-
+-#define AP121_GPIO_BTN_JUMPSTART 11
+-#define AP121_GPIO_BTN_RESET 12
+-
+-#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
+-#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
+-
+-#define AP121_CAL_DATA_ADDR 0x1fff1000
+-
+-static struct gpio_led ap121_leds_gpio[] __initdata = {
+- {
+- .name = "ap121:green:usb",
+- .gpio = AP121_GPIO_LED_USB,
+- .active_low = 0,
+- },
+- {
+- .name = "ap121:green:wlan",
+- .gpio = AP121_GPIO_LED_WLAN,
+- .active_low = 0,
+- },
+-};
+-
+-static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
+- {
+- .desc = "jumpstart button",
+- .type = EV_KEY,
+- .code = KEY_WPS_BUTTON,
+- .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = AP121_GPIO_BTN_JUMPSTART,
+- .active_low = 1,
+- },
+- {
+- .desc = "reset button",
+- .type = EV_KEY,
+- .code = KEY_RESTART,
+- .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = AP121_GPIO_BTN_RESET,
+- .active_low = 1,
+- }
+-};
+-
+-static struct spi_board_info ap121_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "mx25l1606e",
+- }
+-};
+-
+-static struct ath79_spi_platform_data ap121_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+-static void __init ap121_setup(void)
+-{
+- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
+-
+- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
+- ap121_leds_gpio);
+- ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+- ARRAY_SIZE(ap121_gpio_keys),
+- ap121_gpio_keys);
+-
+- ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+- ARRAY_SIZE(ap121_spi_info));
+- ath79_register_usb();
+- ath79_register_wmac(cal_data);
+-}
+-
+-MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
+- ap121_setup);
+--- a/arch/mips/ath79/mach-ap136.c
++++ /dev/null
+@@ -1,156 +0,0 @@
+-/*
+- * Qualcomm Atheros AP136 reference board support
+- *
+- * Copyright (c) 2012 Qualcomm Atheros
+- * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- *
+- */
+-
+-#include <linux/pci.h>
+-#include <linux/ath9k_platform.h>
+-
+-#include "machtypes.h"
+-#include "dev-gpio-buttons.h"
+-#include "dev-leds-gpio.h"
+-#include "dev-spi.h"
+-#include "dev-usb.h"
+-#include "dev-wmac.h"
+-#include "pci.h"
+-
+-#define AP136_GPIO_LED_STATUS_RED 14
+-#define AP136_GPIO_LED_STATUS_GREEN 19
+-#define AP136_GPIO_LED_USB 4
+-#define AP136_GPIO_LED_WLAN_2G 13
+-#define AP136_GPIO_LED_WLAN_5G 12
+-#define AP136_GPIO_LED_WPS_RED 15
+-#define AP136_GPIO_LED_WPS_GREEN 20
+-
+-#define AP136_GPIO_BTN_WPS 16
+-#define AP136_GPIO_BTN_RFKILL 21
+-
+-#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
+-#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
+-
+-#define AP136_WMAC_CALDATA_OFFSET 0x1000
+-#define AP136_PCIE_CALDATA_OFFSET 0x5000
+-
+-static struct gpio_led ap136_leds_gpio[] __initdata = {
+- {
+- .name = "qca:green:status",
+- .gpio = AP136_GPIO_LED_STATUS_GREEN,
+- .active_low = 1,
+- },
+- {
+- .name = "qca:red:status",
+- .gpio = AP136_GPIO_LED_STATUS_RED,
+- .active_low = 1,
+- },
+- {
+- .name = "qca:green:wps",
+- .gpio = AP136_GPIO_LED_WPS_GREEN,
+- .active_low = 1,
+- },
+- {
+- .name = "qca:red:wps",
+- .gpio = AP136_GPIO_LED_WPS_RED,
+- .active_low = 1,
+- },
+- {
+- .name = "qca:red:wlan-2g",
+- .gpio = AP136_GPIO_LED_WLAN_2G,
+- .active_low = 1,
+- },
+- {
+- .name = "qca:red:usb",
+- .gpio = AP136_GPIO_LED_USB,
+- .active_low = 1,
+- }
+-};
+-
+-static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
+- {
+- .desc = "WPS button",
+- .type = EV_KEY,
+- .code = KEY_WPS_BUTTON,
+- .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = AP136_GPIO_BTN_WPS,
+- .active_low = 1,
+- },
+- {
+- .desc = "RFKILL button",
+- .type = EV_KEY,
+- .code = KEY_RFKILL,
+- .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = AP136_GPIO_BTN_RFKILL,
+- .active_low = 1,
+- },
+-};
+-
+-static struct spi_board_info ap136_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "mx25l6405d",
+- }
+-};
+-
+-static struct ath79_spi_platform_data ap136_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ap136_ath9k_data;
+-
+-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+-{
+- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
+- dev->dev.platform_data = &ap136_ath9k_data;
+-
+- return 0;
+-}
+-
+-static void __init ap136_pci_init(u8 *eeprom)
+-{
+- memcpy(ap136_ath9k_data.eeprom_data, eeprom,
+- sizeof(ap136_ath9k_data.eeprom_data));
+-
+- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
+- ath79_register_pci();
+-}
+-#else
+-static inline void ap136_pci_init(u8 *eeprom) {}
+-#endif /* CONFIG_PCI */
+-
+-static void __init ap136_setup(void)
+-{
+- u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+-
+- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
+- ap136_leds_gpio);
+- ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
+- ARRAY_SIZE(ap136_gpio_keys),
+- ap136_gpio_keys);
+- ath79_register_spi(&ap136_spi_data, ap136_spi_info,
+- ARRAY_SIZE(ap136_spi_info));
+- ath79_register_usb();
+- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
+- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
+-}
+-
+-MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
+- "Atheros AP136-010 reference board",
+- ap136_setup);
+--- a/arch/mips/ath79/mach-ap81.c
++++ /dev/null
+@@ -1,100 +0,0 @@
+-/*
+- * Atheros AP81 board support
+- *
+- * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include "machtypes.h"
+-#include "dev-wmac.h"
+-#include "dev-gpio-buttons.h"
+-#include "dev-leds-gpio.h"
+-#include "dev-spi.h"
+-#include "dev-usb.h"
+-
+-#define AP81_GPIO_LED_STATUS 1
+-#define AP81_GPIO_LED_AOSS 3
+-#define AP81_GPIO_LED_WLAN 6
+-#define AP81_GPIO_LED_POWER 14
+-
+-#define AP81_GPIO_BTN_SW4 12
+-#define AP81_GPIO_BTN_SW1 21
+-
+-#define AP81_KEYS_POLL_INTERVAL 20 /* msecs */
+-#define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL)
+-
+-#define AP81_CAL_DATA_ADDR 0x1fff1000
+-
+-static struct gpio_led ap81_leds_gpio[] __initdata = {
+- {
+- .name = "ap81:green:status",
+- .gpio = AP81_GPIO_LED_STATUS,
+- .active_low = 1,
+- }, {
+- .name = "ap81:amber:aoss",
+- .gpio = AP81_GPIO_LED_AOSS,
+- .active_low = 1,
+- }, {
+- .name = "ap81:green:wlan",
+- .gpio = AP81_GPIO_LED_WLAN,
+- .active_low = 1,
+- }, {
+- .name = "ap81:green:power",
+- .gpio = AP81_GPIO_LED_POWER,
+- .active_low = 1,
+- }
+-};
+-
+-static struct gpio_keys_button ap81_gpio_keys[] __initdata = {
+- {
+- .desc = "sw1",
+- .type = EV_KEY,
+- .code = BTN_0,
+- .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = AP81_GPIO_BTN_SW1,
+- .active_low = 1,
+- } , {
+- .desc = "sw4",
+- .type = EV_KEY,
+- .code = BTN_1,
+- .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = AP81_GPIO_BTN_SW4,
+- .active_low = 1,
+- }
+-};
+-
+-static struct spi_board_info ap81_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "m25p64",
+- }
+-};
+-
+-static struct ath79_spi_platform_data ap81_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+-static void __init ap81_setup(void)
+-{
+- u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
+-
+- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio),
+- ap81_leds_gpio);
+- ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
+- ARRAY_SIZE(ap81_gpio_keys),
+- ap81_gpio_keys);
+- ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+- ARRAY_SIZE(ap81_spi_info));
+- ath79_register_wmac(cal_data);
+- ath79_register_usb();
+-}
+-
+-MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
+- ap81_setup);
+--- a/arch/mips/ath79/mach-db120.c
++++ /dev/null
+@@ -1,136 +0,0 @@
+-/*
+- * Atheros DB120 reference board support
+- *
+- * Copyright (c) 2011 Qualcomm Atheros
+- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- *
+- */
+-
+-#include <linux/pci.h>
+-#include <linux/ath9k_platform.h>
+-
+-#include "machtypes.h"
+-#include "dev-gpio-buttons.h"
+-#include "dev-leds-gpio.h"
+-#include "dev-spi.h"
+-#include "dev-usb.h"
+-#include "dev-wmac.h"
+-#include "pci.h"
+-
+-#define DB120_GPIO_LED_WLAN_5G 12
+-#define DB120_GPIO_LED_WLAN_2G 13
+-#define DB120_GPIO_LED_STATUS 14
+-#define DB120_GPIO_LED_WPS 15
+-
+-#define DB120_GPIO_BTN_WPS 16
+-
+-#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
+-#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
+-
+-#define DB120_WMAC_CALDATA_OFFSET 0x1000
+-#define DB120_PCIE_CALDATA_OFFSET 0x5000
+-
+-static struct gpio_led db120_leds_gpio[] __initdata = {
+- {
+- .name = "db120:green:status",
+- .gpio = DB120_GPIO_LED_STATUS,
+- .active_low = 1,
+- },
+- {
+- .name = "db120:green:wps",
+- .gpio = DB120_GPIO_LED_WPS,
+- .active_low = 1,
+- },
+- {
+- .name = "db120:green:wlan-5g",
+- .gpio = DB120_GPIO_LED_WLAN_5G,
+- .active_low = 1,
+- },
+- {
+- .name = "db120:green:wlan-2g",
+- .gpio = DB120_GPIO_LED_WLAN_2G,
+- .active_low = 1,
+- },
+-};
+-
+-static struct gpio_keys_button db120_gpio_keys[] __initdata = {
+- {
+- .desc = "WPS button",
+- .type = EV_KEY,
+- .code = KEY_WPS_BUTTON,
+- .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = DB120_GPIO_BTN_WPS,
+- .active_low = 1,
+- },
+-};
+-
+-static struct spi_board_info db120_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "s25sl064a",
+- }
+-};
+-
+-static struct ath79_spi_platform_data db120_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data db120_ath9k_data;
+-
+-static int db120_pci_plat_dev_init(struct pci_dev *dev)
+-{
+- switch (PCI_SLOT(dev->devfn)) {
+- case 0:
+- dev->dev.platform_data = &db120_ath9k_data;
+- break;
+- }
+-
+- return 0;
+-}
+-
+-static void __init db120_pci_init(u8 *eeprom)
+-{
+- memcpy(db120_ath9k_data.eeprom_data, eeprom,
+- sizeof(db120_ath9k_data.eeprom_data));
+-
+- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
+- ath79_register_pci();
+-}
+-#else
+-static inline void db120_pci_init(u8 *eeprom) {}
+-#endif /* CONFIG_PCI */
+-
+-static void __init db120_setup(void)
+-{
+- u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+-
+- ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
+- db120_leds_gpio);
+- ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
+- ARRAY_SIZE(db120_gpio_keys),
+- db120_gpio_keys);
+- ath79_register_spi(&db120_spi_data, db120_spi_info,
+- ARRAY_SIZE(db120_spi_info));
+- ath79_register_usb();
+- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
+- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
+-}
+-
+-MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
+- db120_setup);
+--- a/arch/mips/ath79/mach-pb44.c
++++ /dev/null
+@@ -1,122 +0,0 @@
+-/*
+- * Atheros PB44 reference board support
+- *
+- * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/init.h>
+-#include <linux/platform_device.h>
+-#include <linux/i2c.h>
+-#include <linux/i2c-gpio.h>
+-#include <linux/platform_data/pcf857x.h>
+-
+-#include "machtypes.h"
+-#include "dev-gpio-buttons.h"
+-#include "dev-leds-gpio.h"
+-#include "dev-spi.h"
+-#include "dev-usb.h"
+-#include "pci.h"
+-
+-#define PB44_GPIO_I2C_SCL 0
+-#define PB44_GPIO_I2C_SDA 1
+-
+-#define PB44_GPIO_EXP_BASE 16
+-#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
+-#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
+-#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
+-#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10)
+-
+-#define PB44_KEYS_POLL_INTERVAL 20 /* msecs */
+-#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL)
+-
+-static struct i2c_gpio_platform_data pb44_i2c_gpio_data = {
+- .sda_pin = PB44_GPIO_I2C_SDA,
+- .scl_pin = PB44_GPIO_I2C_SCL,
+-};
+-
+-static struct platform_device pb44_i2c_gpio_device = {
+- .name = "i2c-gpio",
+- .id = 0,
+- .dev = {
+- .platform_data = &pb44_i2c_gpio_data,
+- }
+-};
+-
+-static struct pcf857x_platform_data pb44_pcf857x_data = {
+- .gpio_base = PB44_GPIO_EXP_BASE,
+-};
+-
+-static struct i2c_board_info pb44_i2c_board_info[] __initdata = {
+- {
+- I2C_BOARD_INFO("pcf8575", 0x20),
+- .platform_data = &pb44_pcf857x_data,
+- },
+-};
+-
+-static struct gpio_led pb44_leds_gpio[] __initdata = {
+- {
+- .name = "pb44:amber:jump1",
+- .gpio = PB44_GPIO_LED_JUMP1,
+- .active_low = 1,
+- }, {
+- .name = "pb44:green:jump2",
+- .gpio = PB44_GPIO_LED_JUMP2,
+- .active_low = 1,
+- },
+-};
+-
+-static struct gpio_keys_button pb44_gpio_keys[] __initdata = {
+- {
+- .desc = "soft_reset",
+- .type = EV_KEY,
+- .code = KEY_RESTART,
+- .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = PB44_GPIO_SW_RESET,
+- .active_low = 1,
+- } , {
+- .desc = "jumpstart",
+- .type = EV_KEY,
+- .code = KEY_WPS_BUTTON,
+- .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = PB44_GPIO_SW_JUMP,
+- .active_low = 1,
+- }
+-};
+-
+-static struct spi_board_info pb44_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "m25p64",
+- },
+-};
+-
+-static struct ath79_spi_platform_data pb44_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+-static void __init pb44_init(void)
+-{
+- i2c_register_board_info(0, pb44_i2c_board_info,
+- ARRAY_SIZE(pb44_i2c_board_info));
+- platform_device_register(&pb44_i2c_gpio_device);
+-
+- ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio),
+- pb44_leds_gpio);
+- ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL,
+- ARRAY_SIZE(pb44_gpio_keys),
+- pb44_gpio_keys);
+- ath79_register_spi(&pb44_spi_data, pb44_spi_info,
+- ARRAY_SIZE(pb44_spi_info));
+- ath79_register_usb();
+- ath79_register_pci();
+-}
+-
+-MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
+- pb44_init);
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ /dev/null
+@@ -1,126 +0,0 @@
+-/*
+- * Ubiquiti Networks XM (rev 1.0) board support
+- *
+- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+- *
+- * Derived from: mach-pb44.c
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/init.h>
+-#include <linux/pci.h>
+-#include <linux/ath9k_platform.h>
+-
+-#include <asm/mach-ath79/irq.h>
+-
+-#include "machtypes.h"
+-#include "dev-gpio-buttons.h"
+-#include "dev-leds-gpio.h"
+-#include "dev-spi.h"
+-#include "pci.h"
+-
+-#define UBNT_XM_GPIO_LED_L1 0
+-#define UBNT_XM_GPIO_LED_L2 1
+-#define UBNT_XM_GPIO_LED_L3 11
+-#define UBNT_XM_GPIO_LED_L4 7
+-
+-#define UBNT_XM_GPIO_BTN_RESET 12
+-
+-#define UBNT_XM_KEYS_POLL_INTERVAL 20
+-#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
+-
+-#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
+-
+-static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+- {
+- .name = "ubnt-xm:red:link1",
+- .gpio = UBNT_XM_GPIO_LED_L1,
+- .active_low = 0,
+- }, {
+- .name = "ubnt-xm:orange:link2",
+- .gpio = UBNT_XM_GPIO_LED_L2,
+- .active_low = 0,
+- }, {
+- .name = "ubnt-xm:green:link3",
+- .gpio = UBNT_XM_GPIO_LED_L3,
+- .active_low = 0,
+- }, {
+- .name = "ubnt-xm:green:link4",
+- .gpio = UBNT_XM_GPIO_LED_L4,
+- .active_low = 0,
+- },
+-};
+-
+-static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = {
+- {
+- .desc = "reset",
+- .type = EV_KEY,
+- .code = KEY_RESTART,
+- .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
+- .gpio = UBNT_XM_GPIO_BTN_RESET,
+- .active_low = 1,
+- }
+-};
+-
+-static struct spi_board_info ubnt_xm_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "mx25l6405d",
+- }
+-};
+-
+-static struct ath79_spi_platform_data ubnt_xm_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ubnt_xm_eeprom_data;
+-
+-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
+-{
+- switch (PCI_SLOT(dev->devfn)) {
+- case 0:
+- dev->dev.platform_data = &ubnt_xm_eeprom_data;
+- break;
+- }
+-
+- return 0;
+-}
+-
+-static void __init ubnt_xm_pci_init(void)
+-{
+- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+- sizeof(ubnt_xm_eeprom_data.eeprom_data));
+-
+- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
+- ath79_register_pci();
+-}
+-#else
+-static inline void ubnt_xm_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+-
+-static void __init ubnt_xm_init(void)
+-{
+- ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+- ubnt_xm_leds_gpio);
+-
+- ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
+- ARRAY_SIZE(ubnt_xm_gpio_keys),
+- ubnt_xm_gpio_keys);
+-
+- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
+- ARRAY_SIZE(ubnt_xm_spi_info));
+-
+- ubnt_xm_pci_init();
+-}
+-
+-MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+- "UBNT-XM",
+- "Ubiquiti Networks XM (rev 1.0) board",
+- ubnt_xm_init);
+--- a/arch/mips/ath79/machtypes.h
++++ /dev/null
+@@ -1,28 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X machine type definitions
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_MACHTYPE_H
+-#define _ATH79_MACHTYPE_H
+-
+-#include <asm/mips_machine.h>
+-
+-enum ath79_mach_type {
+- ATH79_MACH_GENERIC_OF = -1, /* Device tree board */
+- ATH79_MACH_GENERIC = 0,
+- ATH79_MACH_AP121, /* Atheros AP121 reference board */
+- ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
+- ATH79_MACH_AP81, /* Atheros AP81 reference board */
+- ATH79_MACH_DB120, /* Atheros DB120 reference board */
+- ATH79_MACH_PB44, /* Atheros PB44 reference board */
+- ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
+-};
+-
+-#endif /* _ATH79_MACHTYPE_H */
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -33,7 +33,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "common.h"
+ #include "dev-common.h"
+-#include "machtypes.h"
+
+ #define ATH79_SYS_TYPE_LEN 64
+
+@@ -236,25 +235,21 @@ void __init plat_mem_setup(void)
+ else if (fw_passed_dtb)
+ __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
+
+- if (mips_machtype != ATH79_MACH_GENERIC_OF) {
+- ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
+- AR71XX_RESET_SIZE);
+- ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
+- AR71XX_PLL_SIZE);
+- ath79_detect_sys_type();
+- ath79_ddr_ctrl_init();
++ ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
++ AR71XX_RESET_SIZE);
++ ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
++ AR71XX_PLL_SIZE);
++ ath79_detect_sys_type();
++ ath79_ddr_ctrl_init();
+
+- detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
+-
+- /* OF machines should use the reset driver */
+- _machine_restart = ath79_restart;
+- }
++ detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
+
++ _machine_restart = ath79_restart;
+ _machine_halt = ath79_halt;
+ pm_power_off = ath79_halt;
+ }
+
+-static void __init ath79_of_plat_time_init(void)
++void __init plat_time_init(void)
+ {
+ struct device_node *np;
+ struct clk *clk;
+@@ -284,66 +279,12 @@ static void __init ath79_of_plat_time_in
+ clk_put(clk);
+ }
+
+-void __init plat_time_init(void)
+-{
+- unsigned long cpu_clk_rate;
+- unsigned long ahb_clk_rate;
+- unsigned long ddr_clk_rate;
+- unsigned long ref_clk_rate;
+-
+- if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
+- ath79_of_plat_time_init();
+- return;
+- }
+-
+- ath79_clocks_init();
+-
+- cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
+- ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
+- ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
+- ref_clk_rate = ath79_get_sys_clk_rate("ref");
+-
+- pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
+- cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
+- ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
+- ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
+- ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
+-
+- mips_hpt_frequency = cpu_clk_rate / 2;
+-}
+-
+ void __init arch_init_irq(void)
+ {
+ irqchip_init();
+ }
+
+-static int __init ath79_setup(void)
+-{
+- if (mips_machtype == ATH79_MACH_GENERIC_OF)
+- return 0;
+-
+- ath79_gpio_init();
+- ath79_register_uart();
+- ath79_register_wdt();
+-
+- mips_machine_setup();
+-
+- return 0;
+-}
+-
+-arch_initcall(ath79_setup);
+-
+ void __init device_tree_init(void)
+ {
+ unflatten_and_copy_device_tree();
+ }
+-
+-MIPS_MACHINE(ATH79_MACH_GENERIC,
+- "Generic",
+- "Generic AR71XX/AR724X/AR913X based board",
+- NULL);
+-
+-MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
+- "DTB",
+- "Generic AR71XX/AR724X/AR913X based board (DT)",
+- NULL);
--- /dev/null
+From d0f1420702ed47a82572aaf39e7407055518d14e Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:05:19 +0200
+Subject: [PATCH 29/33] MIPS: ath79: drop legacy pci code
+
+With the target now being fully OF based, we can drop the legacy pci
+platform code. The only bits that we need to keep is the fixup code
+which we move to its own code file.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/Makefile | 1 -
+ arch/mips/ath79/pci.c | 273 --------------------------------------------
+ arch/mips/ath79/pci.h | 35 ------
+ arch/mips/pci/Makefile | 1 +
+ arch/mips/pci/fixup-ath79.c | 21 ++++
+ 5 files changed, 22 insertions(+), 309 deletions(-)
+ delete mode 100644 arch/mips/ath79/pci.c
+ delete mode 100644 arch/mips/ath79/pci.h
+ create mode 100644 arch/mips/pci/fixup-ath79.c
+
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -11,7 +11,6 @@
+ obj-y := prom.o setup.o common.o clock.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+-obj-$(CONFIG_PCI) += pci.o
+
+ #
+ # Devices
+--- a/arch/mips/ath79/pci.c
++++ /dev/null
+@@ -1,273 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X specific PCI setup code
+- *
+- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * Parts of this file are based on Atheros' 2.6.15 BSP
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/init.h>
+-#include <linux/pci.h>
+-#include <linux/resource.h>
+-#include <linux/platform_device.h>
+-#include <asm/mach-ath79/ar71xx_regs.h>
+-#include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/irq.h>
+-#include "pci.h"
+-
+-static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
+-static const struct ath79_pci_irq *ath79_pci_irq_map;
+-static unsigned ath79_pci_nr_irqs;
+-
+-static const struct ath79_pci_irq ar71xx_pci_irq_map[] = {
+- {
+- .slot = 17,
+- .pin = 1,
+- .irq = ATH79_PCI_IRQ(0),
+- }, {
+- .slot = 18,
+- .pin = 1,
+- .irq = ATH79_PCI_IRQ(1),
+- }, {
+- .slot = 19,
+- .pin = 1,
+- .irq = ATH79_PCI_IRQ(2),
+- }
+-};
+-
+-static const struct ath79_pci_irq ar724x_pci_irq_map[] = {
+- {
+- .slot = 0,
+- .pin = 1,
+- .irq = ATH79_PCI_IRQ(0),
+- }
+-};
+-
+-static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
+- {
+- .bus = 0,
+- .slot = 0,
+- .pin = 1,
+- .irq = ATH79_PCI_IRQ(0),
+- },
+- {
+- .bus = 1,
+- .slot = 0,
+- .pin = 1,
+- .irq = ATH79_PCI_IRQ(1),
+- },
+-};
+-
+-int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+-{
+- int irq = -1;
+- int i;
+-
+- if (ath79_pci_nr_irqs == 0 ||
+- ath79_pci_irq_map == NULL) {
+- if (soc_is_ar71xx()) {
+- ath79_pci_irq_map = ar71xx_pci_irq_map;
+- ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
+- } else if (soc_is_ar724x() ||
+- soc_is_ar9342() ||
+- soc_is_ar9344()) {
+- ath79_pci_irq_map = ar724x_pci_irq_map;
+- ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
+- } else if (soc_is_qca955x()) {
+- ath79_pci_irq_map = qca955x_pci_irq_map;
+- ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
+- } else {
+- pr_crit("pci %s: invalid irq map\n",
+- pci_name((struct pci_dev *) dev));
+- return irq;
+- }
+- }
+-
+- for (i = 0; i < ath79_pci_nr_irqs; i++) {
+- const struct ath79_pci_irq *entry;
+-
+- entry = &ath79_pci_irq_map[i];
+- if (entry->bus == dev->bus->number &&
+- entry->slot == slot &&
+- entry->pin == pin) {
+- irq = entry->irq;
+- break;
+- }
+- }
+-
+- if (irq < 0)
+- pr_crit("pci %s: no irq found for pin %u\n",
+- pci_name((struct pci_dev *) dev), pin);
+- else
+- pr_info("pci %s: using irq %d for pin %u\n",
+- pci_name((struct pci_dev *) dev), irq, pin);
+-
+- return irq;
+-}
+-
+-int pcibios_plat_dev_init(struct pci_dev *dev)
+-{
+- if (ath79_pci_plat_dev_init)
+- return ath79_pci_plat_dev_init(dev);
+-
+- return 0;
+-}
+-
+-void __init ath79_pci_set_irq_map(unsigned nr_irqs,
+- const struct ath79_pci_irq *map)
+-{
+- ath79_pci_nr_irqs = nr_irqs;
+- ath79_pci_irq_map = map;
+-}
+-
+-void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
+-{
+- ath79_pci_plat_dev_init = func;
+-}
+-
+-static struct platform_device *
+-ath79_register_pci_ar71xx(void)
+-{
+- struct platform_device *pdev;
+- struct resource res[4];
+-
+- memset(res, 0, sizeof(res));
+-
+- res[0].name = "cfg_base";
+- res[0].flags = IORESOURCE_MEM;
+- res[0].start = AR71XX_PCI_CFG_BASE;
+- res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
+-
+- res[1].flags = IORESOURCE_IRQ;
+- res[1].start = ATH79_CPU_IRQ(2);
+- res[1].end = ATH79_CPU_IRQ(2);
+-
+- res[2].name = "io_base";
+- res[2].flags = IORESOURCE_IO;
+- res[2].start = 0;
+- res[2].end = 0;
+-
+- res[3].name = "mem_base";
+- res[3].flags = IORESOURCE_MEM;
+- res[3].start = AR71XX_PCI_MEM_BASE;
+- res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
+-
+- pdev = platform_device_register_simple("ar71xx-pci", -1,
+- res, ARRAY_SIZE(res));
+- return pdev;
+-}
+-
+-static struct platform_device *
+-ath79_register_pci_ar724x(int id,
+- unsigned long cfg_base,
+- unsigned long ctrl_base,
+- unsigned long crp_base,
+- unsigned long mem_base,
+- unsigned long mem_size,
+- unsigned long io_base,
+- int irq)
+-{
+- struct platform_device *pdev;
+- struct resource res[6];
+-
+- memset(res, 0, sizeof(res));
+-
+- res[0].name = "cfg_base";
+- res[0].flags = IORESOURCE_MEM;
+- res[0].start = cfg_base;
+- res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
+-
+- res[1].name = "ctrl_base";
+- res[1].flags = IORESOURCE_MEM;
+- res[1].start = ctrl_base;
+- res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
+-
+- res[2].flags = IORESOURCE_IRQ;
+- res[2].start = irq;
+- res[2].end = irq;
+-
+- res[3].name = "mem_base";
+- res[3].flags = IORESOURCE_MEM;
+- res[3].start = mem_base;
+- res[3].end = mem_base + mem_size - 1;
+-
+- res[4].name = "io_base";
+- res[4].flags = IORESOURCE_IO;
+- res[4].start = io_base;
+- res[4].end = io_base;
+-
+- res[5].name = "crp_base";
+- res[5].flags = IORESOURCE_MEM;
+- res[5].start = crp_base;
+- res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
+-
+- pdev = platform_device_register_simple("ar724x-pci", id,
+- res, ARRAY_SIZE(res));
+- return pdev;
+-}
+-
+-int __init ath79_register_pci(void)
+-{
+- struct platform_device *pdev = NULL;
+-
+- if (soc_is_ar71xx()) {
+- pdev = ath79_register_pci_ar71xx();
+- } else if (soc_is_ar724x()) {
+- pdev = ath79_register_pci_ar724x(-1,
+- AR724X_PCI_CFG_BASE,
+- AR724X_PCI_CTRL_BASE,
+- AR724X_PCI_CRP_BASE,
+- AR724X_PCI_MEM_BASE,
+- AR724X_PCI_MEM_SIZE,
+- 0,
+- ATH79_CPU_IRQ(2));
+- } else if (soc_is_ar9342() ||
+- soc_is_ar9344()) {
+- u32 bootstrap;
+-
+- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+- if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
+- return -ENODEV;
+-
+- pdev = ath79_register_pci_ar724x(-1,
+- AR724X_PCI_CFG_BASE,
+- AR724X_PCI_CTRL_BASE,
+- AR724X_PCI_CRP_BASE,
+- AR724X_PCI_MEM_BASE,
+- AR724X_PCI_MEM_SIZE,
+- 0,
+- ATH79_IP2_IRQ(0));
+- } else if (soc_is_qca9558()) {
+- pdev = ath79_register_pci_ar724x(0,
+- QCA955X_PCI_CFG_BASE0,
+- QCA955X_PCI_CTRL_BASE0,
+- QCA955X_PCI_CRP_BASE0,
+- QCA955X_PCI_MEM_BASE0,
+- QCA955X_PCI_MEM_SIZE,
+- 0,
+- ATH79_IP2_IRQ(0));
+-
+- pdev = ath79_register_pci_ar724x(1,
+- QCA955X_PCI_CFG_BASE1,
+- QCA955X_PCI_CTRL_BASE1,
+- QCA955X_PCI_CRP_BASE1,
+- QCA955X_PCI_MEM_BASE1,
+- QCA955X_PCI_MEM_SIZE,
+- 1,
+- ATH79_IP3_IRQ(2));
+- } else {
+- /* No PCI support */
+- return -ENODEV;
+- }
+-
+- if (!pdev)
+- pr_err("unable to register PCI controller device\n");
+-
+- return pdev ? 0 : -ENODEV;
+-}
+--- a/arch/mips/ath79/pci.h
++++ /dev/null
+@@ -1,35 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X PCI support
+- *
+- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_PCI_H
+-#define _ATH79_PCI_H
+-
+-struct ath79_pci_irq {
+- int bus;
+- u8 slot;
+- u8 pin;
+- int irq;
+-};
+-
+-#ifdef CONFIG_PCI
+-void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
+-void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
+-int ath79_register_pci(void);
+-#else
+-static inline void
+-ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {}
+-static inline void
+-ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
+-static inline int ath79_register_pci(void) { return 0; }
+-#endif
+-
+-#endif /* _ATH79_PCI_H */
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-vir
+ #
+ # These are still pretty much in the old state, watch, go blind.
+ #
++obj-$(CONFIG_ATH79) += fixup-ath79.o
+ obj-$(CONFIG_LASAT) += pci-lasat.o
+ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
+ obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
+--- /dev/null
++++ b/arch/mips/pci/fixup-ath79.c
+@@ -0,0 +1,21 @@
++/*
++ * Copyright (C) 2018 John Crispin <john@phrozen.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/pci.h>
++//#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ return PCIBIOS_SUCCESSFUL;
++}
++
++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ return of_irq_parse_and_map_pci(dev, slot, pin);
++}
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Tue, 6 Mar 2018 13:22:43 +0100
-Subject: [PATCH] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
- out of soc init
-
-Preparation for reusing functions for DT
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -109,9 +109,6 @@ static void __init ar71xx_clocks_init(vo
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
-- clk_add_alias("wdt", NULL, "ahb", NULL);
-- clk_add_alias("uart", NULL, "ahb", NULL);
- }
-
- static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-@@ -139,9 +136,6 @@ static void __init ar724x_clocks_init(vo
- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
-
- ar724x_clk_init(ref_clk, ath79_pll_base);
--
-- clk_add_alias("wdt", NULL, "ahb", NULL);
-- clk_add_alias("uart", NULL, "ahb", NULL);
- }
-
- static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-@@ -217,9 +211,6 @@ static void __init ar933x_clocks_init(vo
- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
-
- ar9330_clk_init(ref_clk, ath79_pll_base);
--
-- clk_add_alias("wdt", NULL, "ahb", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
- }
-
- static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
-@@ -352,9 +343,6 @@ static void __init ar934x_clocks_init(vo
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
-- clk_add_alias("wdt", NULL, "ref", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
--
- iounmap(dpll_base);
- }
-
-@@ -438,9 +426,6 @@ static void __init qca953x_clocks_init(v
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
-- clk_add_alias("wdt", NULL, "ref", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
- }
-
- static void __init qca955x_clocks_init(void)
-@@ -523,9 +508,6 @@ static void __init qca955x_clocks_init(v
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
-- clk_add_alias("wdt", NULL, "ref", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
- }
-
- static void __init qca956x_clocks_init(void)
-@@ -617,13 +599,13 @@ static void __init qca956x_clocks_init(v
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
-- clk_add_alias("wdt", NULL, "ref", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
- }
-
- void __init ath79_clocks_init(void)
- {
-+ const char *wdt;
-+ const char *uart;
-+
- if (soc_is_ar71xx())
- ar71xx_clocks_init();
- else if (soc_is_ar724x() || soc_is_ar913x())
-@@ -640,6 +622,20 @@ void __init ath79_clocks_init(void)
- qca956x_clocks_init();
- else
- BUG();
-+
-+ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
-+ wdt = "ahb";
-+ uart = "ahb";
-+ } else if (soc_is_ar933x()) {
-+ wdt = "ahb";
-+ uart = "ref";
-+ } else {
-+ wdt = "ref";
-+ uart = "ref";
-+ }
-+
-+ clk_add_alias("wdt", NULL, wdt, NULL);
-+ clk_add_alias("uart", NULL, uart, NULL);
- }
-
- unsigned long __init
--- /dev/null
+From dce930fba8ad3a90ccd164f199e57c2d61937ccd Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:12:38 +0200
+Subject: [PATCH 30/33] MIPS: ath79: drop platform device registration code
+
+With the target now being fully OF based, we can drop the legacy platform
+device registration code. All devices and their drivers are now probed
+via OF.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/Makefile | 10 --
+ arch/mips/ath79/common.h | 2 -
+ arch/mips/ath79/dev-common.c | 159 ------------------------
+ arch/mips/ath79/dev-common.h | 18 ---
+ arch/mips/ath79/dev-gpio-buttons.c | 56 ---------
+ arch/mips/ath79/dev-gpio-buttons.h | 23 ----
+ arch/mips/ath79/dev-leds-gpio.c | 54 ---------
+ arch/mips/ath79/dev-leds-gpio.h | 21 ----
+ arch/mips/ath79/dev-spi.c | 38 ------
+ arch/mips/ath79/dev-spi.h | 22 ----
+ arch/mips/ath79/dev-usb.c | 242 -------------------------------------
+ arch/mips/ath79/dev-usb.h | 17 ---
+ arch/mips/ath79/dev-wmac.c | 155 ------------------------
+ arch/mips/ath79/dev-wmac.h | 17 ---
+ arch/mips/ath79/setup.c | 1 -
+ 15 files changed, 835 deletions(-)
+ delete mode 100644 arch/mips/ath79/dev-common.c
+ delete mode 100644 arch/mips/ath79/dev-common.h
+ delete mode 100644 arch/mips/ath79/dev-gpio-buttons.c
+ delete mode 100644 arch/mips/ath79/dev-gpio-buttons.h
+ delete mode 100644 arch/mips/ath79/dev-leds-gpio.c
+ delete mode 100644 arch/mips/ath79/dev-leds-gpio.h
+ delete mode 100644 arch/mips/ath79/dev-spi.c
+ delete mode 100644 arch/mips/ath79/dev-spi.h
+ delete mode 100644 arch/mips/ath79/dev-usb.c
+ delete mode 100644 arch/mips/ath79/dev-usb.h
+ delete mode 100644 arch/mips/ath79/dev-wmac.c
+ delete mode 100644 arch/mips/ath79/dev-wmac.h
+
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -11,13 +11,3 @@
+ obj-y := prom.o setup.o common.o clock.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+-
+-#
+-# Devices
+-#
+-obj-y += dev-common.o
+-obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
+-obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
+-obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
+-obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
+-obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
+--- a/arch/mips/ath79/common.h
++++ b/arch/mips/ath79/common.h
+@@ -24,6 +24,4 @@ unsigned long ath79_get_sys_clk_rate(con
+
+ void ath79_ddr_ctrl_init(void);
+
+-void ath79_gpio_init(void);
+-
+ #endif /* __ATH79_COMMON_H */
+--- a/arch/mips/ath79/dev-common.c
++++ /dev/null
+@@ -1,159 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X common devices
+- *
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * Parts of this file are based on Atheros' 2.6.15 BSP
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/platform_device.h>
+-#include <linux/platform_data/gpio-ath79.h>
+-#include <linux/serial_8250.h>
+-#include <linux/clk.h>
+-#include <linux/err.h>
+-
+-#include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/ar71xx_regs.h>
+-#include "common.h"
+-#include "dev-common.h"
+-
+-static struct resource ath79_uart_resources[] = {
+- {
+- .start = AR71XX_UART_BASE,
+- .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
+-static struct plat_serial8250_port ath79_uart_data[] = {
+- {
+- .mapbase = AR71XX_UART_BASE,
+- .irq = ATH79_MISC_IRQ(3),
+- .flags = AR71XX_UART_FLAGS,
+- .iotype = UPIO_MEM32,
+- .regshift = 2,
+- }, {
+- /* terminating entry */
+- }
+-};
+-
+-static struct platform_device ath79_uart_device = {
+- .name = "serial8250",
+- .id = PLAT8250_DEV_PLATFORM,
+- .resource = ath79_uart_resources,
+- .num_resources = ARRAY_SIZE(ath79_uart_resources),
+- .dev = {
+- .platform_data = ath79_uart_data
+- },
+-};
+-
+-static struct resource ar933x_uart_resources[] = {
+- {
+- .start = AR933X_UART_BASE,
+- .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .start = ATH79_MISC_IRQ(3),
+- .end = ATH79_MISC_IRQ(3),
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device ar933x_uart_device = {
+- .name = "ar933x-uart",
+- .id = -1,
+- .resource = ar933x_uart_resources,
+- .num_resources = ARRAY_SIZE(ar933x_uart_resources),
+-};
+-
+-void __init ath79_register_uart(void)
+-{
+- unsigned long uart_clk_rate;
+-
+- uart_clk_rate = ath79_get_sys_clk_rate("uart");
+-
+- if (soc_is_ar71xx() ||
+- soc_is_ar724x() ||
+- soc_is_ar913x() ||
+- soc_is_ar934x() ||
+- soc_is_qca955x()) {
+- ath79_uart_data[0].uartclk = uart_clk_rate;
+- platform_device_register(&ath79_uart_device);
+- } else if (soc_is_ar933x()) {
+- platform_device_register(&ar933x_uart_device);
+- } else {
+- BUG();
+- }
+-}
+-
+-void __init ath79_register_wdt(void)
+-{
+- struct resource res;
+-
+- memset(&res, 0, sizeof(res));
+-
+- res.flags = IORESOURCE_MEM;
+- res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL;
+- res.end = res.start + 0x8 - 1;
+-
+- platform_device_register_simple("ath79-wdt", -1, &res, 1);
+-}
+-
+-static struct ath79_gpio_platform_data ath79_gpio_pdata;
+-
+-static struct resource ath79_gpio_resources[] = {
+- {
+- .flags = IORESOURCE_MEM,
+- .start = AR71XX_GPIO_BASE,
+- .end = AR71XX_GPIO_BASE + AR71XX_GPIO_SIZE - 1,
+- },
+- {
+- .start = ATH79_MISC_IRQ(2),
+- .end = ATH79_MISC_IRQ(2),
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device ath79_gpio_device = {
+- .name = "ath79-gpio",
+- .id = -1,
+- .resource = ath79_gpio_resources,
+- .num_resources = ARRAY_SIZE(ath79_gpio_resources),
+- .dev = {
+- .platform_data = &ath79_gpio_pdata
+- },
+-};
+-
+-void __init ath79_gpio_init(void)
+-{
+- if (soc_is_ar71xx()) {
+- ath79_gpio_pdata.ngpios = AR71XX_GPIO_COUNT;
+- } else if (soc_is_ar7240()) {
+- ath79_gpio_pdata.ngpios = AR7240_GPIO_COUNT;
+- } else if (soc_is_ar7241() || soc_is_ar7242()) {
+- ath79_gpio_pdata.ngpios = AR7241_GPIO_COUNT;
+- } else if (soc_is_ar913x()) {
+- ath79_gpio_pdata.ngpios = AR913X_GPIO_COUNT;
+- } else if (soc_is_ar933x()) {
+- ath79_gpio_pdata.ngpios = AR933X_GPIO_COUNT;
+- } else if (soc_is_ar934x()) {
+- ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
+- ath79_gpio_pdata.oe_inverted = 1;
+- } else if (soc_is_qca955x()) {
+- ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
+- ath79_gpio_pdata.oe_inverted = 1;
+- } else {
+- BUG();
+- }
+-
+- platform_device_register(&ath79_gpio_device);
+-}
+--- a/arch/mips/ath79/dev-common.h
++++ /dev/null
+@@ -1,18 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X common devices
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_DEV_COMMON_H
+-#define _ATH79_DEV_COMMON_H
+-
+-void ath79_register_uart(void);
+-void ath79_register_wdt(void);
+-
+-#endif /* _ATH79_DEV_COMMON_H */
+--- a/arch/mips/ath79/dev-gpio-buttons.c
++++ /dev/null
+@@ -1,56 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X GPIO button support
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include "linux/init.h"
+-#include "linux/slab.h"
+-#include <linux/platform_device.h>
+-
+-#include "dev-gpio-buttons.h"
+-
+-void __init ath79_register_gpio_keys_polled(int id,
+- unsigned poll_interval,
+- unsigned nbuttons,
+- struct gpio_keys_button *buttons)
+-{
+- struct platform_device *pdev;
+- struct gpio_keys_platform_data pdata;
+- struct gpio_keys_button *p;
+- int err;
+-
+- p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL);
+- if (!p)
+- return;
+-
+- pdev = platform_device_alloc("gpio-keys-polled", id);
+- if (!pdev)
+- goto err_free_buttons;
+-
+- memset(&pdata, 0, sizeof(pdata));
+- pdata.poll_interval = poll_interval;
+- pdata.nbuttons = nbuttons;
+- pdata.buttons = p;
+-
+- err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+- if (err)
+- goto err_put_pdev;
+-
+- err = platform_device_add(pdev);
+- if (err)
+- goto err_put_pdev;
+-
+- return;
+-
+-err_put_pdev:
+- platform_device_put(pdev);
+-
+-err_free_buttons:
+- kfree(p);
+-}
+--- a/arch/mips/ath79/dev-gpio-buttons.h
++++ /dev/null
+@@ -1,23 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X GPIO button support
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_DEV_GPIO_BUTTONS_H
+-#define _ATH79_DEV_GPIO_BUTTONS_H
+-
+-#include <linux/input.h>
+-#include <linux/gpio_keys.h>
+-
+-void ath79_register_gpio_keys_polled(int id,
+- unsigned poll_interval,
+- unsigned nbuttons,
+- struct gpio_keys_button *buttons);
+-
+-#endif /* _ATH79_DEV_GPIO_BUTTONS_H */
+--- a/arch/mips/ath79/dev-leds-gpio.c
++++ /dev/null
+@@ -1,54 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/init.h>
+-#include <linux/slab.h>
+-#include <linux/platform_device.h>
+-
+-#include "dev-leds-gpio.h"
+-
+-void __init ath79_register_leds_gpio(int id,
+- unsigned num_leds,
+- struct gpio_led *leds)
+-{
+- struct platform_device *pdev;
+- struct gpio_led_platform_data pdata;
+- struct gpio_led *p;
+- int err;
+-
+- p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL);
+- if (!p)
+- return;
+-
+- pdev = platform_device_alloc("leds-gpio", id);
+- if (!pdev)
+- goto err_free_leds;
+-
+- memset(&pdata, 0, sizeof(pdata));
+- pdata.num_leds = num_leds;
+- pdata.leds = p;
+-
+- err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+- if (err)
+- goto err_put_pdev;
+-
+- err = platform_device_add(pdev);
+- if (err)
+- goto err_put_pdev;
+-
+- return;
+-
+-err_put_pdev:
+- platform_device_put(pdev);
+-
+-err_free_leds:
+- kfree(p);
+-}
+--- a/arch/mips/ath79/dev-leds-gpio.h
++++ /dev/null
+@@ -1,21 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_DEV_LEDS_GPIO_H
+-#define _ATH79_DEV_LEDS_GPIO_H
+-
+-#include <linux/leds.h>
+-
+-void ath79_register_leds_gpio(int id,
+- unsigned num_leds,
+- struct gpio_led *leds);
+-
+-#endif /* _ATH79_DEV_LEDS_GPIO_H */
+--- a/arch/mips/ath79/dev-spi.c
++++ /dev/null
+@@ -1,38 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X SPI controller device
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/platform_device.h>
+-#include <asm/mach-ath79/ar71xx_regs.h>
+-#include "dev-spi.h"
+-
+-static struct resource ath79_spi_resources[] = {
+- {
+- .start = AR71XX_SPI_BASE,
+- .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct platform_device ath79_spi_device = {
+- .name = "ath79-spi",
+- .id = -1,
+- .resource = ath79_spi_resources,
+- .num_resources = ARRAY_SIZE(ath79_spi_resources),
+-};
+-
+-void __init ath79_register_spi(struct ath79_spi_platform_data *pdata,
+- struct spi_board_info const *info,
+- unsigned n)
+-{
+- spi_register_board_info(info, n);
+- ath79_spi_device.dev.platform_data = pdata;
+- platform_device_register(&ath79_spi_device);
+-}
+--- a/arch/mips/ath79/dev-spi.h
++++ /dev/null
+@@ -1,22 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X SPI controller device
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_DEV_SPI_H
+-#define _ATH79_DEV_SPI_H
+-
+-#include <linux/spi/spi.h>
+-#include <asm/mach-ath79/ath79_spi_platform.h>
+-
+-void ath79_register_spi(struct ath79_spi_platform_data *pdata,
+- struct spi_board_info const *info,
+- unsigned n);
+-
+-#endif /* _ATH79_DEV_SPI_H */
+--- a/arch/mips/ath79/dev-usb.c
++++ /dev/null
+@@ -1,242 +0,0 @@
+-/*
+- * Atheros AR7XXX/AR9XXX USB Host Controller device
+- *
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * Parts of this file are based on Atheros' 2.6.15 BSP
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/delay.h>
+-#include <linux/irq.h>
+-#include <linux/dma-mapping.h>
+-#include <linux/platform_device.h>
+-#include <linux/usb/ehci_pdriver.h>
+-#include <linux/usb/ohci_pdriver.h>
+-
+-#include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/ar71xx_regs.h>
+-#include "common.h"
+-#include "dev-usb.h"
+-
+-static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
+-
+-static struct usb_ohci_pdata ath79_ohci_pdata = {
+-};
+-
+-static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
+- .has_synopsys_hc_bug = 1,
+-};
+-
+-static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
+- .caps_offset = 0x100,
+- .has_tt = 1,
+-};
+-
+-static void __init ath79_usb_register(const char *name, int id,
+- unsigned long base, unsigned long size,
+- int irq, const void *data,
+- size_t data_size)
+-{
+- struct resource res[2];
+- struct platform_device *pdev;
+-
+- memset(res, 0, sizeof(res));
+-
+- res[0].flags = IORESOURCE_MEM;
+- res[0].start = base;
+- res[0].end = base + size - 1;
+-
+- res[1].flags = IORESOURCE_IRQ;
+- res[1].start = irq;
+- res[1].end = irq;
+-
+- pdev = platform_device_register_resndata(NULL, name, id,
+- res, ARRAY_SIZE(res),
+- data, data_size);
+-
+- if (IS_ERR(pdev)) {
+- pr_err("ath79: unable to register USB at %08lx, err=%d\n",
+- base, (int) PTR_ERR(pdev));
+- return;
+- }
+-
+- pdev->dev.dma_mask = &ath79_usb_dmamask;
+- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+-}
+-
+-#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
+- AR71XX_RESET_USB_PHY | \
+- AR71XX_RESET_USB_OHCI_DLL)
+-
+-static void __init ath79_usb_setup(void)
+-{
+- void __iomem *usb_ctrl_base;
+-
+- ath79_device_reset_set(AR71XX_USB_RESET_MASK);
+- mdelay(1000);
+- ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
+-
+- usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
+-
+- /* Turning on the Buff and Desc swap bits */
+- __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
+-
+- /* WAR for HW bug. Here it adjusts the duration between two SOFS */
+- __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
+-
+- iounmap(usb_ctrl_base);
+-
+- mdelay(900);
+-
+- ath79_usb_register("ohci-platform", -1,
+- AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
+- ATH79_MISC_IRQ(6),
+- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
+-
+- ath79_usb_register("ehci-platform", -1,
+- AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
+- ATH79_CPU_IRQ(3),
+- &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
+-}
+-
+-static void __init ar7240_usb_setup(void)
+-{
+- void __iomem *usb_ctrl_base;
+-
+- ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
+- ath79_device_reset_set(AR7240_RESET_USB_HOST);
+-
+- mdelay(1000);
+-
+- ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
+- ath79_device_reset_clear(AR7240_RESET_USB_HOST);
+-
+- usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
+-
+- /* WAR for HW bug. Here it adjusts the duration between two SOFS */
+- __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
+-
+- iounmap(usb_ctrl_base);
+-
+- ath79_usb_register("ohci-platform", -1,
+- AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
+- ATH79_CPU_IRQ(3),
+- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
+-}
+-
+-static void __init ar724x_usb_setup(void)
+-{
+- ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
+- mdelay(10);
+-
+- ath79_device_reset_clear(AR724X_RESET_USB_HOST);
+- mdelay(10);
+-
+- ath79_device_reset_clear(AR724X_RESET_USB_PHY);
+- mdelay(10);
+-
+- ath79_usb_register("ehci-platform", -1,
+- AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
+- ATH79_CPU_IRQ(3),
+- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+-}
+-
+-static void __init ar913x_usb_setup(void)
+-{
+- ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
+- mdelay(10);
+-
+- ath79_device_reset_clear(AR913X_RESET_USB_HOST);
+- mdelay(10);
+-
+- ath79_device_reset_clear(AR913X_RESET_USB_PHY);
+- mdelay(10);
+-
+- ath79_usb_register("ehci-platform", -1,
+- AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
+- ATH79_CPU_IRQ(3),
+- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+-}
+-
+-static void __init ar933x_usb_setup(void)
+-{
+- ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
+- mdelay(10);
+-
+- ath79_device_reset_clear(AR933X_RESET_USB_HOST);
+- mdelay(10);
+-
+- ath79_device_reset_clear(AR933X_RESET_USB_PHY);
+- mdelay(10);
+-
+- ath79_usb_register("ehci-platform", -1,
+- AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
+- ATH79_CPU_IRQ(3),
+- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+-}
+-
+-static void __init ar934x_usb_setup(void)
+-{
+- u32 bootstrap;
+-
+- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
+- return;
+-
+- ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
+- udelay(1000);
+-
+- ath79_device_reset_clear(AR934X_RESET_USB_PHY);
+- udelay(1000);
+-
+- ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
+- udelay(1000);
+-
+- ath79_device_reset_clear(AR934X_RESET_USB_HOST);
+- udelay(1000);
+-
+- ath79_usb_register("ehci-platform", -1,
+- AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
+- ATH79_CPU_IRQ(3),
+- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+-}
+-
+-static void __init qca955x_usb_setup(void)
+-{
+- ath79_usb_register("ehci-platform", 0,
+- QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
+- ATH79_IP3_IRQ(0),
+- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+-
+- ath79_usb_register("ehci-platform", 1,
+- QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
+- ATH79_IP3_IRQ(1),
+- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+-}
+-
+-void __init ath79_register_usb(void)
+-{
+- if (soc_is_ar71xx())
+- ath79_usb_setup();
+- else if (soc_is_ar7240())
+- ar7240_usb_setup();
+- else if (soc_is_ar7241() || soc_is_ar7242())
+- ar724x_usb_setup();
+- else if (soc_is_ar913x())
+- ar913x_usb_setup();
+- else if (soc_is_ar933x())
+- ar933x_usb_setup();
+- else if (soc_is_ar934x())
+- ar934x_usb_setup();
+- else if (soc_is_qca955x())
+- qca955x_usb_setup();
+- else
+- BUG();
+-}
+--- a/arch/mips/ath79/dev-usb.h
++++ /dev/null
+@@ -1,17 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X/AR913X USB Host Controller support
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_DEV_USB_H
+-#define _ATH79_DEV_USB_H
+-
+-void ath79_register_usb(void);
+-
+-#endif /* _ATH79_DEV_USB_H */
+--- a/arch/mips/ath79/dev-wmac.c
++++ /dev/null
+@@ -1,155 +0,0 @@
+-/*
+- * Atheros AR913X/AR933X SoC built-in WMAC device support
+- *
+- * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/init.h>
+-#include <linux/delay.h>
+-#include <linux/irq.h>
+-#include <linux/platform_device.h>
+-#include <linux/ath9k_platform.h>
+-
+-#include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/ar71xx_regs.h>
+-#include "dev-wmac.h"
+-
+-static struct ath9k_platform_data ath79_wmac_data;
+-
+-static struct resource ath79_wmac_resources[] = {
+- {
+- /* .start and .end fields are filled dynamically */
+- .flags = IORESOURCE_MEM,
+- }, {
+- /* .start and .end fields are filled dynamically */
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device ath79_wmac_device = {
+- .name = "ath9k",
+- .id = -1,
+- .resource = ath79_wmac_resources,
+- .num_resources = ARRAY_SIZE(ath79_wmac_resources),
+- .dev = {
+- .platform_data = &ath79_wmac_data,
+- },
+-};
+-
+-static void __init ar913x_wmac_setup(void)
+-{
+- /* reset the WMAC */
+- ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
+- mdelay(10);
+-
+- ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
+- mdelay(10);
+-
+- ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
+- ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
+- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
+- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
+-}
+-
+-
+-static int ar933x_wmac_reset(void)
+-{
+- ath79_device_reset_set(AR933X_RESET_WMAC);
+- ath79_device_reset_clear(AR933X_RESET_WMAC);
+-
+- return 0;
+-}
+-
+-static int ar933x_r1_get_wmac_revision(void)
+-{
+- return ath79_soc_rev;
+-}
+-
+-static void __init ar933x_wmac_setup(void)
+-{
+- u32 t;
+-
+- ar933x_wmac_reset();
+-
+- ath79_wmac_device.name = "ar933x_wmac";
+-
+- ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
+- ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
+- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
+- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
+-
+- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+- ath79_wmac_data.is_clk_25mhz = false;
+- else
+- ath79_wmac_data.is_clk_25mhz = true;
+-
+- if (ath79_soc_rev == 1)
+- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
+-
+- ath79_wmac_data.external_reset = ar933x_wmac_reset;
+-}
+-
+-static void ar934x_wmac_setup(void)
+-{
+- u32 t;
+-
+- ath79_wmac_device.name = "ar934x_wmac";
+-
+- ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
+- ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
+- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
+- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
+-
+- t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+- if (t & AR934X_BOOTSTRAP_REF_CLK_40)
+- ath79_wmac_data.is_clk_25mhz = false;
+- else
+- ath79_wmac_data.is_clk_25mhz = true;
+-}
+-
+-static void qca955x_wmac_setup(void)
+-{
+- u32 t;
+-
+- ath79_wmac_device.name = "qca955x_wmac";
+-
+- ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
+- ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
+- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
+- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
+-
+- t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
+- if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
+- ath79_wmac_data.is_clk_25mhz = false;
+- else
+- ath79_wmac_data.is_clk_25mhz = true;
+-}
+-
+-void __init ath79_register_wmac(u8 *cal_data)
+-{
+- if (soc_is_ar913x())
+- ar913x_wmac_setup();
+- else if (soc_is_ar933x())
+- ar933x_wmac_setup();
+- else if (soc_is_ar934x())
+- ar934x_wmac_setup();
+- else if (soc_is_qca955x())
+- qca955x_wmac_setup();
+- else
+- BUG();
+-
+- if (cal_data)
+- memcpy(ath79_wmac_data.eeprom_data, cal_data,
+- sizeof(ath79_wmac_data.eeprom_data));
+-
+- platform_device_register(&ath79_wmac_device);
+-}
+--- a/arch/mips/ath79/dev-wmac.h
++++ /dev/null
+@@ -1,17 +0,0 @@
+-/*
+- * Atheros AR913X/AR933X SoC built-in WMAC device support
+- *
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_DEV_WMAC_H
+-#define _ATH79_DEV_WMAC_H
+-
+-void ath79_register_wmac(u8 *cal_data);
+-
+-#endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -32,7 +32,6 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "common.h"
+-#include "dev-common.h"
+
+ #define ATH79_SYS_TYPE_LEN 64
+
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Tue, 6 Mar 2018 13:23:20 +0100
-Subject: [PATCH] MIPS: ath79: pass PLL base to clock init functions
-
-Preparation for passing the mapped base via DT
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -79,7 +79,7 @@ static struct clk * __init ath79_set_ff_
- return clk;
- }
-
--static void __init ar71xx_clocks_init(void)
-+static void __init ar71xx_clocks_init(void __iomem *pll_base)
- {
- unsigned long ref_rate;
- unsigned long cpu_rate;
-@@ -91,7 +91,7 @@ static void __init ar71xx_clocks_init(vo
-
- ref_rate = AR71XX_BASE_FREQ;
-
-- pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
-+ pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
-
- div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
- freq = div * ref_rate;
-@@ -129,13 +129,13 @@ static void __init ar724x_clk_init(struc
- ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
- }
-
--static void __init ar724x_clocks_init(void)
-+static void __init ar724x_clocks_init(void __iomem *pll_base)
- {
- struct clk *ref_clk;
-
- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
-
-- ar724x_clk_init(ref_clk, ath79_pll_base);
-+ ar724x_clk_init(ref_clk, pll_base);
- }
-
- static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-@@ -196,7 +196,7 @@ static void __init ar9330_clk_init(struc
- ref_div * out_div * ahb_div);
- }
-
--static void __init ar933x_clocks_init(void)
-+static void __init ar933x_clocks_init(void __iomem *pll_base)
- {
- struct clk *ref_clk;
- unsigned long ref_rate;
-@@ -233,7 +233,7 @@ static u32 __init ar934x_get_pll_freq(u3
- return ret;
- }
-
--static void __init ar934x_clocks_init(void)
-+static void __init ar934x_clocks_init(void __iomem *pll_base)
- {
- unsigned long ref_rate;
- unsigned long cpu_rate;
-@@ -264,7 +264,7 @@ static void __init ar934x_clocks_init(vo
- AR934X_SRIF_DPLL1_REFDIV_MASK;
- frac = 1 << 18;
- } else {
-- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
-+ pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-@@ -291,7 +291,7 @@ static void __init ar934x_clocks_init(vo
- AR934X_SRIF_DPLL1_REFDIV_MASK;
- frac = 1 << 18;
- } else {
-- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
-+ pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
- out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-@@ -306,7 +306,7 @@ static void __init ar934x_clocks_init(vo
- ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
- nfrac, frac, out_div);
-
-- clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
-+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
-
- postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
-@@ -346,7 +346,7 @@ static void __init ar934x_clocks_init(vo
- iounmap(dpll_base);
- }
-
--static void __init qca953x_clocks_init(void)
-+static void __init qca953x_clocks_init(void __iomem *pll_base)
- {
- unsigned long ref_rate;
- unsigned long cpu_rate;
-@@ -362,7 +362,7 @@ static void __init qca953x_clocks_init(v
- else
- ref_rate = 25 * 1000 * 1000;
-
-- pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
-+ pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-@@ -376,7 +376,7 @@ static void __init qca953x_clocks_init(v
- cpu_pll += frac * (ref_rate >> 6) / ref_div;
- cpu_pll /= (1 << out_div);
-
-- pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
-+ pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
- out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-@@ -390,7 +390,7 @@ static void __init qca953x_clocks_init(v
- ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
- ddr_pll /= (1 << out_div);
-
-- clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
-+ clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
-
- postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-@@ -428,7 +428,7 @@ static void __init qca953x_clocks_init(v
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- }
-
--static void __init qca955x_clocks_init(void)
-+static void __init qca955x_clocks_init(void __iomem *pll_base)
- {
- unsigned long ref_rate;
- unsigned long cpu_rate;
-@@ -444,7 +444,7 @@ static void __init qca955x_clocks_init(v
- else
- ref_rate = 25 * 1000 * 1000;
-
-- pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
-+ pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-@@ -458,7 +458,7 @@ static void __init qca955x_clocks_init(v
- cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
- cpu_pll /= (1 << out_div);
-
-- pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
-+ pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
- out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-@@ -472,7 +472,7 @@ static void __init qca955x_clocks_init(v
- ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
- ddr_pll /= (1 << out_div);
-
-- clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
-+ clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
-
- postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-@@ -510,7 +510,7 @@ static void __init qca955x_clocks_init(v
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- }
-
--static void __init qca956x_clocks_init(void)
-+static void __init qca956x_clocks_init(void __iomem *pll_base)
- {
- unsigned long ref_rate;
- unsigned long cpu_rate;
-@@ -526,13 +526,13 @@ static void __init qca956x_clocks_init(v
- else
- ref_rate = 25 * 1000 * 1000;
-
-- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
-+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
- QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
-
-- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
-+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
- nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
- QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
- hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
-@@ -545,12 +545,12 @@ static void __init qca956x_clocks_init(v
- cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
- cpu_pll /= (1 << out_div);
-
-- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
-+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
- out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
- QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
-- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
-+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
- nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
- QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
- hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
-@@ -563,7 +563,7 @@ static void __init qca956x_clocks_init(v
- ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
- ddr_pll /= (1 << out_div);
-
-- clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
-+ clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
-
- postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-@@ -607,19 +607,19 @@ void __init ath79_clocks_init(void)
- const char *uart;
-
- if (soc_is_ar71xx())
-- ar71xx_clocks_init();
-+ ar71xx_clocks_init(ath79_pll_base);
- else if (soc_is_ar724x() || soc_is_ar913x())
-- ar724x_clocks_init();
-+ ar724x_clocks_init(ath79_pll_base);
- else if (soc_is_ar933x())
-- ar933x_clocks_init();
-+ ar933x_clocks_init(ath79_pll_base);
- else if (soc_is_ar934x())
-- ar934x_clocks_init();
-+ ar934x_clocks_init(ath79_pll_base);
- else if (soc_is_qca953x())
-- qca953x_clocks_init();
-+ qca953x_clocks_init(ath79_pll_base);
- else if (soc_is_qca955x())
-- qca955x_clocks_init();
-+ qca955x_clocks_init(ath79_pll_base);
- else if (soc_is_qca956x() || soc_is_tp9343())
-- qca956x_clocks_init();
-+ qca956x_clocks_init(ath79_pll_base);
- else
- BUG();
-
--- /dev/null
+From 00e4313da4609074fff134e61dd9ffe3fd37474d Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sun, 24 Jun 2018 09:39:41 +0200
+Subject: [PATCH 31/33] MIPS: ath79: drop !OF clock code
+
+With the target now being fully OF based, we can drop the legacy clock
+registration code. All clocks are now probed via devicetree.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/clock.c | 56 ------------------------------------------------
+ arch/mips/ath79/common.h | 3 ---
+ 2 files changed, 59 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -617,60 +617,6 @@ static void __init qca956x_clocks_init(v
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+ }
+
+-void __init ath79_clocks_init(void)
+-{
+- const char *wdt;
+- const char *uart;
+-
+- if (soc_is_ar71xx())
+- ar71xx_clocks_init(ath79_pll_base);
+- else if (soc_is_ar724x() || soc_is_ar913x())
+- ar724x_clocks_init(ath79_pll_base);
+- else if (soc_is_ar933x())
+- ar933x_clocks_init(ath79_pll_base);
+- else if (soc_is_ar934x())
+- ar934x_clocks_init(ath79_pll_base);
+- else if (soc_is_qca953x())
+- qca953x_clocks_init(ath79_pll_base);
+- else if (soc_is_qca955x())
+- qca955x_clocks_init(ath79_pll_base);
+- else if (soc_is_qca956x() || soc_is_tp9343())
+- qca956x_clocks_init(ath79_pll_base);
+- else
+- BUG();
+-
+- if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
+- wdt = "ahb";
+- uart = "ahb";
+- } else if (soc_is_ar933x()) {
+- wdt = "ahb";
+- uart = "ref";
+- } else {
+- wdt = "ref";
+- uart = "ref";
+- }
+-
+- clk_add_alias("wdt", NULL, wdt, NULL);
+- clk_add_alias("uart", NULL, uart, NULL);
+-}
+-
+-unsigned long __init
+-ath79_get_sys_clk_rate(const char *id)
+-{
+- struct clk *clk;
+- unsigned long rate;
+-
+- clk = clk_get(NULL, id);
+- if (IS_ERR(clk))
+- panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
+-
+- rate = clk_get_rate(clk);
+- clk_put(clk);
+-
+- return rate;
+-}
+-
+-#ifdef CONFIG_OF
+ static void __init ath79_clocks_init_dt(struct device_node *np)
+ {
+ struct clk *ref_clk;
+@@ -727,5 +673,3 @@ CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-p
+ CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
+ CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
+ CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
+-
+-#endif
+--- a/arch/mips/ath79/common.h
++++ b/arch/mips/ath79/common.h
+@@ -19,9 +19,6 @@
+ #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
+ #define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024)
+
+-void ath79_clocks_init(void);
+-unsigned long ath79_get_sys_clk_rate(const char *id);
+-
+ void ath79_ddr_ctrl_init(void);
+
+ #endif /* __ATH79_COMMON_H */
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Tue, 6 Mar 2018 13:24:07 +0100
-Subject: [PATCH] MIPS: ath79: make specifying the reference clock in DT
- optional
-
-It can be autodetected for many SoCs using the strapping options.
-If the clock is specified in DT, the autodetected value is ignored
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -79,6 +79,18 @@ static struct clk * __init ath79_set_ff_
- return clk;
- }
-
-+static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
-+{
-+ struct clk *clk = clks[ATH79_CLK_REF];
-+
-+ if (clk)
-+ rate = clk_get_rate(clk);
-+ else
-+ clk = ath79_set_clk(ATH79_CLK_REF, rate);
-+
-+ return rate;
-+}
-+
- static void __init ar71xx_clocks_init(void __iomem *pll_base)
- {
- unsigned long ref_rate;
-@@ -89,7 +101,7 @@ static void __init ar71xx_clocks_init(vo
- u32 freq;
- u32 div;
-
-- ref_rate = AR71XX_BASE_FREQ;
-+ ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
-
- pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
-
-@@ -105,16 +117,17 @@ static void __init ar71xx_clocks_init(vo
- div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
- ahb_rate = cpu_rate / div;
-
-- ath79_set_clk(ATH79_CLK_REF, ref_rate);
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- }
-
--static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-+static void __init ar724x_clocks_init(void __iomem *pll_base)
- {
-- u32 pll;
- u32 mult, div, ddr_div, ahb_div;
-+ u32 pll;
-+
-+ ath79_setup_ref_clk(AR71XX_BASE_FREQ);
-
- pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
-
-@@ -129,17 +142,9 @@ static void __init ar724x_clk_init(struc
- ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
- }
-
--static void __init ar724x_clocks_init(void __iomem *pll_base)
--{
-- struct clk *ref_clk;
--
-- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
--
-- ar724x_clk_init(ref_clk, pll_base);
--}
--
--static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-+static void __init ar933x_clocks_init(void __iomem *pll_base)
- {
-+ unsigned long ref_rate;
- u32 clock_ctrl;
- u32 ref_div;
- u32 ninit_mul;
-@@ -148,6 +153,15 @@ static void __init ar9330_clk_init(struc
- u32 cpu_div;
- u32 ddr_div;
- u32 ahb_div;
-+ u32 t;
-+
-+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
-+ ref_rate = (40 * 1000 * 1000);
-+ else
-+ ref_rate = (25 * 1000 * 1000);
-+
-+ ath79_setup_ref_clk(ref_rate);
-
- clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
- if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
-@@ -196,23 +210,6 @@ static void __init ar9330_clk_init(struc
- ref_div * out_div * ahb_div);
- }
-
--static void __init ar933x_clocks_init(void __iomem *pll_base)
--{
-- struct clk *ref_clk;
-- unsigned long ref_rate;
-- u32 t;
--
-- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
-- ref_rate = (40 * 1000 * 1000);
-- else
-- ref_rate = (25 * 1000 * 1000);
--
-- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
--
-- ar9330_clk_init(ref_clk, ath79_pll_base);
--}
--
- static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
- u32 frac, u32 out_div)
- {
-@@ -252,6 +249,8 @@ static void __init ar934x_clocks_init(vo
- else
- ref_rate = 25 * 1000 * 1000;
-
-+ ref_rate = ath79_setup_ref_clk(ref_rate);
-+
- pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
- if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
- out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
-@@ -338,7 +337,6 @@ static void __init ar934x_clocks_init(vo
- else
- ahb_rate = cpu_pll / (postdiv + 1);
-
-- ath79_set_clk(ATH79_CLK_REF, ref_rate);
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-@@ -362,6 +360,8 @@ static void __init qca953x_clocks_init(v
- else
- ref_rate = 25 * 1000 * 1000;
-
-+ ref_rate = ath79_setup_ref_clk(ref_rate);
-+
- pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
-@@ -422,7 +422,6 @@ static void __init qca953x_clocks_init(v
- else
- ahb_rate = cpu_pll / (postdiv + 1);
-
-- ath79_set_clk(ATH79_CLK_REF, ref_rate);
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-@@ -444,6 +443,8 @@ static void __init qca955x_clocks_init(v
- else
- ref_rate = 25 * 1000 * 1000;
-
-+ ref_rate = ath79_setup_ref_clk(ref_rate);
-+
- pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
-@@ -504,7 +505,6 @@ static void __init qca955x_clocks_init(v
- else
- ahb_rate = cpu_pll / (postdiv + 1);
-
-- ath79_set_clk(ATH79_CLK_REF, ref_rate);
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-@@ -526,6 +526,8 @@ static void __init qca956x_clocks_init(v
- else
- ref_rate = 25 * 1000 * 1000;
-
-+ ref_rate = ath79_setup_ref_clk(ref_rate);
-+
- pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
-@@ -595,7 +597,6 @@ static void __init qca956x_clocks_init(v
- else
- ahb_rate = cpu_pll / (postdiv + 1);
-
-- ath79_set_clk(ATH79_CLK_REF, ref_rate);
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-@@ -671,10 +672,8 @@ static void __init ath79_clocks_init_dt_
- void __iomem *pll_base;
-
- ref_clk = of_clk_get(np, 0);
-- if (IS_ERR(ref_clk)) {
-- pr_err("%pOF: of_clk_get failed\n", np);
-- goto err;
-- }
-+ if (!IS_ERR(ref_clk))
-+ clks[ATH79_CLK_REF] = ref_clk;
-
- pll_base = of_iomap(np, 0);
- if (!pll_base) {
-@@ -683,9 +682,9 @@ static void __init ath79_clocks_init_dt_
- }
-
- if (of_device_is_compatible(np, "qca,ar9130-pll"))
-- ar724x_clk_init(ref_clk, pll_base);
-+ ar724x_clocks_init(pll_base);
- else if (of_device_is_compatible(np, "qca,ar9330-pll"))
-- ar9330_clk_init(ref_clk, pll_base);
-+ ar933x_clocks_init(pll_base);
- else {
- pr_err("%pOF: could not find any appropriate clk_init()\n", np);
- goto err_iounmap;
-@@ -703,9 +702,6 @@ err_iounmap:
-
- err_clk:
- clk_put(ref_clk);
--
--err:
-- return;
- }
- CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
- CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
--- /dev/null
+From 3fc8585cf76022dba7496627074d42af88c30718 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:16:55 +0200
+Subject: [PATCH 32/33] MIPS: ath79: sanitize symbols
+
+We no longer need to select which SoCs are supported as the whole arch
+code is always built. So lets drop all the SoC symbols
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/Kconfig | 2 ++
+ arch/mips/ath79/Kconfig | 44 +++++---------------------------------------
+ arch/mips/pci/Makefile | 2 +-
+ 3 files changed, 8 insertions(+), 40 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -202,6 +202,8 @@ config ATH79
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_MIPS16
+ select SYS_SUPPORTS_ZBOOT_UART_PROM
++ select HW_HAS_PCI
++ select USB_ARCH_HAS_EHCI
+ select USE_OF
+ help
+ Support for the Atheros AR71XX/AR724X/AR913X SoCs.
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -1,48 +1,14 @@
+ # SPDX-License-Identifier: GPL-2.0
+ if ATH79
+
+-config SOC_AR71XX
+- select HW_HAS_PCI
+- def_bool n
+-
+-config SOC_AR724X
+- select HW_HAS_PCI
+- select PCI_AR724X if PCI
+- def_bool n
+-
+-config SOC_AR913X
+- def_bool n
+-
+-config SOC_AR933X
+- def_bool n
+-
+-config SOC_AR934X
+- select HW_HAS_PCI
+- select PCI_AR724X if PCI
+- def_bool n
+-
+-config SOC_QCA955X
+- select HW_HAS_PCI
+- select PCI_AR724X if PCI
++config PCI_AR71XX
++ bool "PCI support for AR7100 type SoCs"
++ depends on PCI
+ def_bool n
+
+ config PCI_AR724X
+- def_bool n
+-
+-config ATH79_DEV_GPIO_BUTTONS
+- def_bool n
+-
+-config ATH79_DEV_LEDS_GPIO
+- def_bool n
+-
+-config ATH79_DEV_SPI
+- def_bool n
+-
+-config ATH79_DEV_USB
+- def_bool n
+-
+-config ATH79_DEV_WMAC
+- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
++ bool "PCI support for AR724x type SoCs"
++ depends on PCI
+ def_bool n
+
+ endif
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -23,7 +23,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o
+ ops-bcm63xx.o
+ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
+ obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
+-obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
++obj-$(CONFIG_PCI_AR71XX) += pci-ar71xx.o
+ obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
+ obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
+ #
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Tue, 6 Mar 2018 13:26:27 +0100
-Subject: [PATCH] MIPS: ath79: support setting up clock via DT on all SoC
- types
-
-Use the same functions as the legacy code
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -658,16 +658,6 @@ ath79_get_sys_clk_rate(const char *id)
- #ifdef CONFIG_OF
- static void __init ath79_clocks_init_dt(struct device_node *np)
- {
-- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
--}
--
--CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
--CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
--CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
--CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
--
--static void __init ath79_clocks_init_dt_ng(struct device_node *np)
--{
- struct clk *ref_clk;
- void __iomem *pll_base;
-
-@@ -681,14 +671,21 @@ static void __init ath79_clocks_init_dt_
- goto err_clk;
- }
-
-- if (of_device_is_compatible(np, "qca,ar9130-pll"))
-+ if (of_device_is_compatible(np, "qca,ar7100-pll"))
-+ ar71xx_clocks_init(pll_base);
-+ else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
-+ of_device_is_compatible(np, "qca,ar9130-pll"))
- ar724x_clocks_init(pll_base);
- else if (of_device_is_compatible(np, "qca,ar9330-pll"))
- ar933x_clocks_init(pll_base);
-- else {
-- pr_err("%pOF: could not find any appropriate clk_init()\n", np);
-- goto err_iounmap;
-- }
-+ else if (of_device_is_compatible(np, "qca,ar9340-pll"))
-+ ar934x_clocks_init(pll_base);
-+ else if (of_device_is_compatible(np, "qca,qca9530-pll"))
-+ qca953x_clocks_init(pll_base);
-+ else if (of_device_is_compatible(np, "qca,qca9550-pll"))
-+ qca955x_clocks_init(pll_base);
-+ else if (of_device_is_compatible(np, "qca,qca9560-pll"))
-+ qca956x_clocks_init(pll_base);
-
- if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
- pr_err("%pOF: could not register clk provider\n", np);
-@@ -703,6 +700,14 @@ err_iounmap:
- err_clk:
- clk_put(ref_clk);
- }
--CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
--CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
-+
-+CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
-+CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
-+
- #endif
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Tue, 6 Mar 2018 13:27:28 +0100
-Subject: [PATCH] MIPS: ath79: export switch MDIO reference clock
-
-On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
-clock. If that feature is not used, it defaults to the main reference clock,
-like on all other SoC.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -41,6 +41,7 @@ static const char * const clk_names[ATH7
- [ATH79_CLK_DDR] = "ddr",
- [ATH79_CLK_AHB] = "ahb",
- [ATH79_CLK_REF] = "ref",
-+ [ATH79_CLK_MDIO] = "mdio",
- };
-
- static const char * __init ath79_clk_name(int type)
-@@ -341,6 +342,10 @@ static void __init ar934x_clocks_init(vo
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
-+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
-+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
-+ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
-+
- iounmap(dpll_base);
- }
-
-@@ -687,6 +692,9 @@ static void __init ath79_clocks_init_dt(
- else if (of_device_is_compatible(np, "qca,qca9560-pll"))
- qca956x_clocks_init(pll_base);
-
-+ if (!clks[ATH79_CLK_MDIO])
-+ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
-+
- if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
- pr_err("%pOF: could not register clk provider\n", np);
- goto err_iounmap;
---- a/include/dt-bindings/clock/ath79-clk.h
-+++ b/include/dt-bindings/clock/ath79-clk.h
-@@ -14,7 +14,8 @@
- #define ATH79_CLK_DDR 1
- #define ATH79_CLK_AHB 2
- #define ATH79_CLK_REF 3
-+#define ATH79_CLK_MDIO 4
-
--#define ATH79_CLK_END 4
-+#define ATH79_CLK_END 5
-
- #endif /* __DT_BINDINGS_ATH79_CLK_H */
--- /dev/null
+From c4e197bbcecc7233aa9e553e7047fa50e4e1fe77 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Mon, 25 Jun 2018 15:52:34 +0200
+Subject: [PATCH 33/33] spi: ath79: drop pdata support
+
+The target is being converted to pure OF. We can therefore drop all of the
+platform data code from the driver.
+
+Cc: linux-spi@vger.kernel.org
+Acked-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/include/asm/mach-ath79/ath79_spi_platform.h | 19 -------------------
+ drivers/spi/spi-ath79.c | 8 --------
+ 2 files changed, 27 deletions(-)
+ delete mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+
+--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
++++ /dev/null
+@@ -1,19 +0,0 @@
+-/*
+- * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller
+- *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_SPI_PLATFORM_H
+-#define _ATH79_SPI_PLATFORM_H
+-
+-struct ath79_spi_platform_data {
+- unsigned bus_num;
+- unsigned num_chipselect;
+-};
+-
+-#endif /* _ATH79_SPI_PLATFORM_H */
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -26,7 +26,6 @@
+ #include <linux/err.h>
+
+ #include <asm/mach-ath79/ar71xx_regs.h>
+-#include <asm/mach-ath79/ath79_spi_platform.h>
+
+ #define DRV_NAME "ath79-spi"
+
+@@ -208,7 +207,6 @@ static int ath79_spi_probe(struct platfo
+ {
+ struct spi_master *master;
+ struct ath79_spi *sp;
+- struct ath79_spi_platform_data *pdata;
+ struct resource *r;
+ unsigned long rate;
+ int ret;
+@@ -223,15 +221,9 @@ static int ath79_spi_probe(struct platfo
+ master->dev.of_node = pdev->dev.of_node;
+ platform_set_drvdata(pdev, sp);
+
+- pdata = dev_get_platdata(&pdev->dev);
+-
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
+ master->setup = ath79_spi_setup;
+ master->cleanup = ath79_spi_cleanup;
+- if (pdata) {
+- master->bus_num = pdata->bus_num;
+- master->num_chipselect = pdata->num_chipselect;
+- }
+
+ sp->bitbang.master = master;
+ sp->bitbang.chipselect = ath79_spi_chipselect;
+++ /dev/null
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -525,6 +525,14 @@ static void __init qca956x_clocks_init(v
- u32 cpu_pll, ddr_pll;
- u32 bootstrap;
-
-+ /* QCA956x timer init workaround has to be applied right before setting
-+ * up the clock. Else, there will be no jiffies */
-+ u32 misc;
-+
-+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
-+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
-+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
-+
- bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
- if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
- ref_rate = 40 * 1000 * 1000;
--- /dev/null
+From 4267880319bc1a2270d352e0ded6d6386242a7ef Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 12 Aug 2014 20:49:27 +0200
+Subject: [PATCH 24/53] GPIO: add named gpio exports
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
+ drivers/gpio/gpiolib-sysfs.c | 10 +++++-
+ include/asm-generic/gpio.h | 6 ++++
+ include/linux/gpio/consumer.h | 8 +++++
+ 4 files changed, 91 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/gpiolib-of.c
++++ b/drivers/gpio/gpiolib-of.c
+@@ -23,6 +23,8 @@
+ #include <linux/pinctrl/pinctrl.h>
+ #include <linux/slab.h>
+ #include <linux/gpio/machine.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
+
+ #include "gpiolib.h"
+
+@@ -506,3 +508,68 @@ void of_gpiochip_remove(struct gpio_chip
+ gpiochip_remove_pin_ranges(chip);
+ of_node_put(chip->of_node);
+ }
++
++static struct of_device_id gpio_export_ids[] = {
++ { .compatible = "gpio-export" },
++ { /* sentinel */ }
++};
++
++static int of_gpio_export_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct device_node *cnp;
++ u32 val;
++ int nb = 0;
++
++ for_each_child_of_node(np, cnp) {
++ const char *name = NULL;
++ int gpio;
++ bool dmc;
++ int max_gpio = 1;
++ int i;
++
++ of_property_read_string(cnp, "gpio-export,name", &name);
++
++ if (!name)
++ max_gpio = of_gpio_count(cnp);
++
++ for (i = 0; i < max_gpio; i++) {
++ unsigned flags = 0;
++ enum of_gpio_flags of_flags;
++
++ gpio = of_get_gpio_flags(cnp, i, &of_flags);
++ if (!gpio_is_valid(gpio))
++ return gpio;
++
++ if (of_flags == OF_GPIO_ACTIVE_LOW)
++ flags |= GPIOF_ACTIVE_LOW;
++
++ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
++ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++ else
++ flags |= GPIOF_IN;
++
++ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
++ continue;
++
++ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
++ gpio_export_with_name(gpio, dmc, name);
++ nb++;
++ }
++ }
++
++ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
++
++ return 0;
++}
++
++static struct platform_driver gpio_export_driver = {
++ .driver = {
++ .name = "gpio-export",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(gpio_export_ids),
++ },
++ .probe = of_gpio_export_probe,
++};
++
++module_platform_driver(gpio_export_driver);
+--- a/drivers/gpio/gpiolib-sysfs.c
++++ b/drivers/gpio/gpiolib-sysfs.c
+@@ -553,7 +553,7 @@ static struct class gpio_class = {
+ *
+ * Returns zero on success, else an error.
+ */
+-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
+ {
+ struct gpio_chip *chip;
+ struct gpio_device *gdev;
+@@ -615,6 +615,8 @@ int gpiod_export(struct gpio_desc *desc,
+ offset = gpio_chip_hwgpio(desc);
+ if (chip->names && chip->names[offset])
+ ioname = chip->names[offset];
++ if (name)
++ ioname = name;
+
+ dev = device_create_with_groups(&gpio_class, &gdev->dev,
+ MKDEV(0, 0), data, gpio_groups,
+@@ -636,6 +638,12 @@ err_unlock:
+ gpiod_dbg(desc, "%s: status %d\n", __func__, status);
+ return status;
+ }
++EXPORT_SYMBOL_GPL(__gpiod_export);
++
++int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++{
++ return __gpiod_export(desc, direction_may_change, NULL);
++}
+ EXPORT_SYMBOL_GPL(gpiod_export);
+
+ static int match_export(struct device *dev, const void *desc)
+--- a/include/asm-generic/gpio.h
++++ b/include/asm-generic/gpio.h
+@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g
+ return gpiod_export(gpio_to_desc(gpio), direction_may_change);
+ }
+
++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
++static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
++{
++ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
++}
++
+ static inline int gpio_export_link(struct device *dev, const char *name,
+ unsigned gpio)
+ {
+--- a/include/linux/gpio/consumer.h
++++ b/include/linux/gpio/consumer.h
+@@ -451,6 +451,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_
+
+ #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
+
++int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
+ int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
+ int gpiod_export_link(struct device *dev, const char *name,
+ struct gpio_desc *desc);
+@@ -458,6 +459,13 @@ void gpiod_unexport(struct gpio_desc *de
+
+ #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
+
++static inline int _gpiod_export(struct gpio_desc *desc,
++ bool direction_may_change,
++ const char *name)
++{
++ return -ENOSYS;
++}
++
+ static inline int gpiod_export(struct gpio_desc *desc,
+ bool direction_may_change)
+ {
--- /dev/null
+commit f3ffac90bc7266b7d917616f3233f58e8c08a196
+Author: Christian Lamparter <chunkeey@gmail.com>
+Date: Fri Aug 10 23:24:47 2018 +0200
+
+ ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344
+
+ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+
+Index: linux-4.14.65/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+===================================================================
+--- linux-4.14.65.orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ linux-4.14.65/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1229,6 +1229,10 @@
+ #define AR934X_ETH_CFG_RDV_DELAY BIT(16)
+ #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
+ #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
++#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3
++#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18
++#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3
++#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20
+
+ /*
+ * QCA953X GMAC Interface
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
-@@ -102,9 +102,6 @@ static void ath79_spi_enable(struct ath7
+@@ -101,9 +101,6 @@ static void ath79_spi_enable(struct ath7
/* save CTRL register */
sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
}
static void ath79_spi_disable(struct ath79_spi *sp)
-@@ -204,6 +201,38 @@ static u32 ath79_spi_txrx_mode0(struct s
+@@ -203,6 +200,38 @@ static u32 ath79_spi_txrx_mode0(struct s
return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
}
static int ath79_spi_probe(struct platform_device *pdev)
{
struct spi_master *master;
-@@ -232,6 +261,8 @@ static int ath79_spi_probe(struct platfo
- master->bus_num = pdata->bus_num;
- master->num_chipselect = pdata->num_chipselect;
+@@ -237,6 +266,8 @@ static int ath79_spi_probe(struct platfo
+ ret = PTR_ERR(sp->base);
+ goto err_put_master;
}
+ master->spi_flash_read = ath79_spi_read_flash_data;
+ master->flash_read_supported = ath79_spi_flash_read_supported;
- sp->bitbang.master = master;
- sp->bitbang.chipselect = ath79_spi_chipselect;
+ sp->clk = devm_clk_get(&pdev->dev, "ahb");
+ if (IS_ERR(sp->clk)) {
static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
{
u32 t;
-@@ -384,6 +423,9 @@ static int ar71xx_pci_probe(struct platf
+@@ -385,6 +424,9 @@ static int ar71xx_pci_probe(struct platf
register_pci_controller(&apc->pci_ctrl);
projects / openwrt / openwrt.git / commitdiff