GIC: Do not flush cache when unneeded

When a platform enables its caches before it initializes the
GICC/GICR interface then explicit cache maintenance is not
needed. Remove these here.

Signed-off-by: Andrew F. Davis <afd@ti.com>

diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index bbe73fb954cfef5adc369f7b955fa291048d60b8..7cf6c76e3a604620a0962267400ca2702ab6b62f 100644 (file)
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -221,9 +221,10 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
         * enabled. When the secondary CPU boots up, it initializes the
         * GICC/GICR interface with the caches disabled. Hence flush the
         * driver_data to ensure coherency. This is not required if the
-        * platform has HW_ASSISTED_COHERENCY enabled.
+        * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
+        * enabled.
         */
-#if !HW_ASSISTED_COHERENCY
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
        flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data));
        flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data));
 #endif
@@ -360,7 +361,7 @@ void gicv2_set_pe_target_mask(unsigned int proc_num)
        if (driver_data->target_masks[proc_num] == 0) {
                driver_data->target_masks[proc_num] =
                        gicv2_get_cpuif_id(driver_data->gicd_base);
-#if !HW_ASSISTED_COHERENCY
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
                /*
                 * PEs only update their own masks. Primary updates it with
                 * caches on. But because secondaries does it with caches off,

diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 83d030a86adc31389c6b84afa295406180a6a656..40d14aba27f42c32f7535bea8d3415a443350427 100644 (file)
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -147,9 +147,10 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
         * enabled. When the secondary CPU boots up, it initializes the
         * GICC/GICR interface with the caches disabled. Hence flush the
         * driver data to ensure coherency. This is not required if the
-        * platform has HW_ASSISTED_COHERENCY enabled.
+        * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
+        * enabled.
         */
-#if !HW_ASSISTED_COHERENCY
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
        flush_dcache_range((uintptr_t) &gicv3_driver_data,
                        sizeof(gicv3_driver_data));
        flush_dcache_range((uintptr_t) gicv3_driver_data,