ramips: re-implement PCI mux

Parallel flash access on RT3662/RT3883 based devices
is broken without that. It was fixed already some time
ago, but that change seems lost somewhere.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 37708

diff --git a/target/linux/ramips/patches-3.10/0002-MIPS-ralink-add-pinmux-driver.patch b/target/linux/ramips/patches-3.10/0002-MIPS-ralink-add-pinmux-driver.patch
index 1d17e4d54fa1101f3883669d1f032eb56e89cb52..67dd69db40e7a88bff410411f6d726c61f1f87a3 100644 (file)
--- a/target/linux/ramips/patches-3.10/0002-MIPS-ralink-add-pinmux-driver.patch
+++ b/target/linux/ramips/patches-3.10/0002-MIPS-ralink-add-pinmux-driver.patch
@@ -49,7 +49,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
 --- /dev/null
 +++ b/arch/mips/ralink/pinmux.c
-@@ -0,0 +1,77 @@
+@@ -0,0 +1,92 @@
 +/*
 + *  This program is free software; you can redistribute it and/or modify it
 + *  under the terms of the GNU General Public License version 2 as published
@@ -83,7 +83,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +      const __be32 *wdt;
 +      struct device_node *np;
 +      struct property *prop;
-+      const char *uart, *pin;
++      const char *uart, *pci, *pin;
 +      u32 mode = 0;
 +      int m;
 +
@@ -125,5 +125,20 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +      if (wdt && *wdt && rt_gpio_pinmux.wdt_reset)
 +              rt_gpio_pinmux.wdt_reset();
 +
++      pci = NULL;
++      if (rt_gpio_pinmux.pci)
++              of_property_read_string(np, "ralink,pcimux", &pci);
++
++      if (pci) {
++              mode &= ~(rt_gpio_pinmux.pci_mask << rt_gpio_pinmux.pci_shift);
++              if (ralink_mux_mask(pci, rt_gpio_pinmux.pci, &m)) {
++                      mode |= rt_gpio_pinmux.pci_mask << rt_gpio_pinmux.pci_shift;
++                      pr_debug("pinmux: failed to load pcimux \"%s\"\n", pci);
++              } else {
++                      mode |= m << rt_gpio_pinmux.pci_shift;
++                      pr_debug("pinmux: registered pcimux \"%s\"\n", pci);
++              }
++      }
++
 +      rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
 +}