drm/i915/skl: Implement WaSetGAPSunitClckGateDisable
authorDamien Lespiau <damien.lespiau@intel.com>
Mon, 9 Feb 2015 19:33:10 +0000 (19:33 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 13 Feb 2015 22:28:33 +0000 (23:28 +0100)
Let's also take the opportunity the remove the comment telling it's a
pre-prod W/A, it should be obvious from the stepping test.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c

index 5de6cf450e1a4dc2b685ca546d4dce30f68c1dd6..b00d323095af79709a3ad5b704c212e2c431a6ce 100644 (file)
@@ -6018,6 +6018,7 @@ enum skl_disp_power_wells {
 #define GEN6_RSTCTL                            0x9420
 
 #define GEN8_UCGCTL6                           0x9430
+#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE     (1<<24)
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE      (1<<14)
 
 #define GEN6_GFXPAUSE                          0xA000
index b162c5c288bb0e9648acb5153dd83e741e7c5aaa..af8dca28c5053220869c1ba773c38b30e9a3aed5 100644 (file)
@@ -59,9 +59,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
        if (INTEL_REVID(dev) == SKL_REVID_A0) {
                /*
                 * WaDisableSDEUnitClockGating:skl
-                * This seems to be a pre-production w/a.
+                * WaSetGAPSunitClckGateDisable:skl
                 */
                I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+                          GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
                           GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
        }
 }