ice: Update comment regarding the ITR_GRAN_S
authorBrett Creeley <brett.creeley@intel.com>
Tue, 19 Feb 2019 23:04:10 +0000 (15:04 -0800)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Tue, 26 Mar 2019 22:22:44 +0000 (15:22 -0700)
Since the driver now hard codes the ITR granularity to 2 us in the
GLINT_CTL register the comment next to ITR_GRAN_S needs to be updated.

Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/ice/ice_txrx.h

index 2c8af98ff6405d961421047ded47a43af9383c6b..60131b84b0215d6371cf32beb5138563952657f7 100644 (file)
@@ -128,7 +128,7 @@ enum ice_rx_dtype {
 #define ICE_ITR_DYNAMIC        0x8000  /* used as flag for itr_setting */
 #define ITR_IS_DYNAMIC(setting) (!!((setting) & ICE_ITR_DYNAMIC))
 #define ITR_TO_REG(setting)    ((setting) & ~ICE_ITR_DYNAMIC)
-#define ICE_ITR_GRAN_S         1       /* Assume ITR granularity is 2us */
+#define ICE_ITR_GRAN_S         1       /* ITR granularity is always 2us */
 #define ICE_ITR_GRAN_US                BIT(ICE_ITR_GRAN_S)
 #define ICE_ITR_MASK           0x1FFE  /* ITR register value alignment mask */
 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~ICE_ITR_MASK)