perf intel-pt: Always set no branch for dummy event
authorKan Liang <kan.liang@intel.com>
Fri, 30 Jun 2017 14:16:56 +0000 (10:16 -0400)
committerArnaldo Carvalho de Melo <acme@redhat.com>
Thu, 20 Jul 2017 12:55:51 +0000 (09:55 -0300)
An earlier kernel patch allowed enabling PT and LBR at the same time on
Goldmont.

commit ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity
if the core supports it")

However, users still cannot use Intel PT and LBRs simultaneously.  $
sudo perf record -e cycles,intel_pt//u -b  -- sleep 1 Error: PMU
Hardware doesn't support sampling/overflow-interrupts.

PT implicitly adds dummy event in perf tool. dummy event is software
event which doesn't support LBR.

Always setting no branch for dummy event in Intel PT.

Signed-off-by: Kan Liang <kan.liang@intel.com>
Acked-by: Jiri Olsa <jolsa@redhat.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20170630141656.1626-2-kan.liang@intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
tools/perf/arch/x86/util/intel-pt.c

index 4a461e8ae3268596c097c3270e13c6a4e2b2fe46..db0ba8caf5a2475485f068b49cafaea87c29118d 100644 (file)
@@ -701,6 +701,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
                                perf_evsel__set_sample_bit(switch_evsel, TID);
                                perf_evsel__set_sample_bit(switch_evsel, TIME);
                                perf_evsel__set_sample_bit(switch_evsel, CPU);
+                               perf_evsel__reset_sample_bit(switch_evsel, BRANCH_STACK);
 
                                opts->record_switch_events = false;
                                ptr->have_sched_switch = 3;
@@ -762,6 +763,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
                        /* And the CPU for switch events */
                        perf_evsel__set_sample_bit(tracking_evsel, CPU);
                }
+               perf_evsel__reset_sample_bit(tracking_evsel, BRANCH_STACK);
        }
 
        /*