serial: imx: Fix clearing of receiver overrun flag
authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tue, 24 Feb 2015 10:17:05 +0000 (11:17 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 7 Mar 2015 02:26:32 +0000 (03:26 +0100)
The writeable bits in the USR2 register are all "write 1 to
clear" so only write the bits that actually should be cleared.

Fixes: f1f836e4209e ("serial: imx: Add Rx Fifo overrun error message")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/tty/serial/imx.c

index ca00b3f1520ff09d707c14ece58eb8db0f9e6ae7..0f2afae25f6e78e360c124d11a82424720a0d41e 100644 (file)
@@ -818,7 +818,7 @@ static irqreturn_t imx_int(int irq, void *dev_id)
        if (sts2 & USR2_ORE) {
                dev_err(sport->port.dev, "Rx FIFO overrun\n");
                sport->port.icount.overrun++;
-               writel(sts2 | USR2_ORE, sport->port.membase + USR2);
+               writel(USR2_ORE, sport->port.membase + USR2);
        }
 
        return IRQ_HANDLED;
@@ -1181,10 +1181,12 @@ static int imx_startup(struct uart_port *port)
                imx_uart_dma_init(sport);
 
        spin_lock_irqsave(&sport->port.lock, flags);
+
        /*
         * Finally, clear and enable interrupts
         */
        writel(USR1_RTSD, sport->port.membase + USR1);
+       writel(USR2_ORE, sport->port.membase + USR2);
 
        if (sport->dma_is_inited && !sport->dma_is_enabled)
                imx_enable_dma(sport);
@@ -1199,10 +1201,6 @@ static int imx_startup(struct uart_port *port)
 
        writel(temp, sport->port.membase + UCR1);
 
-       /* Clear any pending ORE flag before enabling interrupt */
-       temp = readl(sport->port.membase + USR2);
-       writel(temp | USR2_ORE, sport->port.membase + USR2);
-
        temp = readl(sport->port.membase + UCR4);
        temp |= UCR4_OREN;
        writel(temp, sport->port.membase + UCR4);