select CPU_V7
select SYS_FSL_HAS_SEC if SECURE_BOOT
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
config ARCH_MX6
bool "Freescale MX6"
select CPU_V7
select SYS_FSL_HAS_SEC if SECURE_BOOT
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
config ARCH_MX5
bool "Freescale MX5"
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
menu "LS102xA architecture"
depends on ARCH_LS1021A
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_2
config FSL_LSCH2
bool
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_BE
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
#define CONFIG_SYS_FSL_SFP_LE
#define CONFIG_SYS_FSL_SRK_LE
-/* SEC */
-#define CONFIG_SYS_FSL_SEC_LE
-
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
-#define CONFIG_SYS_FSL_SEC_BE
/* SoC related */
#ifdef CONFIG_LS1043A
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_DCU_BE
#define CONFIG_SYS_FSL_SEC_MON_LE
-#define CONFIG_SYS_FSL_SEC_LE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
config MPC85xx
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_B4860
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9131
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9132
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_6
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8544
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8560
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8569
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8572
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
config ARCH_P1010
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_P1024
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_P3041
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_P4080
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_P5020
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_P5040
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_QEMU_E500
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
config ARCH_T1024
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
config ARCH_T1040
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
config ARCH_T1042
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
config ARCH_T2080
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_T2081
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_T4160
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config ARCH_T4240
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
config BOOKE
#endif
#endif
-/*
- * SEC (crypto unit) major compatible version determination
- */
-#if defined(CONFIG_MPC83xx)
-#define CONFIG_SYS_FSL_SEC_BE
-#endif
-
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SEC_MON_BE
help
Secure boot and trust architecture compatible version 6
+config SYS_FSL_SEC_BE
+ bool "Big-endian access to Freescale Secure Boot"
+
config SYS_FSL_SEC_COMPAT
int "Freescale Secure Boot compatibility"
depends on SYS_FSL_HAS_SEC
default 4 if SYS_FSL_SEC_COMPAT_4
default 5 if SYS_FSL_SEC_COMPAT_5
default 6 if SYS_FSL_SEC_COMPAT_6
+
+config SYS_FSL_SEC_LE
+ bool "Little-endian access to Freescale Secure Boot"
#define CONFIG_CSF_SIZE 0x2000
#define CONFIG_FSL_CAAM
#define CONFIG_CMD_DEKBLOB
-#define CONFIG_SYS_FSL_SEC_LE
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#endif
#define CONFIG_CSF_SIZE 0x2000
#define CONFIG_FSL_CAAM
#define CONFIG_CMD_DEKBLOB
-#define CONFIG_SYS_FSL_SEC_LE
#endif
#endif
#define sec_in16(a) in_be16(a)
#define sec_clrbits32 clrbits_be32
#define sec_setbits32 setbits_be32
-#else
+#elif defined(CONFIG_SYS_FSL_HAS_SEC)
#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
#endif
CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
CONFIG_SYS_FSL_SEC_ADDR
-CONFIG_SYS_FSL_SEC_BE
CONFIG_SYS_FSL_SEC_IDX_OFFSET
-CONFIG_SYS_FSL_SEC_LE
CONFIG_SYS_FSL_SEC_MON_BE
CONFIG_SYS_FSL_SEC_MON_LE
CONFIG_SYS_FSL_SEC_OFFSET