drm/amdgpu: Constify some tables

Some more tables with constant data were added with the polaris support

v2: missed a few

Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index b146ec8a69bb64840c2695f53f90d396a09aca1c..010199fb71265718ba1d80d6cedd34cc7004f144 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -99,16 +99,17 @@
 #define TCLK                        (PCIE_BUS_CLK / 10)
 
 
-uint16_t polaris10_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
-                                                         {600, 1050, 6, 1} };
+static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
+{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 
 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
-uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
-                                                       { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
+static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
+{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
+  { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 
 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
-uint8_t polaris10_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
-                                                           {0, 2, 4, 5, 6, 5} };
+static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
+{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 
 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 enum DPM_EVENT_SRC {
@@ -119,7 +120,7 @@ enum DPM_EVENT_SRC {
        DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 };
 
-const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
+static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 
 struct polaris10_power_state *cast_phw_polaris10_power_state(
                                  struct pp_hw_power_state *hw_ps)
@@ -1069,14 +1070,15 @@ static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
        return 0;
 }
 
-sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
-                                               {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
-                                               {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
-                                               {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
-                                               {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
-                                               {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
-                                               {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
-                                               {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
+static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
+{ {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
+  {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
+  {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
+  {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
+  {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
+  {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
+  {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
+  {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
 
 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
 {

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
index b02296444f2fede409e960846a08e1f4a0346718..beedf35cbfa67974eba8758721b9a4fb227c9a69 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
@@ -264,7 +264,7 @@ struct polaris10_hwmgr {
        bool                           enable_tdc_limit_feature;
        bool                           enable_pkg_pwr_tracking_feature;
        bool                           disable_uvd_power_tune_feature;
-       struct polaris10_pt_defaults       *power_tune_defaults;
+       const struct polaris10_pt_defaults       *power_tune_defaults;
        struct SMU74_Discrete_PmFuses  power_tune_table;
        uint32_t                       dte_tj_offset;
        uint32_t                       fast_watermark_threshold;

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
index 02bcedc7f549c6fe28f5011f4d4bb07701d83189..0b99ab3ba0c5063ca8d3cd70c91e3bab0c3f5ab1 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
@@ -32,7 +32,7 @@
 #define VOLTAGE_SCALE  4
 #define POWERTUNE_DEFAULT_SET_MAX    1
 
-struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
+static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
        /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
         * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
        { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
@@ -67,7 +67,7 @@ static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
 int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
 {
        struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-       struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
+       const struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
        SMU74_Discrete_DpmTable  *dpm_table = &(data->smc_state_table);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -75,8 +75,8 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
        struct pp_advance_fan_control_parameters *fan_table=
                        &hwmgr->thermal_controller.advanceFanControlParameters;
        int i, j, k;
-       uint16_t *pdef1;
-       uint16_t *pdef2;
+       const uint16_t *pdef1;
+       const uint16_t *pdef2;
 
        dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
        dpm_table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
@@ -114,7 +114,7 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
 {
        struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-       struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
+       const struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
 
        data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
        data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
@@ -130,7 +130,7 @@ static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
        struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
-       struct  polaris10_pt_defaults *defaults = data->power_tune_defaults;
+       const struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
 
        tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
        data->power_tune_table.TDC_VDDC_PkgLimit =
@@ -145,7 +145,7 @@ static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
 static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
 {
        struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-       struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
+       const struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
        uint32_t temp;
 
        if (polaris10_read_smc_sram_dword(hwmgr->smumgr,

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
index d39c89bbdab045a6c0f06a78cd911924fcfd44e5..956e00ca361a15dc2ec31185d5608c1f8889b610 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
@@ -638,7 +638,7 @@ static int tf_polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
        return ret;
 }
 
-static struct phm_master_table_item
+static const struct phm_master_table_item
 polaris10_thermal_start_thermal_controller_master_list[] = {
        {NULL, tf_polaris10_thermal_initialize},
        {NULL, tf_polaris10_thermal_set_temperature_range},
@@ -654,14 +654,14 @@ polaris10_thermal_start_thermal_controller_master_list[] = {
        {NULL, NULL}
 };
 
-static struct phm_master_table_header
+static const struct phm_master_table_header
 polaris10_thermal_start_thermal_controller_master = {
        0,
        PHM_MasterTableFlag_None,
        polaris10_thermal_start_thermal_controller_master_list
 };
 
-static struct phm_master_table_item
+static const struct phm_master_table_item
 polaris10_thermal_set_temperature_range_master_list[] = {
        {NULL, tf_polaris10_thermal_disable_alert},
        {NULL, tf_polaris10_thermal_set_temperature_range},
@@ -669,7 +669,7 @@ polaris10_thermal_set_temperature_range_master_list[] = {
        {NULL, NULL}
 };
 
-struct phm_master_table_header
+static const struct phm_master_table_header
 polaris10_thermal_set_temperature_range_master = {
        0,
        PHM_MasterTableFlag_None,

diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
index 933103e6ad08faba74b6e3b7993dd6305ab82621..f497e7d98e6d639828efc299e2f05b24abfd12ed 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
@@ -50,7 +50,7 @@ typedef struct PWR_Command_Table PWR_Command_Table;
 
 #define PWR_VIRUS_TABLE_SIZE  10031
 
-static PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
+static const PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
        { PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
        { PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL                             },
        { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL                               },

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 667e055edd010615a58607e226afad787b5d1c1f..de618ead9db8df73e10ee0da9dac0cad940049b3 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -49,7 +49,7 @@
 
 #define SMC_RAM_END 0x40000
 
-SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
+static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
        /*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
        /* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
        { 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } },
@@ -62,8 +62,9 @@ SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
        { 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } }
 };
 
-SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
-                                                       0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
+static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 =
+       {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
+        0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
 
 /**
 * Set the address for reading/writing the SMC SRAM space.
@@ -200,7 +201,7 @@ int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
 
 static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr)
 {
-       static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
+       static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
 
        polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
 
@@ -616,7 +617,7 @@ static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
        int result = -1;
        uint32_t reg, data;
 
-       PWR_Command_Table *pvirus = pwr_virus_table;
+       const PWR_Command_Table *pvirus = pwr_virus_table;
        struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);