ath9k: merge an interrupt processing fix for AR5008-AR9002

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 39053

diff --git a/package/kernel/mac80211/patches/300-pending_work.patch b/package/kernel/mac80211/patches/300-pending_work.patch
index 58ae04e5df33eb508df385a25d4d4ec7eb484163..7fd622546f37ac97da3013b8bbdd13e9e44fe70b 100644 (file)
--- a/package/kernel/mac80211/patches/300-pending_work.patch
+++ b/package/kernel/mac80211/patches/300-pending_work.patch
@@ -11455,3 +11455,81 @@
 +};
 +
 +#endif /* INITVALS_9003_BUFFALO_H */
+--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+@@ -76,9 +76,16 @@ static bool ar9002_hw_get_isr(struct ath
+                               mask2 |= ATH9K_INT_CST;
+                       if (isr2 & AR_ISR_S2_TSFOOR)
+                               mask2 |= ATH9K_INT_TSFOOR;
++
++                      if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
++                              REG_WRITE(ah, AR_ISR_S2, isr2);
++                              isr &= ~AR_ISR_BCNMISC;
++                      }
+               }
+ 
+-              isr = REG_READ(ah, AR_ISR_RAC);
++              if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
++                      isr = REG_READ(ah, AR_ISR_RAC);
++
+               if (isr == 0xffffffff) {
+                       *masked = 0;
+                       return false;
+@@ -97,11 +104,23 @@ static bool ar9002_hw_get_isr(struct ath
+ 
+                       *masked |= ATH9K_INT_TX;
+ 
+-                      s0_s = REG_READ(ah, AR_ISR_S0_S);
++                      if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
++                              s0_s = REG_READ(ah, AR_ISR_S0_S);
++                              s1_s = REG_READ(ah, AR_ISR_S1_S);
++                      } else {
++                              s0_s = REG_READ(ah, AR_ISR_S0);
++                              REG_WRITE(ah, AR_ISR_S0, s0_s);
++                              s1_s = REG_READ(ah, AR_ISR_S1);
++                              REG_WRITE(ah, AR_ISR_S1, s1_s);
++
++                              isr &= ~(AR_ISR_TXOK |
++                                       AR_ISR_TXDESC |
++                                       AR_ISR_TXERR |
++                                       AR_ISR_TXEOL);
++                      }
++
+                       ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
+                       ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
+-
+-                      s1_s = REG_READ(ah, AR_ISR_S1_S);
+                       ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
+                       ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
+               }
+@@ -120,7 +139,12 @@ static bool ar9002_hw_get_isr(struct ath
+       if (isr & AR_ISR_GENTMR) {
+               u32 s5_s;
+ 
+-              s5_s = REG_READ(ah, AR_ISR_S5_S);
++              if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
++                      s5_s = REG_READ(ah, AR_ISR_S5_S);
++              } else {
++                      s5_s = REG_READ(ah, AR_ISR_S5);
++              }
++
+               ah->intr_gen_timer_trigger =
+                               MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
+ 
+@@ -133,6 +157,16 @@ static bool ar9002_hw_get_isr(struct ath
+               if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
+                   !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
+                       *masked |= ATH9K_INT_TIM_TIMER;
++
++              if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
++                      REG_WRITE(ah, AR_ISR_S5, s5_s);
++                      isr &= ~AR_ISR_GENTMR;
++              }
++      }
++
++      if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
++              REG_WRITE(ah, AR_ISR, isr);
++              REG_READ(ah, AR_ISR);
+       }
+ 
+       if (sync_cause) {