staging: ccree: rename all DX to CC

Unify naming convention by renaming all DX macros to CC.

Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h b/drivers/staging/ccree/cc_hw_queue_defs.h
index 3ca548d6e3b2e89aea40a246b954b9dbd03ad358..7c25a4f0a936e8719111b06a4001993af0aecef5 100644 (file)
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -31,11 +31,11 @@
 #define HW_QUEUE_SLOTS_MAX              15
 
 #define CC_REG_LOW(word, name)  \
-       (DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT)
+       (CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT)
 
 #define CC_REG_HIGH(word, name) \
        (CC_REG_LOW(word, name) + \
-        DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1)
+        CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1)
 
 #define CC_GENMASK(word, name) \
        GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name))

diff --git a/drivers/staging/ccree/cc_lli_defs.h b/drivers/staging/ccree/cc_lli_defs.h
index a9c417b07b0429800d58982c67fced9ad0c35267..861634aa2e7a80be02abcec0fcf6c9bf3e5c90f5 100644 (file)
--- a/drivers/staging/ccree/cc_lli_defs.h
+++ b/drivers/staging/ccree/cc_lli_defs.h
@@ -20,7 +20,7 @@
 #include <linux/types.h>
 
 /* Max DLLI size
- *  AKA DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE
+ *  AKA CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE
  */
 #define DLLI_SIZE_BIT_SIZE     0x18
 

diff --git a/drivers/staging/ccree/dx_crys_kernel.h b/drivers/staging/ccree/dx_crys_kernel.h
index 219603030344d8246c1e6adc39843b445f084542..30719f45cb16e0d4b6a3217e3095d6a64d124996 100644 (file)
--- a/drivers/staging/ccree/dx_crys_kernel.h
+++ b/drivers/staging/ccree/dx_crys_kernel.h
@@ -14,167 +14,167 @@
  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef __DX_CRYS_KERNEL_H__
-#define __DX_CRYS_KERNEL_H__
+#ifndef __CC_CRYS_KERNEL_H__
+#define __CC_CRYS_KERNEL_H__
 
 // --------------------------------------
 // BLOCK: DSCRPTR
 // --------------------------------------
-#define DX_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET       0xE00UL
-#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT     0x0UL
-#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE      0x6UL
-#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT       0x6UL
-#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE        0x1UL
-#define DX_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL
-#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT    0x0UL
-#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SIZE     0x1UL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET  0xE60UL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT    0x0UL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE     0xAUL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE  0xCUL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE  0x3UL
-#define DX_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET   0xE64UL
-#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT      0x0UL
-#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE       0x1UL
-#define DX_DSCRPTR_MEASURE_CNTR_REG_OFFSET     0xE68UL
-#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT        0x0UL
-#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL
-#define DX_DSCRPTR_QUEUE_WORD0_REG_OFFSET      0xE80UL
-#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL
-#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE  0x20UL
-#define DX_DSCRPTR_QUEUE_WORD1_REG_OFFSET      0xE84UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT  0x0UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE   0x2UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT      0x2UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE       0x18UL
-#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT        0x1AUL
-#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT       0x1BUL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE        0x1UL
-#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT      0x1CUL
-#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE       0x1UL
-#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT    0x1DUL
-#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE     0x1UL
-#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT      0x1EUL
-#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE       0x2UL
-#define DX_DSCRPTR_QUEUE_WORD2_REG_OFFSET      0xE88UL
-#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL
-#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE  0x20UL
-#define DX_DSCRPTR_QUEUE_WORD3_REG_OFFSET      0xE8CUL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE  0x2UL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT     0x2UL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE      0x18UL
-#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT        0x1AUL
-#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE  0x1UL
-#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT  0x1DUL
-#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE   0x1UL
-#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT      0x1EUL
-#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE       0x1UL
-#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT        0x1FUL
-#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_REG_OFFSET      0xE90UL
-#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT        0x0UL
-#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL
-#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT        0x6UL
-#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT    0x7UL
-#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE     0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT    0x8UL
-#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE     0x2UL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT   0xAUL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE    0x4UL
-#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT    0xEUL
-#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE     0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT     0xFUL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE      0x2UL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT  0x11UL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE   0x2UL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT  0x13UL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE   0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT  0x14UL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE   0x2UL
-#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT      0x16UL
-#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE       0x2UL
-#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT       0x18UL
-#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE        0x4UL
-#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT   0x1CUL
-#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE    0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT  0x1DUL
-#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE   0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT     0x1EUL
-#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE      0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT    0x1FUL
-#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE     0x1UL
-#define DX_DSCRPTR_QUEUE_WORD5_REG_OFFSET      0xE94UL
-#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL
-#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE  0x10UL
-#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT        0x10UL
-#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL
-#define DX_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET  0xE98UL
-#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT     0x0UL
-#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE      0xAUL
-#define DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET    0xE9CUL
-#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT       0x0UL
-#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE        0xAUL
+#define CC_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET       0xE00UL
+#define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT     0x0UL
+#define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE      0x6UL
+#define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT       0x6UL
+#define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE        0x1UL
+#define CC_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL
+#define CC_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT    0x0UL
+#define CC_DSCRPTR_SW_RESET_VALUE_BIT_SIZE     0x1UL
+#define CC_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET  0xE60UL
+#define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT    0x0UL
+#define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE     0xAUL
+#define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL
+#define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE  0xCUL
+#define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL
+#define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE  0x3UL
+#define CC_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET   0xE64UL
+#define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT      0x0UL
+#define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE       0x1UL
+#define CC_DSCRPTR_MEASURE_CNTR_REG_OFFSET     0xE68UL
+#define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT        0x0UL
+#define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL
+#define CC_DSCRPTR_QUEUE_WORD0_REG_OFFSET      0xE80UL
+#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL
+#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE  0x20UL
+#define CC_DSCRPTR_QUEUE_WORD1_REG_OFFSET      0xE84UL
+#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT  0x0UL
+#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE   0x2UL
+#define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT      0x2UL
+#define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE       0x18UL
+#define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT        0x1AUL
+#define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL
+#define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT       0x1BUL
+#define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE        0x1UL
+#define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT      0x1CUL
+#define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE       0x1UL
+#define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT    0x1DUL
+#define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE     0x1UL
+#define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT      0x1EUL
+#define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE       0x2UL
+#define CC_DSCRPTR_QUEUE_WORD2_REG_OFFSET      0xE88UL
+#define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL
+#define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE  0x20UL
+#define CC_DSCRPTR_QUEUE_WORD3_REG_OFFSET      0xE8CUL
+#define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL
+#define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE  0x2UL
+#define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT     0x2UL
+#define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE      0x18UL
+#define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT        0x1AUL
+#define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL
+#define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL
+#define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE  0x1UL
+#define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT  0x1DUL
+#define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE   0x1UL
+#define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT      0x1EUL
+#define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE       0x1UL
+#define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT        0x1FUL
+#define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL
+#define CC_DSCRPTR_QUEUE_WORD4_REG_OFFSET      0xE90UL
+#define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT        0x0UL
+#define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL
+#define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT        0x6UL
+#define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL
+#define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT    0x7UL
+#define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE     0x1UL
+#define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT    0x8UL
+#define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE     0x2UL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT   0xAUL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE    0x4UL
+#define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT    0xEUL
+#define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE     0x1UL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT     0xFUL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE      0x2UL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT  0x11UL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE   0x2UL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT  0x13UL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE   0x1UL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT  0x14UL
+#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE   0x2UL
+#define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT      0x16UL
+#define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE       0x2UL
+#define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT       0x18UL
+#define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE        0x4UL
+#define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT   0x1CUL
+#define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE    0x1UL
+#define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT  0x1DUL
+#define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE   0x1UL
+#define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT     0x1EUL
+#define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE      0x1UL
+#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT    0x1FUL
+#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE     0x1UL
+#define CC_DSCRPTR_QUEUE_WORD5_REG_OFFSET      0xE94UL
+#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL
+#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE  0x10UL
+#define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT        0x10UL
+#define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL
+#define CC_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET  0xE98UL
+#define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT     0x0UL
+#define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE      0xAUL
+#define CC_DSCRPTR_QUEUE_CONTENT_REG_OFFSET    0xE9CUL
+#define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT       0x0UL
+#define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE        0xAUL
 // --------------------------------------
 // BLOCK: AXI_P
 // --------------------------------------
-#define DX_AXIM_MON_INFLIGHT_REG_OFFSET        0xB00UL
-#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT   0x0UL
-#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE    0x8UL
-#define DX_AXIM_MON_INFLIGHTLAST_REG_OFFSET    0xB40UL
-#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT       0x0UL
-#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE        0x8UL
-#define DX_AXIM_MON_COMP_REG_OFFSET    0xB80UL
-#define DX_AXIM_MON_COMP_VALUE_BIT_SHIFT       0x0UL
-#define DX_AXIM_MON_COMP_VALUE_BIT_SIZE        0x10UL
-#define DX_AXIM_MON_ERR_REG_OFFSET     0xBC4UL
-#define DX_AXIM_MON_ERR_BRESP_BIT_SHIFT        0x0UL
-#define DX_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL
-#define DX_AXIM_MON_ERR_BID_BIT_SHIFT  0x2UL
-#define DX_AXIM_MON_ERR_BID_BIT_SIZE   0x4UL
-#define DX_AXIM_MON_ERR_RRESP_BIT_SHIFT        0x10UL
-#define DX_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL
-#define DX_AXIM_MON_ERR_RID_BIT_SHIFT  0x12UL
-#define DX_AXIM_MON_ERR_RID_BIT_SIZE   0x4UL
-#define DX_AXIM_CFG_REG_OFFSET 0xBE8UL
-#define DX_AXIM_CFG_BRESPMASK_BIT_SHIFT        0x4UL
-#define DX_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL
-#define DX_AXIM_CFG_RRESPMASK_BIT_SHIFT        0x5UL
-#define DX_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL
-#define DX_AXIM_CFG_INFLTMASK_BIT_SHIFT        0x6UL
-#define DX_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL
-#define DX_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL
-#define DX_AXIM_CFG_COMPMASK_BIT_SIZE  0x1UL
-#define DX_AXIM_ACE_CONST_REG_OFFSET   0xBECUL
-#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT   0x0UL
-#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE    0x2UL
-#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT   0x2UL
-#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE    0x2UL
-#define DX_AXIM_ACE_CONST_ARBAR_BIT_SHIFT      0x4UL
-#define DX_AXIM_ACE_CONST_ARBAR_BIT_SIZE       0x2UL
-#define DX_AXIM_ACE_CONST_AWBAR_BIT_SHIFT      0x6UL
-#define DX_AXIM_ACE_CONST_AWBAR_BIT_SIZE       0x2UL
-#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT    0x8UL
-#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE     0x4UL
-#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT        0xCUL
-#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL
-#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT    0xFUL
-#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE     0x3UL
-#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT  0x12UL
-#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE   0x7UL
-#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT  0x19UL
-#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE   0x4UL
-#define DX_AXIM_CACHE_PARAMS_REG_OFFSET        0xBF0UL
-#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT    0x0UL
-#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE     0x4UL
-#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL
-#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE  0x4UL
-#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL
-#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE  0x4UL
-#endif // __DX_CRYS_KERNEL_H__
+#define CC_AXIM_MON_INFLIGHT_REG_OFFSET        0xB00UL
+#define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT   0x0UL
+#define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE    0x8UL
+#define CC_AXIM_MON_INFLIGHTLAST_REG_OFFSET    0xB40UL
+#define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT       0x0UL
+#define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE        0x8UL
+#define CC_AXIM_MON_COMP_REG_OFFSET    0xB80UL
+#define CC_AXIM_MON_COMP_VALUE_BIT_SHIFT       0x0UL
+#define CC_AXIM_MON_COMP_VALUE_BIT_SIZE        0x10UL
+#define CC_AXIM_MON_ERR_REG_OFFSET     0xBC4UL
+#define CC_AXIM_MON_ERR_BRESP_BIT_SHIFT        0x0UL
+#define CC_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL
+#define CC_AXIM_MON_ERR_BID_BIT_SHIFT  0x2UL
+#define CC_AXIM_MON_ERR_BID_BIT_SIZE   0x4UL
+#define CC_AXIM_MON_ERR_RRESP_BIT_SHIFT        0x10UL
+#define CC_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL
+#define CC_AXIM_MON_ERR_RID_BIT_SHIFT  0x12UL
+#define CC_AXIM_MON_ERR_RID_BIT_SIZE   0x4UL
+#define CC_AXIM_CFG_REG_OFFSET 0xBE8UL
+#define CC_AXIM_CFG_BRESPMASK_BIT_SHIFT        0x4UL
+#define CC_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL
+#define CC_AXIM_CFG_RRESPMASK_BIT_SHIFT        0x5UL
+#define CC_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL
+#define CC_AXIM_CFG_INFLTMASK_BIT_SHIFT        0x6UL
+#define CC_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL
+#define CC_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL
+#define CC_AXIM_CFG_COMPMASK_BIT_SIZE  0x1UL
+#define CC_AXIM_ACE_CONST_REG_OFFSET   0xBECUL
+#define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT   0x0UL
+#define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE    0x2UL
+#define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT   0x2UL
+#define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE    0x2UL
+#define CC_AXIM_ACE_CONST_ARBAR_BIT_SHIFT      0x4UL
+#define CC_AXIM_ACE_CONST_ARBAR_BIT_SIZE       0x2UL
+#define CC_AXIM_ACE_CONST_AWBAR_BIT_SHIFT      0x6UL
+#define CC_AXIM_ACE_CONST_AWBAR_BIT_SIZE       0x2UL
+#define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT    0x8UL
+#define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE     0x4UL
+#define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT        0xCUL
+#define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL
+#define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT    0xFUL
+#define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE     0x3UL
+#define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT  0x12UL
+#define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE   0x7UL
+#define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT  0x19UL
+#define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE   0x4UL
+#define CC_AXIM_CACHE_PARAMS_REG_OFFSET        0xBF0UL
+#define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT    0x0UL
+#define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE     0x4UL
+#define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL
+#define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE  0x4UL
+#define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL
+#define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE  0x4UL
+#endif // __CC_CRYS_KERNEL_H__

diff --git a/drivers/staging/ccree/dx_host.h b/drivers/staging/ccree/dx_host.h
index 863c2670d826878904bd168aec5ebcdd3527d01a..e90afbc9e762f2d85afc23caa393d94151e952db 100644 (file)
--- a/drivers/staging/ccree/dx_host.h
+++ b/drivers/staging/ccree/dx_host.h
@@ -14,142 +14,142 @@
  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef __DX_HOST_H__
-#define __DX_HOST_H__
+#ifndef __CC_HOST_H__
+#define __CC_HOST_H__
 
 // --------------------------------------
 // BLOCK: HOST_P
 // --------------------------------------
-#define DX_HOST_IRR_REG_OFFSET 0xA00UL
-#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT       0x2UL
-#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE        0x1UL
-#define DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT      0x8UL
-#define DX_HOST_IRR_AXI_ERR_INT_BIT_SIZE       0x1UL
-#define DX_HOST_IRR_GPR0_BIT_SHIFT     0xBUL
-#define DX_HOST_IRR_GPR0_BIT_SIZE      0x1UL
-#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT    0x13UL
-#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE     0x1UL
-#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT    0x17UL
-#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SIZE     0x1UL
-#define DX_HOST_IMR_REG_OFFSET 0xA04UL
-#define DX_HOST_IMR_NOT_USED_MASK_BIT_SHIFT    0x1UL
-#define DX_HOST_IMR_NOT_USED_MASK_BIT_SIZE     0x1UL
-#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT  0x2UL
-#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE   0x1UL
-#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT     0x8UL
-#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SIZE      0x1UL
-#define DX_HOST_IMR_GPR0_BIT_SHIFT     0xBUL
-#define DX_HOST_IMR_GPR0_BIT_SIZE      0x1UL
-#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT  0x13UL
-#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE   0x1UL
-#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT       0x17UL
-#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE        0x1UL
-#define DX_HOST_ICR_REG_OFFSET 0xA08UL
-#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT       0x2UL
-#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE        0x1UL
-#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT    0x8UL
-#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE     0x1UL
-#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT    0xBUL
-#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE     0x1UL
-#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT   0x13UL
-#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE    0x1UL
-#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT      0x17UL
-#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE       0x1UL
-#define DX_HOST_SIGNATURE_REG_OFFSET   0xA24UL
-#define DX_HOST_SIGNATURE_VALUE_BIT_SHIFT      0x0UL
-#define DX_HOST_SIGNATURE_VALUE_BIT_SIZE       0x20UL
-#define DX_HOST_BOOT_REG_OFFSET        0xA28UL
-#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT        0x0UL
-#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL
-#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT        0x1UL
-#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL
-#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT     0x2UL
-#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE      0x1UL
-#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT   0x3UL
-#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE    0x1UL
-#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL
-#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE  0x1UL
-#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL
-#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE  0x3UL
-#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT    0x9UL
-#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE     0x1UL
-#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT        0xAUL
-#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL
-#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT        0xBUL
-#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL
-#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT        0xCUL
-#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL
-#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT        0xDUL
-#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL
-#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT     0xEUL
-#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE      0x1UL
-#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT     0xFUL
-#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE      0x1UL
-#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL
-#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE  0x1UL
-#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT       0x11UL
-#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE        0x1UL
-#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL
-#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE  0x1UL
-#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT        0x13UL
-#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL
-#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT       0x14UL
-#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE        0x1UL
-#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT   0x15UL
-#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE    0x1UL
-#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT    0x16UL
-#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE     0x1UL
-#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL
-#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE  0x1UL
-#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT    0x18UL
-#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE     0x1UL
-#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT        0x19UL
-#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL
-#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT   0x1AUL
-#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE    0x1UL
-#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT     0x1BUL
-#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE      0x1UL
-#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT       0x1CUL
-#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE        0x1UL
-#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT      0x1DUL
-#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE       0x1UL
-#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT        0x1EUL
-#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL
-#define DX_HOST_VERSION_REG_OFFSET     0xA40UL
-#define DX_HOST_VERSION_VALUE_BIT_SHIFT        0x0UL
-#define DX_HOST_VERSION_VALUE_BIT_SIZE 0x20UL
-#define DX_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL
-#define DX_HOST_KFDE0_VALID_VALUE_BIT_SHIFT    0x0UL
-#define DX_HOST_KFDE0_VALID_VALUE_BIT_SIZE     0x1UL
-#define DX_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL
-#define DX_HOST_KFDE1_VALID_VALUE_BIT_SHIFT    0x0UL
-#define DX_HOST_KFDE1_VALID_VALUE_BIT_SIZE     0x1UL
-#define DX_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL
-#define DX_HOST_KFDE2_VALID_VALUE_BIT_SHIFT    0x0UL
-#define DX_HOST_KFDE2_VALID_VALUE_BIT_SIZE     0x1UL
-#define DX_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL
-#define DX_HOST_KFDE3_VALID_VALUE_BIT_SHIFT    0x0UL
-#define DX_HOST_KFDE3_VALID_VALUE_BIT_SIZE     0x1UL
-#define DX_HOST_GPR0_REG_OFFSET        0xA70UL
-#define DX_HOST_GPR0_VALUE_BIT_SHIFT   0x0UL
-#define DX_HOST_GPR0_VALUE_BIT_SIZE    0x20UL
-#define DX_GPR_HOST_REG_OFFSET 0xA74UL
-#define DX_GPR_HOST_VALUE_BIT_SHIFT    0x0UL
-#define DX_GPR_HOST_VALUE_BIT_SIZE     0x20UL
-#define DX_HOST_POWER_DOWN_EN_REG_OFFSET       0xA78UL
-#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT  0x0UL
-#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE   0x1UL
+#define CC_HOST_IRR_REG_OFFSET 0xA00UL
+#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT       0x2UL
+#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE        0x1UL
+#define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT      0x8UL
+#define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE       0x1UL
+#define CC_HOST_IRR_GPR0_BIT_SHIFT     0xBUL
+#define CC_HOST_IRR_GPR0_BIT_SIZE      0x1UL
+#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT    0x13UL
+#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE     0x1UL
+#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT    0x17UL
+#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE     0x1UL
+#define CC_HOST_IMR_REG_OFFSET 0xA04UL
+#define CC_HOST_IMR_NOT_USED_MASK_BIT_SHIFT    0x1UL
+#define CC_HOST_IMR_NOT_USED_MASK_BIT_SIZE     0x1UL
+#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT  0x2UL
+#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE   0x1UL
+#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT     0x8UL
+#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE      0x1UL
+#define CC_HOST_IMR_GPR0_BIT_SHIFT     0xBUL
+#define CC_HOST_IMR_GPR0_BIT_SIZE      0x1UL
+#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT  0x13UL
+#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE   0x1UL
+#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT       0x17UL
+#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE        0x1UL
+#define CC_HOST_ICR_REG_OFFSET 0xA08UL
+#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT       0x2UL
+#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE        0x1UL
+#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT    0x8UL
+#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE     0x1UL
+#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT    0xBUL
+#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE     0x1UL
+#define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT   0x13UL
+#define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE    0x1UL
+#define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT      0x17UL
+#define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE       0x1UL
+#define CC_HOST_SIGNATURE_REG_OFFSET   0xA24UL
+#define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT      0x0UL
+#define CC_HOST_SIGNATURE_VALUE_BIT_SIZE       0x20UL
+#define CC_HOST_BOOT_REG_OFFSET        0xA28UL
+#define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT        0x0UL
+#define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL
+#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT        0x1UL
+#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL
+#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT     0x2UL
+#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE      0x1UL
+#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT   0x3UL
+#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE    0x1UL
+#define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL
+#define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE  0x1UL
+#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL
+#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE  0x3UL
+#define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT    0x9UL
+#define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE     0x1UL
+#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT        0xAUL
+#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL
+#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT        0xBUL
+#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL
+#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT        0xCUL
+#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL
+#define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT        0xDUL
+#define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL
+#define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT     0xEUL
+#define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE      0x1UL
+#define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT     0xFUL
+#define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE      0x1UL
+#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL
+#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE  0x1UL
+#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT       0x11UL
+#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE        0x1UL
+#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL
+#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE  0x1UL
+#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT        0x13UL
+#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL
+#define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT       0x14UL
+#define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE        0x1UL
+#define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT   0x15UL
+#define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE    0x1UL
+#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT    0x16UL
+#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE     0x1UL
+#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL
+#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE  0x1UL
+#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT    0x18UL
+#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE     0x1UL
+#define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT        0x19UL
+#define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL
+#define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT   0x1AUL
+#define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE    0x1UL
+#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT     0x1BUL
+#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE      0x1UL
+#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT       0x1CUL
+#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE        0x1UL
+#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT      0x1DUL
+#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE       0x1UL
+#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT        0x1EUL
+#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL
+#define CC_HOST_VERSION_REG_OFFSET     0xA40UL
+#define CC_HOST_VERSION_VALUE_BIT_SHIFT        0x0UL
+#define CC_HOST_VERSION_VALUE_BIT_SIZE 0x20UL
+#define CC_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL
+#define CC_HOST_KFDE0_VALID_VALUE_BIT_SHIFT    0x0UL
+#define CC_HOST_KFDE0_VALID_VALUE_BIT_SIZE     0x1UL
+#define CC_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL
+#define CC_HOST_KFDE1_VALID_VALUE_BIT_SHIFT    0x0UL
+#define CC_HOST_KFDE1_VALID_VALUE_BIT_SIZE     0x1UL
+#define CC_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL
+#define CC_HOST_KFDE2_VALID_VALUE_BIT_SHIFT    0x0UL
+#define CC_HOST_KFDE2_VALID_VALUE_BIT_SIZE     0x1UL
+#define CC_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL
+#define CC_HOST_KFDE3_VALID_VALUE_BIT_SHIFT    0x0UL
+#define CC_HOST_KFDE3_VALID_VALUE_BIT_SIZE     0x1UL
+#define CC_HOST_GPR0_REG_OFFSET        0xA70UL
+#define CC_HOST_GPR0_VALUE_BIT_SHIFT   0x0UL
+#define CC_HOST_GPR0_VALUE_BIT_SIZE    0x20UL
+#define CC_GPR_HOST_REG_OFFSET 0xA74UL
+#define CC_GPR_HOST_VALUE_BIT_SHIFT    0x0UL
+#define CC_GPR_HOST_VALUE_BIT_SIZE     0x20UL
+#define CC_HOST_POWER_DOWN_EN_REG_OFFSET       0xA78UL
+#define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT  0x0UL
+#define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE   0x1UL
 // --------------------------------------
 // BLOCK: HOST_SRAM
 // --------------------------------------
-#define DX_SRAM_DATA_REG_OFFSET        0xF00UL
-#define DX_SRAM_DATA_VALUE_BIT_SHIFT   0x0UL
-#define DX_SRAM_DATA_VALUE_BIT_SIZE    0x20UL
-#define DX_SRAM_ADDR_REG_OFFSET        0xF04UL
-#define DX_SRAM_ADDR_VALUE_BIT_SHIFT   0x0UL
-#define DX_SRAM_ADDR_VALUE_BIT_SIZE    0xFUL
-#define DX_SRAM_DATA_READY_REG_OFFSET  0xF08UL
-#define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT     0x0UL
-#define DX_SRAM_DATA_READY_VALUE_BIT_SIZE      0x1UL
+#define CC_SRAM_DATA_REG_OFFSET        0xF00UL
+#define CC_SRAM_DATA_VALUE_BIT_SHIFT   0x0UL
+#define CC_SRAM_DATA_VALUE_BIT_SIZE    0x20UL
+#define CC_SRAM_ADDR_REG_OFFSET        0xF04UL
+#define CC_SRAM_ADDR_VALUE_BIT_SHIFT   0x0UL
+#define CC_SRAM_ADDR_VALUE_BIT_SIZE    0xFUL
+#define CC_SRAM_DATA_READY_REG_OFFSET  0xF08UL
+#define CC_SRAM_DATA_READY_VALUE_BIT_SHIFT     0x0UL
+#define CC_SRAM_DATA_READY_VALUE_BIT_SIZE      0x1UL
 
-#endif //__DX_HOST_H__
+#endif //__CC_HOST_H__

diff --git a/drivers/staging/ccree/dx_reg_common.h b/drivers/staging/ccree/dx_reg_common.h
index d5132ffaf6e68aa27950d7367cdea5a8257d8bdf..8334d9fc6edbc504b15fd28b919a30295bf8ebe6 100644 (file)
--- a/drivers/staging/ccree/dx_reg_common.h
+++ b/drivers/staging/ccree/dx_reg_common.h
@@ -14,13 +14,13 @@
  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef __DX_REG_COMMON_H__
-#define __DX_REG_COMMON_H__
+#ifndef __CC_REG_COMMON_H__
+#define __CC_REG_COMMON_H__
 
-#define DX_DEV_SIGNATURE 0xDCC71200UL
+#define CC_DEV_SIGNATURE 0xDCC71200UL
 
 #define CC_HW_VERSION 0xef840015UL
 
-#define DX_DEV_SHA_MAX 512
+#define CC_DEV_SHA_MAX 512
 
-#endif /*__DX_REG_COMMON_H__*/
+#endif /*__CC_REG_COMMON_H__*/

diff --git a/drivers/staging/ccree/ssi_config.h b/drivers/staging/ccree/ssi_config.h
index e97bc68d96eac6ea115856428ca5c02efea3422e..ee2d310473ea5c2301fe721f212c74a6b7d1878d 100644 (file)
--- a/drivers/staging/ccree/ssi_config.h
+++ b/drivers/staging/ccree/ssi_config.h
@@ -25,14 +25,14 @@
 
 //#define FLUSH_CACHE_ALL
 //#define COMPLETION_DELAY
-//#define DX_DUMP_DESCS
-// #define DX_DUMP_BYTES
+//#define CC_DUMP_DESCS
+// #define CC_DUMP_BYTES
 // #define CC_DEBUG
 /* Enable sysfs interface for debugging REE driver */
 #define ENABLE_CC_SYSFS
-//#define DX_IRQ_DELAY 100000
+//#define CC_IRQ_DELAY 100000
 /* was 32 bit, but for juno's sake it was enlarged to 48 bit */
 #define DMA_BIT_MASK_LEN       48
 
-#endif /*__DX_CONFIG_H__*/
+#endif /*__CC_CONFIG_H__*/
 

diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index dce12e1b55f36acaefdddf3034dc9be25afb1cdb..078d1461e9f5d46b1b81dcda685619c3c1216187 100644 (file)
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -72,7 +72,7 @@
 #include "ssi_pm.h"
 #include "ssi_fips.h"
 
-#ifdef DX_DUMP_BYTES
+#ifdef CC_DUMP_BYTES
 void dump_byte_array(const char *name, const u8 *buf, size_t len)
 {
        char prefix[NAME_LEN];
@@ -171,10 +171,10 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe)
                               CC_GPR0_IRQ_MASK));
        cc_iowrite(drvdata, CC_REG(HOST_IMR), val);
 
-#ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET
-#ifdef DX_IRQ_DELAY
+#ifdef CC_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET
+#ifdef CC_IRQ_DELAY
        /* Set CC IRQ delay */
-       cc_iowrite(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL), DX_IRQ_DELAY);
+       cc_iowrite(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL), CC_IRQ_DELAY);
 #endif
        if (cc_ioread(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL)) > 0) {
                dev_dbg(dev, "irq_delay=%d CC cycles\n",
@@ -279,9 +279,9 @@ static int init_cc_resources(struct platform_device *plat_dev)
 
        /* Verify correct mapping */
        signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE));
-       if (signature_val != DX_DEV_SIGNATURE) {
+       if (signature_val != CC_DEV_SIGNATURE) {
                dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
-                       signature_val, (u32)DX_DEV_SIGNATURE);
+                       signature_val, (u32)CC_DEV_SIGNATURE);
                rc = -EINVAL;
                goto post_clk_err;
        }
@@ -507,9 +507,9 @@ static const struct dev_pm_ops arm_cc7x_driver_pm = {
 #endif
 
 #if defined(CONFIG_PM)
-#define        DX_DRIVER_RUNTIME_PM    (&arm_cc7x_driver_pm)
+#define        CC_DRIVER_RUNTIME_PM    (&arm_cc7x_driver_pm)
 #else
-#define        DX_DRIVER_RUNTIME_PM    NULL
+#define        CC_DRIVER_RUNTIME_PM    NULL
 #endif
 
 #ifdef CONFIG_OF
@@ -526,7 +526,7 @@ static struct platform_driver cc7x_driver = {
 #ifdef CONFIG_OF
                   .of_match_table = arm_cc7x_dev_of_match,
 #endif
-                  .pm = DX_DRIVER_RUNTIME_PM,
+                  .pm = CC_DRIVER_RUNTIME_PM,
        },
        .probe = cc7x_probe,
        .remove = cc7x_remove,

diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index 3d4513b59e5186a2fd53ffd11f5c1f1139bf6a48..4d94a06e881194a445b9274a9a0562fd45abd040 100644 (file)
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -42,7 +42,7 @@
 /* Registers definitions from shared/hw/ree_include */
 #include "dx_host.h"
 #include "dx_reg_common.h"
-#define CC_SUPPORT_SHA DX_DEV_SHA_MAX
+#define CC_SUPPORT_SHA CC_DEV_SHA_MAX
 #include "cc_crypto_ctx.h"
 #include "ssi_sysfs.h"
 #include "hash_defs.h"
@@ -54,24 +54,24 @@
 #define CC_DEV_NAME_STR "cc715ree"
 #define CC_COHERENT_CACHE_PARAMS 0xEEE
 
-#define CC_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \
-                         (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
-                         (1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \
-                         (1 << DX_AXIM_CFG_COMPMASK_BIT_SHIFT))
+#define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \
+                         (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
+                         (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \
+                         (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))
 
-#define CC_AXI_ERR_IRQ_MASK BIT(DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
+#define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
 
-#define CC_COMP_IRQ_MASK BIT(DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
+#define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
 
-#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
-                                   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
-                                   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
+#define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
+                                   CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
+                                   CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)
 
 /* Register name mangling macro */
-#define CC_REG(reg_name) DX_ ## reg_name ## _REG_OFFSET
+#define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
 
 /* TEE FIPS status interrupt */
-#define CC_GPR0_IRQ_MASK BIT(DX_HOST_IRR_GPR0_BIT_SHIFT)
+#define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)
 
 #define CC_CRA_PRIO 3000
 
@@ -169,7 +169,7 @@ static inline struct device *drvdata_to_dev(struct ssi_drvdata *drvdata)
        return &drvdata->plat_dev->dev;
 }
 
-#ifdef DX_DUMP_BYTES
+#ifdef CC_DUMP_BYTES
 void dump_byte_array(const char *name, const u8 *the_array,
                     unsigned long size);
 #else

diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 9990ecc510e24238c8e685620e158e42dfb843b4..04e193f43928d55bb4af7890b8a715ad0a25460f 100644 (file)
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -53,7 +53,7 @@ static const u32 sha224_init[] = {
 static const u32 sha256_init[] = {
        SHA256_H7, SHA256_H6, SHA256_H5, SHA256_H4,
        SHA256_H3, SHA256_H2, SHA256_H1, SHA256_H0 };
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
 static const u32 digest_len_sha512_init[] = {
        0x00000080, 0x00000000, 0x00000000, 0x00000000 };
 static const u64 sha384_init[] = {
@@ -209,7 +209,7 @@ static int cc_map_req(struct device *dev, struct ahash_req_ctx *state,
                } else { /*sha*/
                        memcpy(state->digest_buff, ctx->digest_buff,
                               ctx->inter_digestsize);
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
                        if (ctx->hash_mode == DRV_HASH_SHA512 ||
                            ctx->hash_mode == DRV_HASH_SHA384)
                                memcpy(state->digest_bytes_len,
@@ -1839,7 +1839,7 @@ static struct cc_hash_template driver_hash[] = {
                .hw_mode = DRV_HASH_HW_SHA256,
                .inter_digestsize = SHA256_DIGEST_SIZE,
        },
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
        {
                .name = "sha384",
                .driver_name = "sha384-dx",
@@ -2013,7 +2013,7 @@ int cc_init_hash_sram(struct ssi_drvdata *drvdata)
        struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)];
        struct device *dev = drvdata_to_dev(drvdata);
        int rc = 0;
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
        int i;
 #endif
 
@@ -2028,7 +2028,7 @@ int cc_init_hash_sram(struct ssi_drvdata *drvdata)
        sram_buff_ofs += sizeof(digest_len_init);
        larval_seq_len = 0;
 
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
        /* Copy-to-sram digest-len for sha384/512 */
        cc_set_sram_desc(digest_len_sha512_init, sram_buff_ofs,
                         ARRAY_SIZE(digest_len_sha512_init),
@@ -2081,7 +2081,7 @@ int cc_init_hash_sram(struct ssi_drvdata *drvdata)
        sram_buff_ofs += sizeof(sha256_init);
        larval_seq_len = 0;
 
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
        /* We are forced to swap each double-word larval before copying to
         * sram
         */
@@ -2142,7 +2142,7 @@ int cc_hash_alloc(struct ssi_drvdata *drvdata)
        drvdata->hash_handle = hash_handle;
 
        sram_size_to_alloc = sizeof(digest_len_init) +
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
                        sizeof(digest_len_sha512_init) +
                        sizeof(sha384_init) +
                        sizeof(sha512_init) +
@@ -2413,7 +2413,7 @@ ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode)
                        sizeof(md5_init) +
                        sizeof(sha1_init) +
                        sizeof(sha224_init));
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
        case DRV_HASH_SHA384:
                return (hash_handle->larval_digest_sram_addr +
                        sizeof(md5_init) +
@@ -2449,7 +2449,7 @@ cc_digest_len_addr(void *drvdata, u32 mode)
        case DRV_HASH_SHA256:
        case DRV_HASH_MD5:
                return digest_len_addr;
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
        case DRV_HASH_SHA384:
        case DRV_HASH_SHA512:
                return  digest_len_addr + sizeof(digest_len_init);

diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h
index 19fc4cfb036adccf83a27cc1b726c4621dd068cd..9d1af96c85f2ecb6fcc6e950eacb1e641224f62a 100644 (file)
--- a/drivers/staging/ccree/ssi_hash.h
+++ b/drivers/staging/ccree/ssi_hash.h
@@ -25,7 +25,7 @@
 
 #define HMAC_IPAD_CONST        0x36363636
 #define HMAC_OPAD_CONST        0x5C5C5C5C
-#if (DX_DEV_SHA_MAX > 256)
+#if (CC_DEV_SHA_MAX > 256)
 #define HASH_LEN_SIZE 16
 #define CC_MAX_HASH_DIGEST_SIZE        SHA512_DIGEST_SIZE
 #define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE

diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c
index 436e035aa4efe3cd89c9d6894e2ab3bc2bd7d7c1..f1356d18230e0cf3b0ce885e8cdaca45b4698342 100644 (file)
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -179,7 +179,7 @@ static void enqueue_seq(void __iomem *cc_base, struct cc_hw_desc seq[],
        for (i = 0; i < seq_len; i++) {
                for (w = 0; w <= 5; w++)
                        writel_relaxed(seq[i].word[w], reg);
-#ifdef DX_DUMP_DESCS
+#ifdef CC_DUMP_DESCS
                dev_dbg(dev, "desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
                        i, seq[i].word[0], seq[i].word[1], seq[i].word[2],
                        seq[i].word[3], seq[i].word[4], seq[i].word[5]);

diff --git a/drivers/staging/ccree/ssi_sysfs.c b/drivers/staging/ccree/ssi_sysfs.c
index 08858a4e9d242938f0323c223ff87c7ecb3d04cb..6b11a720e41dd5a83e4d2b18f672514bd6b4e709 100644 (file)
--- a/drivers/staging/ccree/ssi_sysfs.c
+++ b/drivers/staging/ccree/ssi_sysfs.c
@@ -34,23 +34,23 @@ static ssize_t ssi_sys_regdump_show(struct kobject *kobj,
        register_value = cc_ioread(drvdata, CC_REG(HOST_SIGNATURE));
        offset += scnprintf(buf + offset, PAGE_SIZE - offset,
                            "%s \t(0x%lX)\t 0x%08X\n", "HOST_SIGNATURE       ",
-                           DX_HOST_SIGNATURE_REG_OFFSET, register_value);
+                           CC_HOST_SIGNATURE_REG_OFFSET, register_value);
        register_value = cc_ioread(drvdata, CC_REG(HOST_IRR));
        offset += scnprintf(buf + offset, PAGE_SIZE - offset,
                            "%s \t(0x%lX)\t 0x%08X\n", "HOST_IRR             ",
-                           DX_HOST_IRR_REG_OFFSET, register_value);
+                           CC_HOST_IRR_REG_OFFSET, register_value);
        register_value = cc_ioread(drvdata, CC_REG(HOST_POWER_DOWN_EN));
        offset += scnprintf(buf + offset, PAGE_SIZE - offset,
                            "%s \t(0x%lX)\t 0x%08X\n", "HOST_POWER_DOWN_EN   ",
-                           DX_HOST_POWER_DOWN_EN_REG_OFFSET, register_value);
+                           CC_HOST_POWER_DOWN_EN_REG_OFFSET, register_value);
        register_value =  cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));
        offset += scnprintf(buf + offset, PAGE_SIZE - offset,
                            "%s \t(0x%lX)\t 0x%08X\n", "AXIM_MON_ERR         ",
-                           DX_AXIM_MON_ERR_REG_OFFSET, register_value);
+                           CC_AXIM_MON_ERR_REG_OFFSET, register_value);
        register_value = cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));
        offset += scnprintf(buf + offset, PAGE_SIZE - offset,
                            "%s \t(0x%lX)\t 0x%08X\n", "DSCRPTR_QUEUE_CONTENT",
-                           DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET,
+                           CC_DSCRPTR_QUEUE_CONTENT_REG_OFFSET,
                            register_value);
        return offset;
 }