CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_CEVT_R4K=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_HAVE_CLK=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_BOSTON=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_REGMAP_MMIO=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RTL838X=y
+CONFIG_RTL9300_TIMER=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SFP=y
CONFIG_SPI_MEM=y
CONFIG_SPI_RTL838X=y
CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
+CONFIG_SWAP_IO_SPACE=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
#include <linux/console.h>
#include <linux/init.h>
-#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of_fdt.h>
#include <asm/addrspace.h>
#include <asm/io.h>
-
#include <asm/bootinfo.h>
-#include <linux/of_fdt.h>
#include <asm/reboot.h>
-#include <asm/time.h> /* for mips_hpt_frequency */
+#include <asm/time.h>
#include <asm/prom.h>
#include <asm/smp-ops.h>
#include "mach-rtl83xx.h"
-extern int rtl838x_serial_init(void);
extern struct rtl83xx_soc_info soc_info;
u32 pll_reset_value;
static void rtl838x_restart(char *command)
{
u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
- /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
- void (*f)(void) = (void *) 0xbfc00000;
pr_info("System restart.\n");
- if (soc_info.family == RTL8390_FAMILY_ID) {
- f();
- /* If calling reset vector fails, reset entire chip */
- sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
- /* If this fails, halt the CPU */
- while
- (1);
- }
-
pr_info("PLL control register: %x, applying reset value %x\n",
pll, pll_reset_value);
+
sw_w32(3, RTL838X_INT_RW_CTRL);
sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
sw_w32(0, RTL838X_INT_RW_CTRL);
- pr_info("Resetting RTL838X SoC\n");
/* Reset Global Control1 Register */
sw_w32(1, RTL838X_RST_GLB_CTRL_1);
}
+static void rtl839x_restart(char *command)
+{
+ /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
+ void (*f)(void) = (void *) 0xbfc00000;
+
+ pr_info("System restart.\n");
+ /* Reset SoC */
+ sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
+ /* and call reset vector */
+ f();
+ /* If this fails, halt the CPU */
+ while
+ (1);
+}
+
+static void rtl930x_restart(char *command)
+{
+ pr_info("System restart.\n");
+ sw_w32(0x1, RTL930X_RST_GLB_CTRL_0);
+ while
+ (1);
+}
+
+static void rtl931x_restart(char *command)
+{
+ u32 v;
+
+ pr_info("System restart.\n");
+ sw_w32(1, RTL931X_RST_GLB_CTRL);
+ v = sw_r32(RTL931X_RST_GLB_CTRL);
+ sw_w32(0x101, RTL931X_RST_GLB_CTRL);
+ msleep(15);
+ sw_w32(v, RTL931X_RST_GLB_CTRL);
+ msleep(15);
+ sw_w32(0x101, RTL931X_RST_GLB_CTRL);
+}
+
+static void rtl838x_halt(void)
+{
+ pr_info("System halted.\n");
+ while
+ (1);
+}
+
+static void __init rtl838x_setup(void)
+{
+ pr_info("Registering _machine_restart\n");
+ _machine_restart = rtl838x_restart;
+ _machine_halt = rtl838x_halt;
+
+ /* This PLL value needs to be restored before a reset and will then be
+ * preserved over a SoC reset. A wrong value prevents the SoC from
+ * connecting to the SPI flash controller at boot and reading the
+ * reset routine */
+ pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
+
+ /* Setup System LED. Bit 15 then allows to toggle it */
+ sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
+}
+
+static void __init rtl839x_setup(void)
+{
+ pr_info("Registering _machine_restart\n");
+ _machine_restart = rtl839x_restart;
+ _machine_halt = rtl838x_halt;
+
+ /* Setup System LED. Bit 14 of RTL839X_LED_GLB_CTRL then allows to toggle it */
+ sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
+}
+
+static void __init rtl930x_setup(void)
+{
+ pr_info("Registering _machine_restart\n");
+ _machine_restart = rtl930x_restart;
+ _machine_halt = rtl838x_halt;
+
+ if (soc_info.id == 0x9302)
+ sw_w32_mask(0, 3 << 13, RTL9302_LED_GLB_CTRL);
+ else
+ sw_w32_mask(0, 3 << 13, RTL930X_LED_GLB_CTRL);
+}
+
+static void __init rtl931x_setup(void)
+{
+ pr_info("Registering _machine_restart\n");
+ _machine_restart = rtl931x_restart;
+ _machine_halt = rtl838x_halt;
+ sw_w32_mask(0, 3 << 12, RTL931X_LED_GLB_CTRL);
+}
+
void __init plat_mem_setup(void)
{
void *dtb;
* parsed resulting in our memory appearing
*/
__dt_setup_arch(dtb);
+
+ switch (soc_info.family) {
+ case RTL8380_FAMILY_ID:
+ rtl838x_setup();
+ break;
+ case RTL8390_FAMILY_ID:
+ rtl839x_setup();
+ break;
+ case RTL9300_FAMILY_ID:
+ rtl930x_setup();
+ break;
+ case RTL9310_FAMILY_ID:
+ rtl931x_setup();
+ break;
+ }
}
void __init plat_time_init(void)
struct device_node *np;
u32 freq = 500000000;
+ of_clk_init(NULL);
+ timer_probe();
+
np = of_find_node_by_name(NULL, "cpus");
if (!np) {
pr_err("Missing 'cpus' DT node, using default frequency.");
if (of_property_read_u32(np, "frequency", &freq) < 0)
pr_err("No 'frequency' property in DT, using default.");
else
- pr_info("CPU frequency from device tree: %d", freq);
+ pr_info("CPU frequency from device tree: %dMHz", freq / 1000000);
of_node_put(np);
}
mips_hpt_frequency = freq / 2;
-
- pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/clockchips.h>
+#include <linux/init.h>
+#include <asm/time.h>
+#include <linux/interrupt.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
+#include "timer-of.h"
+
+#include <mach-rtl83xx.h>
+
+/*
+ * Timer registers
+ * the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart
+ */
+#define RTL9300_TC_DATA 0x0
+#define RTL9300_TC_CNT 0x4
+#define RTL9300_TC_CTRL 0x8
+#define RTL9300_TC_CTRL_MODE BIT(24)
+#define RTL9300_TC_CTRL_EN BIT(28)
+#define RTL9300_TC_INT 0xc
+#define RTL9300_TC_INT_IP BIT(16)
+#define RTL9300_TC_INT_IE BIT(20)
+
+// Clocksource is using timer 0, clock event uses timer 1
+#define TIMER_CLK_SRC 0
+#define TIMER_CLK_EVT 1
+#define TIMER_BLK_EVT (TIMER_CLK_EVT << 4)
+
+// Timer modes
+#define TIMER_MODE_REPEAT 1
+#define TIMER_MODE_ONCE 0
+
+// Minimum divider is 2
+#define DIVISOR_RTL9300 2
+
+#define N_BITS 28
+
+static void __iomem *rtl9300_sched_reg __read_mostly;
+
+static u64 notrace rtl9300_sched_clock_read(void)
+{
+/* pr_info("In %s: %x\n", __func__, readl_relaxed(rtl9300_sched_reg));
+ dump_stack();*/
+ return readl_relaxed(rtl9300_sched_reg);
+}
+
+static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *clk = dev_id;
+ struct timer_of *to = to_timer_of(clk);
+ u32 v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
+
+ // Acknowledge the IRQ
+ v |= RTL9300_TC_INT_IP;
+ writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
+
+ clk->event_handler(clk);
+ return IRQ_HANDLED;
+}
+
+static void rtl9300_timer_stop(struct timer_of *to)
+{
+ u32 v;
+
+ writel(0, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_CTRL);
+
+ // Acknowledge possibly pending IRQ
+ v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
+ if (v & RTL9300_TC_INT_IP)
+ writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
+}
+
+static void rtl9300_timer_start(struct timer_of *to, int timer, bool periodic)
+{
+ u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300;
+ writel(v, timer_of_base(to) + timer * 0x10 + RTL9300_TC_CTRL);
+}
+
+static int rtl9300_set_next_event(unsigned long delta, struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ rtl9300_timer_stop(to);
+ writel(delta, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
+ rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE);
+ return 0;
+}
+
+static int rtl9300_set_state_periodic(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ rtl9300_timer_stop(to);
+ writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
+ rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_REPEAT);
+ return 0;
+}
+
+static int rtl9300_set_state_oneshot(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ rtl9300_timer_stop(to);
+ writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
+ rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE);
+ return 0;
+}
+
+static int rtl9300_set_state_shutdown(struct clock_event_device *clk)
+{
+ struct timer_of *to = to_timer_of(clk);
+
+ rtl9300_timer_stop(to);
+ return 0;
+}
+
+static struct timer_of t_of = {
+ .flags = TIMER_OF_BASE | TIMER_OF_IRQ | TIMER_OF_CLOCK,
+
+ .clkevt = {
+ .name = "rtl9300_timer",
+ .rating = 350,
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_next_event = rtl9300_set_next_event,
+ .set_state_oneshot = rtl9300_set_state_oneshot,
+ .set_state_periodic = rtl9300_set_state_periodic,
+ .set_state_shutdown = rtl9300_set_state_shutdown,
+ },
+
+ .of_irq = {
+ .name = "ostimer",
+ .handler = rtl9300_timer_interrupt,
+ .flags = IRQF_TIMER,
+ },
+};
+
+static void __init rtl9300_timer_setup(u8 timer)
+{
+ u32 v;
+
+ // Disable timer
+ writel(0, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_CTRL);
+
+ // Acknowledge possibly pending IRQ
+ v = readl(timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT);
+ if (v & RTL9300_TC_INT_IP)
+ writel(v, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT);
+
+ // Setup maximum period (for use as clock-source)
+ writel(0x0fffffff, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_DATA);
+}
+
+
+static int __init rtl9300_timer_init(struct device_node *node)
+{
+ int err = 0;
+ unsigned long rate;
+
+ pr_info("%s: setting up timer\n", __func__);
+
+ err = timer_of_init(node, &t_of);
+ if (err)
+ return err;
+
+ rate = timer_of_rate(&t_of) / DIVISOR_RTL9300;
+ pr_info("Frequency in dts: %ld, my rate is %ld, period %ld\n",
+ timer_of_rate(&t_of), rate, timer_of_period(&t_of));
+ pr_info("With base %08x IRQ: %d\n", (u32)timer_of_base(&t_of), timer_of_irq(&t_of));
+
+ // Configure clock source and register it for scheduling
+ rtl9300_timer_setup(TIMER_CLK_SRC);
+ rtl9300_timer_start(&t_of, TIMER_CLK_SRC, TIMER_MODE_REPEAT);
+
+ rtl9300_sched_reg = timer_of_base(&t_of) + TIMER_CLK_SRC * 0x10 + RTL9300_TC_CNT;
+
+ err = clocksource_mmio_init(rtl9300_sched_reg, node->name, rate , 100, N_BITS,
+ clocksource_mmio_readl_up);
+ if (err)
+ return err;
+
+ sched_clock_register(rtl9300_sched_clock_read, N_BITS, rate);
+
+ // Configure clock event source
+ rtl9300_timer_setup(TIMER_CLK_EVT);
+ clockevents_config_and_register(&t_of.clkevt, rate, 100, 0x0fffffff);
+
+ // Enable interrupt
+ writel(RTL9300_TC_INT_IE, timer_of_base(&t_of) + TIMER_BLK_EVT + RTL9300_TC_INT);
+
+ return err;
+}
+
+TIMER_OF_DECLARE(rtl9300_timer, "realtek,rtl9300-timer", rtl9300_timer_init);
--- /dev/null
+--- a/drivers/clocksource/Kconfig
++++ b/drivers/clocksource/Kconfig
+@@ -126,6 +126,15 @@
+ help
+ Enables the support for the RDA Micro timer driver.
+
++config RTL9300_TIMER
++ bool "Clocksource/timer for the Realtek RTL9300 family of SoCs"
++ depends on MIPS
++ select COMMON_CLK
++ select TIMER_OF
++ select CLKSRC_MMIO
++ help
++ Enables support for the Realtek RTL9300 timer driver.
++
+ config SUN4I_TIMER
+ bool "Sun4i timer driver" if COMPILE_TEST
+ depends on HAS_IOMEM
+@@ -695,5 +704,4 @@
+ select IRQ_DOMAIN
+ help
+ Support for the timer/counter unit of the Ingenic JZ SoCs.
+-
+ endmenu
+--- a/drivers/clocksource/Makefile
++++ b/drivers/clocksource/Makefile
+@@ -61,6 +61,7 @@
+ obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
+ obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
+ obj-$(CONFIG_RDA_TIMER) += timer-rda.o
++obj-$(CONFIG_RTL9300_TIMER) += timer-rtl9300.o
+
+ obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
+ obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
projects / openwrt / staging / lynxis.git / commitdiff