drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.

This was wrong since its introduction on commit '04416108ccea
("drm/i915/cnl: Add registers related to voltage swing sequences.")'

But since no Port F was needed so far we don't need to
propagate fixes back there.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180129232223.766-4-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d8e283cef4483f637b4363a9aed6bb48991d8155..f66f48ffbdd68a313a2563731f9b46c7f56a2403 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1964,7 +1964,7 @@ enum i915_power_well_id {
 #define _CNL_PORT_TX_DW2_LN0_B         0x162648
 #define _CNL_PORT_TX_DW2_LN0_C         0x162C48
 #define _CNL_PORT_TX_DW2_LN0_D         0x162E48
-#define _CNL_PORT_TX_DW2_LN0_F         0x162A48
+#define _CNL_PORT_TX_DW2_LN0_F         0x162848
 #define CNL_PORT_TX_DW2_GRP(port)      _MMIO_PORT6(port, \
                                                    _CNL_PORT_TX_DW2_GRP_AE, \
                                                    _CNL_PORT_TX_DW2_GRP_B, \