arm64/mm: Correct the cache line size warning with non coherent device

If the cache line size is greater than ARCH_DMA_MINALIGN (128),
the warning shows and it's tainted as TAINT_CPU_OUT_OF_SPEC.

However, it's not good because as discussed in the thread [1], the cpu
cache line size will be problem only on non-coherent devices.

Since the coherent flag is already introduced to struct device,
show the warning only if the device is non-coherent device and
ARCH_DMA_MINALIGN is smaller than the cpu cache size.

[1] https://lore.kernel.org/linux-arm-kernel/20180514145703.celnlobzn3uh5tc2@localhost/

Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Tested-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
[catalin.marinas@arm.com: removed 'if' block for WARN_TAINT]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 758af63403141c2a9262797d85676b3e83cf9d1d..d24b7c1ecd9b0683442a72843627aa1bbd718f84 100644 (file)
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -91,6 +91,13 @@ static inline u32 cache_type_cwg(void)
 
 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
 
+static inline int cache_line_size_of_cpu(void)
+{
+       u32 cwg = cache_type_cwg();
+
+       return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
+}
+
 int cache_line_size(void);
 
 /*

diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
index 0c0cd4d26b875366bda231dca92c743bf93cec6b..969fcc3be556b15753ea19141cc5c52a154085df 100644 (file)
--- a/arch/arm64/kernel/cacheinfo.c
+++ b/arch/arm64/kernel/cacheinfo.c
@@ -30,12 +30,10 @@
 
 int cache_line_size(void)
 {
-       u32 cwg = cache_type_cwg();
-
        if (coherency_max_size != 0)
                return coherency_max_size;
 
-       return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
+       return cache_line_size_of_cpu();
 }
 EXPORT_SYMBOL_GPL(cache_line_size);
 

diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 674860e3e478f3015d21b39bd9669a39efdc2be6..ff410195dc1cfa5f8994fedbc55cd0cff61e329c 100644 (file)
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -91,10 +91,6 @@ static int __swiotlb_mmap_pfn(struct vm_area_struct *vma,
 
 static int __init arm64_dma_init(void)
 {
-       WARN_TAINT(ARCH_DMA_MINALIGN < cache_line_size(),
-                  TAINT_CPU_OUT_OF_SPEC,
-                  "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
-                  ARCH_DMA_MINALIGN, cache_line_size());
        return dma_atomic_pool_init(GFP_DMA32, __pgprot(PROT_NORMAL_NC));
 }
 arch_initcall(arm64_dma_init);
@@ -472,6 +468,14 @@ static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
                        const struct iommu_ops *iommu, bool coherent)
 {
+       int cls = cache_line_size_of_cpu();
+
+       WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN,
+                  TAINT_CPU_OUT_OF_SPEC,
+                  "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
+                  dev_driver_string(dev), dev_name(dev),
+                  ARCH_DMA_MINALIGN, cls);
+
        dev->dma_coherent = coherent;
        __iommu_setup_dma_ops(dev, dma_base, size, iommu);