Linux 802.11 Wireless Networking Stack
endef
-CONFOPTS:=MAC80211 CFG80211 NL80211 MAC80211_RC_DEFAULT_PID MAC80211_RC_PID
+# Ralink rt2x00 drivers
+RT61FW:=RT61_Firmware_V1.2.zip
+RT71FW:=RT71W_Firmware_V1.8.zip
+
+define Download/rt61
+ FILE:=$(RT61FW)
+ URL:=http://www.ralinktech.com.tw/data/
+ MD5SUM:=d4c690c93b470bc9a681297c2adc6281
+endef
+$(eval $(call Download,rt61))
+
+define Download/rt71w
+ FILE:=$(RT71FW)
+ URL:=http://www.ralinktech.com.tw/data/
+ MD5SUM:=1e7a5dc574e0268574fcda3fd5cf52f7
+endef
+$(eval $(call Download,rt71w))
+
+define KernelPackage/rt2x00/Default
+ SUBMENU:=Wireless Drivers
+ TITLE:=Ralink Drivers for RT2x00 cards
+ DEPENDS:=@LINUX_2_6_24 @!TARGET_atheros @!TARGET_uml
+endef
+
+define KernelPackage/rt2x00-lib
+$(call KernelPackage/rt2x00/Default)
+ DEPENDS+= @PCI_SUPPORT||USB_SUPPORT +kmod-mac80211
+ TITLE+= (LIB)
+ FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00lib.$(LINUX_KMOD_SUFFIX)
+ AUTOLOAD:=$(call AutoLoad,25,blkcipher ecb arc4 rt2x00lib)
+endef
+
+define KernelPackage/rt2x00-pci
+$(call KernelPackage/rt2x00/Default)
+ DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-lib +kmod-eeprom-93cx6
+ TITLE+= (PCI)
+ FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00pci.$(LINUX_KMOD_SUFFIX)
+ AUTOLOAD:=$(call AutoLoad,26,rt2x00pci)
+endef
+
+define KernelPackage/rt2x00-usb
+$(call KernelPackage/rt2x00/Default)
+ DEPENDS+= @USB_SUPPORT +kmod-rt2x00-lib +kmod-usb-core
+ TITLE+= (USB)
+ FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00usb.$(LINUX_KMOD_SUFFIX)
+ AUTOLOAD:=$(call AutoLoad,26,rt2x00usb)
+endef
+
+define KernelPackage/rt2400-pci
+$(call KernelPackage/rt2x00/Default)
+ DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci
+ TITLE+= (RT2400 PCI)
+ FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2400pci.$(LINUX_KMOD_SUFFIX)
+ AUTOLOAD:=$(call AutoLoad,27,rt2400pci)
+endef
+
+define KernelPackage/rt2500-pci
+$(call KernelPackage/rt2x00/Default)
+ DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci
+ TITLE+= (RT2500 PCI)
+ FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2500pci.$(LINUX_KMOD_SUFFIX)
+ AUTOLOAD:=$(call AutoLoad,27,rt2500pci)
+endef
+
+define KernelPackage/rt2500-usb
+$(call KernelPackage/rt2x00/Default)
+ DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb +kmod-crc-itu-t
+ TITLE+= (RT2500 USB)
+ FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2500usb.$(LINUX_KMOD_SUFFIX)
+ AUTOLOAD:=$(call AutoLoad,27,rt2500usb)
+endef
+
+define KernelPackage/rt61-pci
+$(call KernelPackage/rt2x00/Default)
+ DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci +kmod-crc-itu-t
+ TITLE+= (RT2x61 PCI)
+ FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt61pci.$(LINUX_KMOD_SUFFIX)
+ AUTOLOAD:=$(call AutoLoad,27,rt61pci)
+endef
+
+define KernelPackage/rt73-usb
+ $(call KernelPackage/rt2x00/Default)
+ DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb
+ TITLE+= (RT73 USB)
+ FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt73usb.$(LINUX_KMOD_SUFFIX)
+ AUTOLOAD:=$(call AutoLoad,27,rt73usb)
+endef
+
+RT2X00_CONFOPTS:=CONFIG_RT2X00=y \
+ CONFIG_RT2X00_DEBUG=y \
+ CONFIG_RT2X00_LIB_FIRMWARE=y \
+ CONFIG_RT2X00_LIB_LEDS=y
+
+ifneq ($(CONFIG_PACKAGE_kmod-rt2x00-pci),)
+ RT2X00_CONFOPTS+= CONFIG_RT2X00_LIB_PCI=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt2x00-usb),)
+ RT2X00_CONFOPTS+= CONFIG_RT2X00_LIB_USB=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt2400-pci),)
+ RT2X00_CONFOPTS+= CONFIG_RT2400PCI=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt2500-pci),)
+ RT2X00_CONFOPTS+= CONFIG_RT2500PCI=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt2500-usb),)
+ RT2X00_CONFOPTS+= CONFIG_RT2500USB=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt61-pci),)
+ RT2X00_CONFOPTS+= CONFIG_RT61PCI=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt73-usb),)
+ RT2X00_CONFOPTS+= CONFIG_RT73USB=y
+endif
+
+
+CONFOPTS:=MAC80211 CFG80211 NL80211 MAC80211_RC_DEFAULT_PID MAC80211_RC_PID \
BUILDFLAGS:= \
$(foreach opt,$(CONFOPTS),-DCONFIG_$(opt)) \
$(if $(CONFIG_LEDS_TRIGGERS), -DCONFIG_MAC80211_LEDS -DCONFIG_LEDS_TRIGGERS) \
- -D__CONFIG_MAC80211_RC_DEFAULT=pid
+ -D__CONFIG_MAC80211_RC_DEFAULT=pid \
MAKE_OPTS:= \
CROSS_COMPILE="$(TARGET_CROSS)" \
mkdir -p $(PKG_BUILD_DIR)
$(PKG_UNPACK)
$(if $(QUILT),touch $(PKG_BUILD_DIR)/.quilt_used)
+ unzip -jod $(PKG_BUILD_DIR) $(DL_DIR)/$(RT61FW)
+ unzip -jod $(PKG_BUILD_DIR) $(DL_DIR)/$(RT71FW)
endef
define Build/Compile
$(INSTALL_DATA) ./files/lib/wifi/mac80211.sh $(1)/lib/wifi
endef
+define KernelPackage/rt61-pci/install
+ $(INSTALL_DIR) $(1)/lib/firmware
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/rt2?61*.bin $(1)/lib/firmware/
+endef
+
+define KernelPackage/rt73-usb/install
+ $(INSTALL_DIR) $(1)/lib/firmware
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/rt73.bin $(1)/lib/firmware/
+endef
+
+
$(eval $(call KernelPackage,mac80211))
+$(eval $(call KernelPackage,rt2x00-lib))
+$(eval $(call KernelPackage,rt2x00-pci))
+$(eval $(call KernelPackage,rt2x00-usb))
+$(eval $(call KernelPackage,rt2400-pci))
+$(eval $(call KernelPackage,rt2500-pci))
+$(eval $(call KernelPackage,rt2500-usb))
+$(eval $(call KernelPackage,rt61-pci))
+$(eval $(call KernelPackage,rt73-usb))
+++ /dev/null
-#
-# Copyright (C) 2007 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-# $Id: $
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=rt2x00
-PKG_VERSION:=$(KERNEL_VERSION)
-
-include $(INCLUDE_DIR)/package.mk
-
-
-RT61FW:=RT61_Firmware_V1.2.zip
-RT71FW:=RT71W_Firmware_V1.8.zip
-
-define Download/rt61
- FILE:=$(RT61FW)
- URL:=http://www.ralinktech.com.tw/data/
- MD5SUM:=d4c690c93b470bc9a681297c2adc6281
-endef
-$(eval $(call Download,rt61))
-
-define Download/rt71w
- FILE:=$(RT71FW)
- URL:=http://www.ralinktech.com.tw/data/
- MD5SUM:=1e7a5dc574e0268574fcda3fd5cf52f7
-endef
-$(eval $(call Download,rt71w))
-
-# XXX: remove @!TARGET_* later when we have PCI & USB support properly detected on all targets
-define KernelPackage/rt2x00/Default
- SUBMENU:=Wireless Drivers
- TITLE:=Ralink Drivers for RT2x00 cards
- DEPENDS:=@LINUX_2_6_24 @!TARGET_atheros @!TARGET_uml
-endef
-
-define KernelPackage/rt2x00-lib
-$(call KernelPackage/rt2x00/Default)
- DEPENDS+= @PCI_SUPPORT||USB_SUPPORT +kmod-mac80211
- TITLE+= (LIB)
- FILES:=$(PKG_BUILD_DIR)/rt2x00lib.$(LINUX_KMOD_SUFFIX)
- AUTOLOAD:=$(call AutoLoad,25,blkcipher ecb arc4 rt2x00lib)
-endef
-
-define KernelPackage/rt2x00-pci
-$(call KernelPackage/rt2x00/Default)
- DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-lib +kmod-eeprom-93cx6
- TITLE+= (PCI)
- FILES:=$(PKG_BUILD_DIR)/rt2x00pci.$(LINUX_KMOD_SUFFIX)
- AUTOLOAD:=$(call AutoLoad,26,rt2x00pci)
-endef
-
-define KernelPackage/rt2x00-usb
-$(call KernelPackage/rt2x00/Default)
- DEPENDS+= @USB_SUPPORT +kmod-rt2x00-lib +kmod-usb-core
- TITLE+= (USB)
- FILES:=$(PKG_BUILD_DIR)/rt2x00usb.$(LINUX_KMOD_SUFFIX)
- AUTOLOAD:=$(call AutoLoad,26,rt2x00usb)
-endef
-
-define KernelPackage/rt2400-pci
-$(call KernelPackage/rt2x00/Default)
- DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci
- TITLE+= (RT2400 PCI)
- FILES:=$(PKG_BUILD_DIR)/rt2400pci.$(LINUX_KMOD_SUFFIX)
- AUTOLOAD:=$(call AutoLoad,27,rt2400pci)
-endef
-
-define KernelPackage/rt2500-pci
-$(call KernelPackage/rt2x00/Default)
- DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci
- TITLE+= (RT2500 PCI)
- FILES:=$(PKG_BUILD_DIR)/rt2500pci.$(LINUX_KMOD_SUFFIX)
- AUTOLOAD:=$(call AutoLoad,27,rt2500pci)
-endef
-
-define KernelPackage/rt2500-usb
-$(call KernelPackage/rt2x00/Default)
- DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb +kmod-crc-itu-t
- TITLE+= (RT2500 USB)
- FILES:=$(PKG_BUILD_DIR)/rt2500usb.$(LINUX_KMOD_SUFFIX)
- AUTOLOAD:=$(call AutoLoad,27,rt2500usb)
-endef
-
-define KernelPackage/rt61-pci
-$(call KernelPackage/rt2x00/Default)
- DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci +kmod-crc-itu-t
- TITLE+= (RT2x61 PCI)
- FILES:=$(PKG_BUILD_DIR)/rt61pci.$(LINUX_KMOD_SUFFIX)
- AUTOLOAD:=$(call AutoLoad,27,rt61pci)
-endef
-
-define KernelPackage/rt73-usb
- $(call KernelPackage/rt2x00/Default)
- DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb
- TITLE+= (RT73 USB)
- FILES:=$(PKG_BUILD_DIR)/rt73usb.$(LINUX_KMOD_SUFFIX)
- AUTOLOAD:=$(call AutoLoad,27,rt73usb)
-endef
-
-$(STAMP_PREPARED): $(DL_DIR)/$(PKG_FW6X_NAME) $(DL_DIR)/$(PKG_FW7X_NAME)
-
-PKG_EXTRA_KCONFIG:= \
- CONFIG_MAC80211=y \
- CONFIG_RT2X00=y \
- CONFIG_RT2X00_DEBUG=y \
- CONFIG_RT2X00_LIB_FIRMWARE=y \
-
-ifneq ($(CONFIG_PACKAGE_kmod-rt2x00-pci),)
- PKG_EXTRA_KCONFIG+= CONFIG_RT2X00PCI=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt2x00-usb),)
- PKG_EXTRA_KCONFIG+= CONFIG_RT2X00USB=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt2400-pci),)
- PKG_EXTRA_KCONFIG+= CONFIG_RT2400PCI=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt2500-pci),)
- PKG_EXTRA_KCONFIG+= CONFIG_RT2500PCI=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt2500-usb),)
- PKG_EXTRA_KCONFIG+= CONFIG_RT2500USB=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt61-pci),)
- PKG_EXTRA_KCONFIG+= CONFIG_RT61PCI=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt73-usb),)
- PKG_EXTRA_KCONFIG+= CONFIG_RT73USB=y
-endif
-
-PKG_EXTRA_CFLAGS:= \
- -I$(STAGING_DIR)/usr/include/mac80211 \
- $(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=m,%,$(filter %=m,$(PKG_EXTRA_KCONFIG)))) \
- $(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=y,%,$(filter %=y,$(PKG_EXTRA_KCONFIG)))) \
-
-define Build/Prepare
- $(call Build/Prepare/Default)
- $(CP) src/* $(PKG_BUILD_DIR)/
- unzip -jod $(PKG_BUILD_DIR) $(DL_DIR)/$(RT61FW)
- unzip -jod $(PKG_BUILD_DIR) $(DL_DIR)/$(RT71FW)
-endef
-
-define Build/Configure
- touch $(PKG_BUILD_DIR)/rt2x00_config.h
-endef
-
-define Build/Compile
- $(MAKE) -C "$(LINUX_DIR)" \
- ARCH="$(LINUX_KARCH)" \
- CROSS_COMPILE="$(TARGET_CROSS)" \
- SUBDIRS="$(PKG_BUILD_DIR)" \
- $(PKG_EXTRA_KCONFIG) \
- EXTRA_CFLAGS="$(PKG_EXTRA_CFLAGS)" \
- V="$(V)" \
- modules
-endef
-
-define KernelPackage/rt61-pci/install
- $(INSTALL_DIR) $(1)/lib/firmware
- $(INSTALL_DATA) $(PKG_BUILD_DIR)/rt2?61*.bin $(1)/lib/firmware/
-endef
-
-define KernelPackage/rt73-usb/install
- $(INSTALL_DIR) $(1)/lib/firmware
- $(INSTALL_DATA) $(PKG_BUILD_DIR)/rt73.bin $(1)/lib/firmware/
-endef
-
-$(eval $(call KernelPackage,rt2x00-lib))
-$(eval $(call KernelPackage,rt2x00-pci))
-$(eval $(call KernelPackage,rt2x00-usb))
-$(eval $(call KernelPackage,rt2400-pci))
-$(eval $(call KernelPackage,rt2500-pci))
-$(eval $(call KernelPackage,rt2500-usb))
-$(eval $(call KernelPackage,rt61-pci))
-$(eval $(call KernelPackage,rt73-usb))
+++ /dev/null
- GNU GENERAL PUBLIC LICENSE
- Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
- Preamble
-
- The licenses for most software are designed to take away your
-freedom to share and change it. By contrast, the GNU General Public
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-\f
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- TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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-specifies a version number of this License which applies to it and "any
-later version", you have the option of following the terms and conditions
-either of that version or of any later version published by the Free
-Software Foundation. If the Program does not specify a version number of
-this License, you may choose any version ever published by the Free Software
-Foundation.
-
- 10. If you wish to incorporate parts of the Program into other free
-programs whose distribution conditions are different, write to the author
-to ask for permission. For software which is copyrighted by the Free
-Software Foundation, write to the Free Software Foundation; we sometimes
-make exceptions for this. Our decision will be guided by the two goals
-of preserving the free status of all derivatives of our free software and
-of promoting the sharing and reuse of software generally.
-
- NO WARRANTY
-
- 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
-FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
-OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
-PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
-OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
-TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
-PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
-REPAIR OR CORRECTION.
-
- 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
-REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
-INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
-OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
-TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
-YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
-PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES.
-
- END OF TERMS AND CONDITIONS
-\f
- How to Apply These Terms to Your New Programs
-
- If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
- To do so, attach the following notices to the program. It is safest
-to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
- <one line to give the program's name and a brief idea of what it does.>
- Copyright (C) <year> <name of author>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
-
-Also add information on how to contact you by electronic and paper mail.
-
-If the program is interactive, make it output a short notice like this
-when it starts in an interactive mode:
-
- Gnomovision version 69, Copyright (C) year name of author
- Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
- This is free software, and you are welcome to redistribute it
- under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License. Of course, the commands you use may
-be called something other than `show w' and `show c'; they could even be
-mouse-clicks or menu items--whatever suits your program.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the program, if
-necessary. Here is a sample; alter the names:
-
- Yoyodyne, Inc., hereby disclaims all copyright interest in the program
- `Gnomovision' (which makes passes at compilers) written by James Hacker.
-
- <signature of Ty Coon>, 1 April 1989
- Ty Coon, President of Vice
-
-This General Public License does not permit incorporating your program into
-proprietary programs. If your program is a subroutine library, you may
-consider it more useful to permit linking proprietary applications with the
-library. If this is what you want to do, use the GNU Library General
-Public License instead of this License.
+++ /dev/null
-# Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
-# <http://rt2x00.serialmonkey.com>
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the
-# Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# Module: Makefile
-# Abstract: Makefile for rt2x00 kernel module
-
-#
-# Set the enviroment variables.
-#
-ifndef SUBDIRS
- SUBDIRS=$(shell pwd)
-endif
-
-ifdef KERNDIR
- KERNEL_SOURCES := $(KERNDIR)
-else
- KERNEL_SOURCES := /lib/modules/$(shell uname -r)/build
-endif
-
-ifdef KERNOUT
- KERNEL_OUTPUT := KBUILD_OUTPUT=$(KERNOUT)
-else
- KERNEL_OUTPUT :=
-endif
-
-#
-# Determine if and with what options the rt2x00 drivers should be build
-#
-rt2x00lib-objs := rt2x00dev.o rt2x00mac.o rt2x00config.o rt2x00firmware.o
-
-ifeq ($(CONFIG_RT2X00),y)
- obj-m += rt2x00lib.o
-
-ifeq ($(CONFIG_RT2X00PCI),y)
- obj-m += rt2x00pci.o
-endif
-
-ifeq ($(CONFIG_RT2X00USB),y)
- obj-m += rt2x00usb.o
-endif
-
-ifeq ($(CONFIG_RT2X00_LIB_DEBUGFS),y)
- rt2x00lib-objs += rt2x00debug.o
-endif
-
-ifeq ($(CONFIG_RT2400PCI),y)
- obj-m += rt2400pci.o
-ifeq ($(CONFIG_RT2400PCI_RFKILL),y)
- rt2x00lib-objs += rt2x00rfkill.o
- EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_RFKILL
-endif
-endif
-
-ifeq ($(CONFIG_RT2500PCI),y)
- obj-m += rt2500pci.o
-ifeq ($(CONFIG_RT2500PCI_RFKILL),y)
- rt2x00lib-objs += rt2x00rfkill.o
- EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_RFKILL
-endif
-endif
-
-ifeq ($(CONFIG_RT2500USB),y)
- obj-m += rt2500usb.o
-endif
-
-ifeq ($(CONFIG_RT61PCI),y)
- EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_FIRMWARE
- rt2x00lib-objs += rt2x00firmware.o
- obj-m += rt61pci.o
-ifeq ($(CONFIG_RT61PCI_RFKILL),y)
- rt2x00lib-objs += rt2x00rfkill.o
- EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_RFKILL
-endif
-endif
-
-ifeq ($(CONFIG_RT73USB),y)
- EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_FIRMWARE
- rt2x00lib-objs += rt2x00firmware.o
- obj-m += rt73usb.o
-endif
-
-endif
-
-MAKEFLAGS += --no-print-directory
-EXTRA_CFLAGS := -include $(SUBDIRS)/rt2x00_compat.h $(CFLAGS)
-
-all: default
-
-config_header:
- @if [ ! -f "rt2x00_config.h" ] || [ "rt2x00_config.h" -ot "config" ]; \
- then \
- awk -F = > rt2x00_config.h < config '/^CONFIG.*$\/ \
- { \
- if($$2 == "y") { \
- print "#ifndef " $$1; \
- print "#define " $$1; \
- print "#endif"; \
- print "" \
- } else { \
- print "#undef " $$1; \
- print ""; \
- } \
- }'; \
- fi
-
-default: config_header
- @$(MAKE) -C $(KERNEL_SOURCES) SUBDIRS=$(SUBDIRS) $(KERNEL_OUTPUT) \
- modules
-
-sparse: config_header
- @$(MAKE) -C $(KERNEL_SOURCES) SUBDIRS=$(SUBDIRS) $(KERNEL_OUTPUT) \
- modules C=1 CF=-D__CHECK_ENDIAN__
-
-install: config_header
- @$(MAKE) -C $(KERNEL_SOURCES) SUBDIRS=$(SUBDIRS) $(KERNEL_OUTPUT) \
- INSTALL_MOD_DIR=rt2x00 $(KERNEL_OUTPUT) modules_install
- /sbin/depmod -a
-
-clean:
- @rm -f rt2x00_config.h
- @rm -f Modules.symvers Module.symvers
- @for folder in $(EXTMODDIRS); \
- do \
- rm -f $${folder}/*.o \
- rm -f $${folder}/*.ko \
- rm -f $${folder}/*.s \
- rm -f $${folder}/*.mod.c \
- rm -f $${folder}/.*.cmd \
- rm -f $${folder}/.*.flags \
- rm -f $${folder}/.*.o.d \
- rm -f $${folder}/.*.s.d \
- rm -f $${folder}/.#* \
- rm -f $${folder}/*~ \
- rm -fr $${folder}/.tmp_versions; \
- done
+++ /dev/null
-===============================================================================
- Installation and configuration instructions for the rt2x00 Modules
-===============================================================================
-
-===============================================================================
- Table of contents:
-========================
-
- - 1: Minimal requirements
- - 1.1: kernel
- - 1.2: gcc
- - 1.3: make
- - 2: Hardware
- - 2.1: Chipsets
- - 2.2: RF button
- - 3: Module building & Installation
- - 3.1: Introduction
- - 3.2: Configure
- - 3.3: Build
- - 3.4: Installation
- - 4: Firmware
- - 4.1: Firmware files
- - 4.2: Firmware installation
- - 4.3: Firmware requirements
- - 5: Module loading
- - 5.1: Module load order
- - 5.2: Module load options
- - 6: Interfaces
- - 6.1: Wireless interfaces
- - 6.2: Input interface
- - 7: Interface configuration
- - 7.1: Minimal configuration
- - 7.2: Configuration tools
- - 8: Distribution specific notes
- - 8.1: Debian & derivatives
- - 8.2: Fedora
- - 8.3: Gentoo
- - 8.4: Mandriva
- - 9: Problems & Troubleshooting
- - 9.1: Debug information
- - 9.2: Debugfs
- - 9.3: Bug reporting
- - 10: Problems & Workarounds
- - 10.1: udev interface naming
- - 10.2: BUG - ifdown & ifup radio failure
- - 11: TODO list
- - 12: Contact us
-
-
-===============================================================================
- 1: Minimal requirements:
-=======================================
-
-===================
- 1.1: kernel
-=========
-
- - The minimal required kernel version is 2.6.22-rc1
-
- - It is important that the installed kernel sources match
- the running kernel. Unless you are crosscompiling and you
- know what you are doing.
-
- - Depending on what rt2x00 components will be built,
- some kernel configuration options are mandatory.
- It does however not matter if these options are compiled
- into the kernel or compiled as module.
-
- Kernel config option Required for component
- ------------------------------------------------------------------
- # CONFIG_NET_RADIO all
- # CONFIG_MAC80211 all
- # CONFIG_WLAN_80211 all
- # CONFIG_PCI rt2400pci, rt2500pci, rt61pci
- # CONFIG_USB rt2500usb, rt73usb
- # CONFIG_HOTPLUG rt61pci, rt73usb
- # CONFIG_FW_LOADER rt61pci, rt73usb
- # CONFIG_CRC_ITU_T rt61pci, rt73usb
- # CONFIG_DEBUG_FS rt2x00 (optional, only for debug)
- # CONFIG_RFKILL rt2400pci, rt2500pci, rt61pci (optional,
- only for button support)
-
-===================
- 1.2: GCC
-=========
-
- - For building the rt2x00 components the same gcc version is required
- as was used to build your target kernel.
-
-===================
- 1.3: make
-=========
-
- - The program 'make' needs to be installed on the system. There are no
- further special requirements for this program.
-
-===============================================================================
- 2: Hardware
-=======================================
-
-===================
- 2.1: Chipsets
-=========
-
- Support for each Ralink wireless chipset has been split into separate drivers.
-
- # rt2400pci
- - chipset: rt2400
- - supports: rt2460
- - bus type: PCI/PCMCIA/miniPCI
- # rt2500pci
- - chipset: rt2500
- - supports: rt2560
- - bus type: PCI/PCMCIA/miniPCI
- # rt2500usb
- - chipset: rt2570
- - supports: rt2570
- - bus type: USB
- # rt61pci
- - chipset: rt61 (or rt2600)
- - supports: rt2561, rt2561s, rt2661
- - bus type: PCI/PCMCIA/miniPCI
- # rt73usb
- - chipset: rt73
- - supports: rt2571(w), rt2573, rt2671
- - bus type: USB
-
-===================
- 2.2: RF button
-=========
-
- On some occasions the Ralink chipset has been built into a laptop.
- If that is the case, there usually is a hardware button that controls the
- radio of the wireless interface.
- If you have such a hardware device, make sure you enable hardware button
- support for your device in the configuration before building the rt2x00
- components.
- Note: This feature requires the enabling of the rfkill driver in the kernel.
-
-===============================================================================
- 3: Module building & Installation
-=======================================
-
-===================
- 3.1: Introduction
-=========
-
- The following steps in this chapter concerning module building and
- installation need to be performed for each kernel. This means that
- after each kernel upgrade the modules need to be rebuild and
- reinstalled in order to make them work with the new kernel.
-
-===================
- 3.2: Configure
-=========
-
- Before starting to build the rt2x00 components it is recommended to look into
- the 'config' file first. In this file you can configure which components of
- rt2x00 should be built. And even more importantly, you can configure with
- what options the components will be built.
- To build all the rt2x00 drivers (with debug capabilities enabled) no changes
- in the configuration file are required. For most users this would be
- sufficient to start working with rt2x00.
-
-===================
- 3.3: Build
-=========
-
- To build all rt2x00 components which were enabled in the configuration file
- simply run (root privileges not required):
-
- # $ make
-
- All modules (.ko files) will be created in the current directory.
-
-===================
- 3.4: Installation
-=========
-
- All rt2x00 modules can be installed by doing (with root privileges):
-
- # $ make install
-
- With this command all rt2x00 modules (including rfkill and d80211) will be
- created in a newly created folder named 'rt2x00' inside the kernel modules
- directory (usually '/lib/modules/$(uname -r)/').
-
-
-==============================================================================
- 4: Firmware
-=======================================
-
-===================
- 4.1: Firmware files
-=========
-
- rt61pci and rt73usb require firmware to be available while loading the module.
- The following firmware files are available for each driver:
-
- # rt61pci
- - rt2561.bin
- - rt2561s.bin
- - rt2661.bin
-
- # rt73usb
- - rt73.bin
-
-===================
- 4.2: Firmware installation
-=========
-
- The latest firmware files are available in a separate .zip archive and can be
- downloaded from the support page on the Ralink website at
- http://www.ralinktech.com.
- Note that by a high level of logic, Ralink has named their firmware for rt73
- chipsets "rt71W" with a comment that it is for the rt2571W and rt2671 devices.
- For rt61pci 3 seperate firmware files are available, which one is used depends
- on which RT chip is on the device. Usually it is best to install all files.
- To install the firmware the firmware files need to be manually copied to the
- systems firmware folder (usually '/lib/firmware/') the exact folder depends
- on the distribution. When in doubt consult the distributions documentation.
-
-===================
- 4.3: Firmware requirements
-=========
-
- To load firmware when the module is loaded the hotplug daemon should be
- running. Make sure you either enable hotplugging manually before loading the
- module, or make sure hotplugging is enabled during the system boot process.
-
-
-==============================================================================
- 5: Module loading
-=======================================
-
-===================
- 5.1: Module load order
-=========
-
- When the modules have been properly installed by following the installation
- instructions from the previous section, the module handlers (i.e. modprobe)
- will automaticly resolve all module dependencies when loading the device
- specific driver.
-
- When loading the modules manually with insmod, you should load them in the
- following order:
-
- # eeprom_93cx6.ko (optional, only required for pci devices)
- # rt2x00lib.ko
- # rt2x00pci.ko (optional, only required for pci devices)
- # rt2x00usb.ko (optional, only required for usb devices)
- # rt2400pci.ko (optional, only required for rt2400 support)
- # rt2500pci.ko (optional, only required for rt2500 support)
- # rt2500usb.ko (optional, only required for rt2570 support)
- # rt61pci.ko (optional, only required for rt61 support)
- # rt73usb.ko (optional, only required for rt73 support)
-
-===================
- 5.2: Module load options
-=========
-
- None.
-
-
-==============================================================================
- 6: Interfaces
-=======================================
-
-===================
- 6.1: Wireless interfaces
-=========
-
- After loading the modules two interfaces will now be visible in ifconfig and
- iwconfig, namely wmaster0 and wlan0. The first device is the so called master
- device which is can be used by some userspace tools, but normally can be
- ignored by the user. The second interface wlan0 is the client interface which
- the user can configure.
- With rt2x00 it is possible to run multiple client interfaces with
- only a single device. 1 client interface can run in adhoc, managed or master
- mode while a second interface can run in monitor mode at the same time.
- More client interfaces can be added by issuing the following command
- (with root privileges):
-
- # $ echo -n <name> > /sys/class/ieee80211/<dev>/add_iface
-
- where the variable <name> is the name of the client interface that should be
- added (i.e. wlan1), and <dev> is the physical device where the new client
- interface should be attached to (i.e. phy0).
-
-===================
- 6.2: Input interface
-=========
-
- When the rfkill driver is being used a new input device with the name of the
- device specific module where the button belongs to will have been created.
- Whenever the user presses the hardware button the rfkill driver will
- automatically make sure the hardware radio is being disabled or enabled
- accordingly. When the user has opened the input device the radio will
- not be automatically controlled, but instead the input device will
- report all button events (KEY_RFKILL) to userspace where the user
- could have setup script to do all the work that has to be executed.
- This means that while the input device is opened, the user is responsible
- for the correct behaviour.
-
-
-==============================================================================
- 7: Interface configuration
-=======================================
-
-===================
- 7.1: Minimal configuration
-=========
-
- - After loading the modules the interface should be configured to start
- an association or work in monitor mode. The following steps are required
- for a minimal configuration to associate with a non-encrypted access point.
-
- - Before bringing the client interface up, the working mode should be set:
-
- # $ iwconfig wlan0 mode managed
-
- - Configuration parts like essid and channel can be set before or after the
- client interface has been brought up.
-
- - It is usually a good idea to set the essid:
-
- # $ iwconfig wlan0 essid myessid
-
- - In some situations the device also requires the channel to be manually set:
-
- # $ iwconfig wlan0 channel mychannel
-
- - To bring the client interface up:
-
- # $ ifconfig wlan0 up
-
- - After the client interface has been brought up, scanning can be performed
- to check if the desired AP is being detected.
-
- # $ iwlist wlan0 scan
-
- - To start an association attempt, the AP address should be set:
-
- # $ iwconfig wlan0 ap mybssid
-
-===================
- 7.2: Configuration tools
-=========
-
- To configure the interface several tools are possible, the most basic tools
- are the wireless-tools that provide the iwconfig, iwpriv and iwlist commands.
- For WPA connections the wireless-tools are not sufficient, to configure the
- interface for WPA wireless network wpa_supplicant is required.
- For master mode functionality it is possible to only use the wireless-tools,
- but it is recommended to use hostapd instead. This tool offers the best
- functionality.
- For all configuration tools (wireless-tools, wpa_supplicant and hostapd) are
- manuals and howto's present in the manpages or on the internet. It is adviced
- to have at least read the manpages before using the tools for a better
- understanding on configuring the interface.
-
-
-==============================================================================
- 8: Distribution specific notes
-=======================================
-
-===================
- 8.1: Debian & derivatives
-=========
-
- In some instances installing the rt2x00 drivers on debian will result
- in the problem that the files are being copied into the wrong folder,
- which results in the fact that the driver cannot be loaded.
- Installing the drivers should be done manually in this case,
- please refer to the distributions documentation regarding the proper
- location of the kernel modules.
-
-===================
- 8.2: Fedora
-=========
-
- Although rt2x00 contains many backward compatibility fixes to ensure
- that all rt2x00 components will be able to compile and run on all
- systems that meet the minimal requirements, this does not work in all
- situations when the Fedora kernels are being used.
- The problem lies in the fact that Fedora (like most other distributions)
- heavily patch their kernel for better stability and more features.
- Unlike the other distributions however, Fedora does not pay attention to
- compatibility for external kernel drivers. This means that compiling rt2x00
- while using a Fedora kernel will result in compile errors regarding unknown
- fields in structures or problems with function arguments.
- For rt2x00 it is impossible to make all checks to support all Fedora kernel
- releases. This means that when rt2x00 compilation is failing while using a
- Fedora kernel we cannot give support for the compilation steps.
- We recommend the user to complain to the Fedora developers when this problem
- occurs.
- If the user has managed to compile rt2x00 for a Fedora kernel we will
- give support for possible problems while working with rt2x00. So the only
- part we do not support is the building of rt2x00.
- Please note that when you have edited the rt2x00 code to make it compile,
- it is advised to state those changes in bugreports while reporting other
- problems with rt2x00.
-
-===================
- 8.3: Gentoo
-=========
-
- rt2x00 can also be found in portage, both the beta releases and the cvs tree.
- Because rt2x00 is still experimental these ebuild are still masked, this means
- that before you can emerge them they first have to be unmasked.
- Gentoo provides various instructions on how this can be done on their website.
-
-===================
- 8.4: Mandriva
-=========
-
- In some instances installing the rt2x00 drivers on Mandriva will result
- in the problem that the files are being copied into the wrong folder,
- which results in the fact that the driver cannot be loaded.
- Installing the drivers should be done manually in this case,
- please refer to the distributions documentation regarding the proper
- location of the kernel modules.
-
-
-==============================================================================
- 9: Problems & Troubleshooting
-=======================================
-
-===================
- 9.1: Debug information
-=========
-
- When reporting problems make sure the driver has been compiled with debug
- enabled.
- If you have done so, the debug output can be found in the output
- of 'dmesg' and also in /var/log/messages and /var/log/syslog.
-
-===================
- 9.2: Debugfs
-=========
-
- rt2x00 provides several debugfs entries which can be used to help
- provide more information about the interface.
- To see the rt2x00 debugfs entries, debugfs should first be mounted,
- to do this you should issue the following command:
-
- # $ mount -t debugfs none /debug
-
- Where /debug is the directy on which the debugfs entries should appear,
- make sure this directory exists when mounting debugfs.
- With the debugfs folder, the rt2x00 folder with the rt2x00 debugfs entries
- will be created. Within the rt2x00 folder, each physical device will be
- represented by a folder named after the interface which belongs to this
- device. Within the folder the following files can be found:
-
- # register
- - This file contains the register contents of the interface.
- # eeprom
- - This file contains the eeprom contents of the interface.
-
-===================
- 9.3: Bug reporting
-=========
-
- When reporting a bug or problem with the rt2x00 module,
- make sure you report the following information:
- # How to reproduce
- # RT2x00 debug output, usually found in /var/log/messages
- # Module version
- # Wireless card chipset, model and manufacturer
- # Kernel version (i.e. 2.6.17)
- # Hardware architecture (i.e. x86, AMD64, Sparc)
- # rt2x00 code changes done by the user
- # Anything else you may think will help us resolve the issue
-
-
-==============================================================================
- 10: Problems & Workarounds
-=======================================
-
-===================
- 10.1: udev interface naming
-=========
-
- In some cases when loading the rt2x00 drivers the interface names are
- different from the names used in this README. This is usually caused by the
- udev handler who has set some rules regarding the interface. These rules
- are usually set up by the distribution and have been created especially for
- for the legacy driver and their strange behavior.
- To change the rules udev applies to your interface you should edit the udev
- rules stored in /etc/udev/rules.d/ (exact location might be different
- depending on distribution).
- When editing this file, search for the line that contains something like this:
-
- # ACTION=="add", SUBSYSTEM=="net", DRIVERS=="?*",
- # SYSFS{address}=="<mac address>", NAME="<interface>"
- (line has been wrapped due to max line length limit)
-
- Where <mac address> is the hardware address of your wireless networkcard,
- and <interface> is the interface name the interface takes as soon as the
- rt2x00 modules are loaded.
- This line should be changed to look like:
-
- # ACTION=="add", SUBSYSTEM=="net", DRIVERS=="?*",
- # SYSFS{address}=="<mac address>", SYSFS{type}=="801",
- # NAME="wmaster0"
- # ACTION=="add", SUBSYSTEM=="net", DRIVERS=="?*",
- # SYSFS{address}=="<mac address>", NAME="wlan0"
- (the 2 lines have been wrapped due to max line length limit)
-
- Where <mac address> is the hardware address of your wireless networkcard,
- and thus should be the same as on the original line.
-
-===================
- 10.2: BUG - ifdown & ifup radio failure
-=========
-
- It is a known issue (and BUG) that the driver will fail to correctly resume
- its radio operations after the interface has been brought down and up again.
- It is still unknown what the cause for this issue could be, besides the fact
- that for some reason the device's registers have been incorrectly initialized.
- This issue also has impact on the device status after a suspend/resume
- operation. There is no known workaround for this yet.
-
-
-==============================================================================
- 11: TODO list
-=======================================
- See http://rt2x00.serialmonkey.com/wiki/index.php/Rt2x00_beta
-
-==============================================================================
- 12: Contact us
-=======================================
-
- - Website
- # http://rt2x00.serialmonkey.com/
- # http://rt2x00.serialmonkey.com/wiki/index.php/Rt2x00_beta
-
- - Forums:
- # http://rt2x00.serialmonkey.com/phpBB2/
-
- - Mailing list:
- # general: rt2400-general@lists.sourceforge.net
- # developers: rt2400-devel@lists.sourceforge.net
-
- - Sourceforge:
- # http://sourceforge.net/projects/rt2400
-
+++ /dev/null
-A big thanks to all the developers, testers and supporters of
-the rt2x00 Linux source code.
-
-Thanks to the projects main developers:
-* Mark Wallis - mwallis@serialmonkey.com
-* Ivo van Doorn - IvDoorn@gmail.com
-* Luis Correia - lfcorreia@users.sf.net
-* Robin Cornelius - robin.cornelius@gmail.com
-* Gertjan van Wingerde - gwingerde@kpnplanet.nl
-* Romain - spy84464@hotmail.com
-
-Special thanks to the contributors of this project:
-* Adisorn Ermongkonchai - moo7822-wlan@yahoo.com
-* Amir Shalem - amir@boom.org.il
-* Bernd Petrovitsch - bernd@firmix.at
-* Bruno - bruno123@users.sf.net
-* Chris Houston - chris.houston@atterotech.com
-* Defekt - defekt@liquid-nexus.net
-* Edvard - eaglenest@users.sourceforge.net
-* Flavio Stanchina - flavio@stanchina.net
-* Gregor Glomm - gg@seh.de
-* Heikki Pernu - heikki.pernu@nekonet.fi
-* Jerzy Kozera - nordom@tlen.pl
-* Joachim Gleißner - jg@suse.de
-* John Coppens - john@jcoppens.com
-* Jonathan Hudson
-* KrissN - krissn@op.pl
-* Luca Tettamanti - kronos.it@gmail.com
-* Magnus Damm - magnus.damm@gmail.com
-* Mags
-* Mathias Klien - ma_klein@gmx.de
-* Meelis Roos - mroos@linux.ee
-* Michal Ludvig - michal@logix.cz
-* Miguel - miguel.marte2@verizon.net
-* Mike Skinner
-* Olivier Cornu - o.cornu@gmail.com
-* Paul Hampson - Paul.Hampson@anu.edu.au
-* Philippe Rousselot - amazilia@users.sourceforge.net
-* Remco - remco@d-compu.dyndns.org
-* Sergey Vlasov - vsu@altlinux.ru
-* Stephen Warren - SWarren@nvidia.com
-* Stuart Rackham - srackham@methods.co.nz
-* Thor Harald Johansen - thorhajo@gmail.com
-* Tor Petterson - 2r@manowar.dk
-
-Special thanks:
-* Ralink - http://www.ralinktech.com.tw
- For releasing their rt2400/rt2500/rt2570 drivers under the GPL,
- and their assistance in providing documentation to help development.
-* Minitar - www.minitar.com
- For working together with Ralink on releasing the
- rt2400/rt2500/rt2570 drivers under the GPL.
-* All the people that have assisted with the rt2400/rt2500/rt2570 source
- and hence progressed the rt2x00 along the way.
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2400pci
- Abstract: rt2400pci device specific routines.
- Supported chipsets: RT2460.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2400pci"
-
-#include <linux/delay.h>
-#include <linux/etherdevice.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/eeprom_93cx6.h>
-
-#include "rt2x00.h"
-#include "rt2x00pci.h"
-#include "rt2400pci.h"
-
-/*
- * Register access.
- * All access to the CSR registers will go through the methods
- * rt2x00pci_register_read and rt2x00pci_register_write.
- * BBP and RF register require indirect register access,
- * and use the CSR registers BBPCSR and RFCSR to achieve this.
- * These indirect registers work with busy bits,
- * and we will try maximal REGISTER_BUSY_COUNT times to access
- * the register while taking a REGISTER_BUSY_DELAY us delay
- * between each attampt. When the busy bit is still set at that time,
- * the access attempt is considered to have failed,
- * and we will print an error.
- */
-static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- unsigned int i;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
- if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
- break;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- return reg;
-}
-
-static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u8 value)
-{
- u32 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt2400pci_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
- ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
- return;
- }
-
- /*
- * Write the data into the BBP.
- */
- reg = 0;
- rt2x00_set_field32(®, BBPCSR_VALUE, value);
- rt2x00_set_field32(®, BBPCSR_REGNUM, word);
- rt2x00_set_field32(®, BBPCSR_BUSY, 1);
- rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
-
- rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
-}
-
-static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u8 *value)
-{
- u32 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt2400pci_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
- ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
- return;
- }
-
- /*
- * Write the request into the BBP.
- */
- reg = 0;
- rt2x00_set_field32(®, BBPCSR_REGNUM, word);
- rt2x00_set_field32(®, BBPCSR_BUSY, 1);
- rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
-
- rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt2400pci_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
- ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
- *value = 0xff;
- return;
- }
-
- *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
-}
-
-static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u32 value)
-{
- u32 reg;
- unsigned int i;
-
- if (!word)
- return;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
- if (!rt2x00_get_field32(reg, RFCSR_BUSY))
- goto rf_write;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
- return;
-
-rf_write:
- reg = 0;
- rt2x00_set_field32(®, RFCSR_VALUE, value);
- rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
- rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
- rt2x00_set_field32(®, RFCSR_BUSY, 1);
-
- rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
- rt2x00_rf_write(rt2x00dev, word, value);
-}
-
-static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
-{
- struct rt2x00_dev *rt2x00dev = eeprom->data;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR21, ®);
-
- eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
- eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
- eeprom->reg_data_clock =
- !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
- eeprom->reg_chip_select =
- !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
-}
-
-static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
-{
- struct rt2x00_dev *rt2x00dev = eeprom->data;
- u32 reg = 0;
-
- rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
- rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
- rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
- !!eeprom->reg_data_clock);
- rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
- !!eeprom->reg_chip_select);
-
- rt2x00pci_register_write(rt2x00dev, CSR21, reg);
-}
-
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
-
-static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 *data)
-{
- rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 data)
-{
- rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static const struct rt2x00debug rt2400pci_rt2x00debug = {
- .owner = THIS_MODULE,
- .csr = {
- .read = rt2400pci_read_csr,
- .write = rt2400pci_write_csr,
- .word_size = sizeof(u32),
- .word_count = CSR_REG_SIZE / sizeof(u32),
- },
- .eeprom = {
- .read = rt2x00_eeprom_read,
- .write = rt2x00_eeprom_write,
- .word_size = sizeof(u16),
- .word_count = EEPROM_SIZE / sizeof(u16),
- },
- .bbp = {
- .read = rt2400pci_bbp_read,
- .write = rt2400pci_bbp_write,
- .word_size = sizeof(u8),
- .word_count = BBP_SIZE / sizeof(u8),
- },
- .rf = {
- .read = rt2x00_rf_read,
- .write = rt2400pci_rf_write,
- .word_size = sizeof(u32),
- .word_count = RF_SIZE / sizeof(u32),
- },
-};
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
-#ifdef CONFIG_RT2400PCI_RFKILL
-static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
- return rt2x00_get_field32(reg, GPIOCSR_BIT0);
-}
-#else
-#define rt2400pci_rfkill_poll NULL
-#endif /* CONFIG_RT2400PCI_RFKILL */
-
-/*
- * Configuration handlers.
- */
-static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
- __le32 *mac)
-{
- rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
- (2 * sizeof(__le32)));
-}
-
-static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
- __le32 *bssid)
-{
- rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
- (2 * sizeof(__le32)));
-}
-
-static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
- const int tsf_sync)
-{
- u32 reg;
-
- rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-
- /*
- * Enable beacon config
- */
- rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
- rt2x00_set_field32(®, BCNCSR1_PRELOAD,
- PREAMBLE + get_duration(IEEE80211_HEADER, 20));
- rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
-
- /*
- * Enable synchronisation.
- */
- rt2x00pci_register_read(rt2x00dev, CSR14, ®);
- rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
- rt2x00_set_field32(®, CSR14_TBCN, 1);
- rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
- rt2x00_set_field32(®, CSR14_TSF_SYNC, tsf_sync);
- rt2x00pci_register_write(rt2x00dev, CSR14, reg);
-}
-
-static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
- const int short_preamble,
- const int ack_timeout,
- const int ack_consume_time)
-{
- int preamble_mask;
- u32 reg;
-
- /*
- * When short preamble is enabled, we should set bit 0x08
- */
- preamble_mask = short_preamble << 3;
-
- rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
- rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, ack_timeout);
- rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
- rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
- rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble_mask);
- rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
- rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
- rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
- rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
- rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
- rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
- rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
- rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
- rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
- rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
- rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
-}
-
-static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
- const int basic_rate_mask)
-{
- rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
-}
-
-static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
- struct rf_channel *rf)
-{
- /*
- * Switch on tuning bits.
- */
- rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
- rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
-
- rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
- rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
- rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
-
- /*
- * RF2420 chipset don't need any additional actions.
- */
- if (rt2x00_rf(&rt2x00dev->chip, RF2420))
- return;
-
- /*
- * For the RT2421 chipsets we need to write an invalid
- * reference clock rate to activate auto_tune.
- * After that we set the value back to the correct channel.
- */
- rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
- rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
- rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
-
- msleep(1);
-
- rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
- rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
- rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
-
- msleep(1);
-
- /*
- * Switch off tuning bits.
- */
- rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
- rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
-
- rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
- rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
-
- /*
- * Clear false CRC during channel switch.
- */
- rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
-}
-
-static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
-{
- rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
-}
-
-static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
- int antenna_tx, int antenna_rx)
-{
- u8 r1;
- u8 r4;
-
- rt2400pci_bbp_read(rt2x00dev, 4, &r4);
- rt2400pci_bbp_read(rt2x00dev, 1, &r1);
-
- /*
- * Configure the TX antenna.
- */
- switch (antenna_tx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
- break;
- }
-
- /*
- * Configure the RX antenna.
- */
- switch (antenna_rx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
- break;
- }
-
- rt2400pci_bbp_write(rt2x00dev, 4, r4);
- rt2400pci_bbp_write(rt2x00dev, 1, r1);
-}
-
-static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
- struct rt2x00lib_conf *libconf)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR11, ®);
- rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
- rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR18, ®);
- rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
- rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
- rt2x00pci_register_write(rt2x00dev, CSR18, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR19, ®);
- rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
- rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
- rt2x00pci_register_write(rt2x00dev, CSR19, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
- rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
- rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
- rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR12, ®);
- rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
- libconf->conf->beacon_int * 16);
- rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
- libconf->conf->beacon_int * 16);
- rt2x00pci_register_write(rt2x00dev, CSR12, reg);
-}
-
-static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
- const unsigned int flags,
- struct rt2x00lib_conf *libconf)
-{
- if (flags & CONFIG_UPDATE_PHYMODE)
- rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
- if (flags & CONFIG_UPDATE_CHANNEL)
- rt2400pci_config_channel(rt2x00dev, &libconf->rf);
- if (flags & CONFIG_UPDATE_TXPOWER)
- rt2400pci_config_txpower(rt2x00dev,
- libconf->conf->power_level);
- if (flags & CONFIG_UPDATE_ANTENNA)
- rt2400pci_config_antenna(rt2x00dev,
- libconf->conf->antenna_sel_tx,
- libconf->conf->antenna_sel_rx);
- if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
- rt2400pci_config_duration(rt2x00dev, libconf);
-}
-
-static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
- struct ieee80211_tx_queue_params *params)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR11, ®);
- rt2x00_set_field32(®, CSR11_CWMIN, params->cw_min);
- rt2x00_set_field32(®, CSR11_CWMAX, params->cw_max);
- rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-}
-
-/*
- * LED functions.
- */
-static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
-
- rt2x00_set_field32(®, LEDCSR_ON_PERIOD, 70);
- rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, 30);
-
- if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
- rt2x00_set_field32(®, LEDCSR_LINK, 1);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0);
- } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
- rt2x00_set_field32(®, LEDCSR_LINK, 0);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 1);
- } else {
- rt2x00_set_field32(®, LEDCSR_LINK, 1);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 1);
- }
-
- rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
-}
-
-static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
- rt2x00_set_field32(®, LEDCSR_LINK, 0);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0);
- rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
-}
-
-/*
- * Link tuning
- */
-static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- u8 bbp;
-
- /*
- * Update FCS error count from register.
- */
- rt2x00pci_register_read(rt2x00dev, CNT0, ®);
- rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
-
- /*
- * Update False CCA count from register.
- */
- rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
- rt2x00dev->link.false_cca = bbp;
-}
-
-static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
-{
- rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
- rt2x00dev->link.vgc_level = 0x08;
-}
-
-static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
- u8 reg;
-
- /*
- * The link tuner should not run longer then 60 seconds,
- * and should run once every 2 seconds.
- */
- if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
- return;
-
- /*
- * Base r13 link tuning on the false cca count.
- */
- rt2400pci_bbp_read(rt2x00dev, 13, ®);
-
- if (rt2x00dev->link.false_cca > 512 && reg < 0x20) {
- rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
- rt2x00dev->link.vgc_level = reg;
- } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) {
- rt2400pci_bbp_write(rt2x00dev, 13, --reg);
- rt2x00dev->link.vgc_level = reg;
- }
-}
-
-/*
- * Initialization functions.
- */
-static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring = rt2x00dev->rx;
- struct data_desc *rxd;
- unsigned int i;
- u32 word;
-
- memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
- for (i = 0; i < ring->stats.limit; i++) {
- rxd = ring->entry[i].priv;
-
- rt2x00_desc_read(rxd, 2, &word);
- rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
- ring->data_size);
- rt2x00_desc_write(rxd, 2, word);
-
- rt2x00_desc_read(rxd, 1, &word);
- rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
- ring->entry[i].data_dma);
- rt2x00_desc_write(rxd, 1, word);
-
- rt2x00_desc_read(rxd, 0, &word);
- rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
- rt2x00_desc_write(rxd, 0, word);
- }
-
- rt2x00_ring_index_clear(rt2x00dev->rx);
-}
-
-static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
-{
- struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
- struct data_desc *txd;
- unsigned int i;
- u32 word;
-
- memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
- for (i = 0; i < ring->stats.limit; i++) {
- txd = ring->entry[i].priv;
-
- rt2x00_desc_read(txd, 1, &word);
- rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
- ring->entry[i].data_dma);
- rt2x00_desc_write(txd, 1, word);
-
- rt2x00_desc_read(txd, 2, &word);
- rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
- ring->data_size);
- rt2x00_desc_write(txd, 2, word);
-
- rt2x00_desc_read(txd, 0, &word);
- rt2x00_set_field32(&word, TXD_W0_VALID, 0);
- rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
- rt2x00_desc_write(txd, 0, word);
- }
-
- rt2x00_ring_index_clear(ring);
-}
-
-static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Initialize rings.
- */
- rt2400pci_init_rxring(rt2x00dev);
- rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
- rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
- rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
- rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
-
- /*
- * Initialize registers.
- */
- rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
- rt2x00_set_field32(®, TXCSR2_TXD_SIZE,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
- rt2x00_set_field32(®, TXCSR2_NUM_TXD,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
- rt2x00_set_field32(®, TXCSR2_NUM_ATIM,
- rt2x00dev->bcn[1].stats.limit);
- rt2x00_set_field32(®, TXCSR2_NUM_PRIO,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
- rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
- rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
- rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
- rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
- rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
- rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
- rt2x00dev->bcn[1].data_dma);
- rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
- rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
- rt2x00dev->bcn[0].data_dma);
- rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
-
- rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
- rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
- rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
- rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
- rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
- rt2x00dev->rx->data_dma);
- rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
-
- return 0;
-}
-
-static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
- rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
- rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
- rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
-
- rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
- rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
- rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
- rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
- rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR9, ®);
- rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
- (rt2x00dev->rx->data_size / 128));
- rt2x00pci_register_write(rt2x00dev, CSR9, reg);
-
- rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
- rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
- rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
- rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
- rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
- rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
-
- rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
- rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
- rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
- rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
- rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
- rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
- rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
- rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
-
- rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
-
- if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
- return -EBUSY;
-
- rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
- rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
-
- rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
- rt2x00_set_field32(®, MACCSR2_DELAY, 64);
- rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
-
- rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
- rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR1, ®);
- rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
- rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
- rt2x00_set_field32(®, CSR1_HOST_READY, 0);
- rt2x00pci_register_write(rt2x00dev, CSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR1, ®);
- rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
- rt2x00_set_field32(®, CSR1_HOST_READY, 1);
- rt2x00pci_register_write(rt2x00dev, CSR1, reg);
-
- /*
- * We must clear the FCS and FIFO error count.
- * These registers are cleared on read,
- * so we may pass a useless variable to store the value.
- */
- rt2x00pci_register_read(rt2x00dev, CNT0, ®);
- rt2x00pci_register_read(rt2x00dev, CNT4, ®);
-
- return 0;
-}
-
-static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
-{
- unsigned int i;
- u16 eeprom;
- u8 reg_id;
- u8 value;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2400pci_bbp_read(rt2x00dev, 0, &value);
- if ((value != 0xff) && (value != 0x00))
- goto continue_csr_init;
- NOTICE(rt2x00dev, "Waiting for BBP register.\n");
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
- return -EACCES;
-
-continue_csr_init:
- rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
- rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
- rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
- rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
- rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
- rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
- rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
- rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
- rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
- rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
- rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
- rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
- rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
- rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
-
- DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
- for (i = 0; i < EEPROM_BBP_SIZE; i++) {
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
-
- if (eeprom != 0xffff && eeprom != 0x0000) {
- reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
- value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
- DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
- reg_id, value);
- rt2400pci_bbp_write(rt2x00dev, reg_id, value);
- }
- }
- DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
-
- return 0;
-}
-
-/*
- * Device state switch handlers.
- */
-static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
- rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
- state == STATE_RADIO_RX_OFF);
- rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
-static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- int mask = (state == STATE_RADIO_IRQ_OFF);
- u32 reg;
-
- /*
- * When interrupts are being enabled, the interrupt registers
- * should clear the register to assure a clean state.
- */
- if (state == STATE_RADIO_IRQ_ON) {
- rt2x00pci_register_read(rt2x00dev, CSR7, ®);
- rt2x00pci_register_write(rt2x00dev, CSR7, reg);
- }
-
- /*
- * Only toggle the interrupts bits we are going to use.
- * Non-checked interrupt bits are disabled by default.
- */
- rt2x00pci_register_read(rt2x00dev, CSR8, ®);
- rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
- rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
- rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
- rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
- rt2x00_set_field32(®, CSR8_RXDONE, mask);
- rt2x00pci_register_write(rt2x00dev, CSR8, reg);
-}
-
-static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
- /*
- * Initialize all registers.
- */
- if (rt2400pci_init_rings(rt2x00dev) ||
- rt2400pci_init_registers(rt2x00dev) ||
- rt2400pci_init_bbp(rt2x00dev)) {
- ERROR(rt2x00dev, "Register initialization failed.\n");
- return -EIO;
- }
-
- /*
- * Enable interrupts.
- */
- rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
-
- /*
- * Enable LED
- */
- rt2400pci_enable_led(rt2x00dev);
-
- return 0;
-}
-
-static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Disable LED
- */
- rt2400pci_disable_led(rt2x00dev);
-
- rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
-
- /*
- * Disable synchronisation.
- */
- rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-
- /*
- * Cancel RX and TX.
- */
- rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
- rt2x00_set_field32(®, TXCSR0_ABORT, 1);
- rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-
- /*
- * Disable interrupts.
- */
- rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
-}
-
-static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- u32 reg;
- unsigned int i;
- char put_to_sleep;
- char bbp_state;
- char rf_state;
-
- put_to_sleep = (state != STATE_AWAKE);
-
- rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
- rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
- rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
- rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
- rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
- rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
-
- /*
- * Device is not guaranteed to be in the requested state yet.
- * We must wait until the register indicates that the
- * device has entered the correct state.
- */
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
- bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
- rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
- if (bbp_state == state && rf_state == state)
- return 0;
- msleep(10);
- }
-
- NOTICE(rt2x00dev, "Device failed to enter state %d, "
- "current device state: bbp %d and rf %d.\n",
- state, bbp_state, rf_state);
-
- return -EBUSY;
-}
-
-static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- int retval = 0;
-
- switch (state) {
- case STATE_RADIO_ON:
- retval = rt2400pci_enable_radio(rt2x00dev);
- break;
- case STATE_RADIO_OFF:
- rt2400pci_disable_radio(rt2x00dev);
- break;
- case STATE_RADIO_RX_ON:
- case STATE_RADIO_RX_OFF:
- rt2400pci_toggle_rx(rt2x00dev, state);
- break;
- case STATE_DEEP_SLEEP:
- case STATE_SLEEP:
- case STATE_STANDBY:
- case STATE_AWAKE:
- retval = rt2400pci_set_state(rt2x00dev, state);
- break;
- default:
- retval = -ENOTSUPP;
- break;
- }
-
- return retval;
-}
-
-/*
- * TX descriptor initialization
- */
-static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
- struct data_desc *txd,
- struct txdata_entry_desc *desc,
- struct ieee80211_hdr *ieee80211hdr,
- unsigned int length,
- struct ieee80211_tx_control *control)
-{
- u32 word;
- u32 signal = 0;
- u32 service = 0;
- u32 length_high = 0;
- u32 length_low = 0;
-
- /*
- * The PLCP values should be treated as if they
- * were BBP values.
- */
- rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
- rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
- rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
-
- rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
- rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
- rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
-
- rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
- rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
- rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
-
- rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
- rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
- rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
-
- /*
- * Start writing the descriptor words.
- */
- rt2x00_desc_read(txd, 2, &word);
- rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
- rt2x00_desc_write(txd, 2, word);
-
- rt2x00_desc_read(txd, 3, &word);
- rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
- rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
- rt2x00_desc_write(txd, 3, word);
-
- rt2x00_desc_read(txd, 4, &word);
- rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
- rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
- rt2x00_desc_write(txd, 4, word);
-
- rt2x00_desc_read(txd, 0, &word);
- rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
- rt2x00_set_field32(&word, TXD_W0_VALID, 1);
- rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
- test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_ACK,
- !(control->flags & IEEE80211_TXCTL_NO_ACK));
- rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
- test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_RTS,
- test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
- rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
- !!(control->flags &
- IEEE80211_TXCTL_LONG_RETRY_LIMIT));
- rt2x00_desc_write(txd, 0, word);
-}
-
-/*
- * TX data initialization
- */
-static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
- unsigned int queue)
-{
- u32 reg;
-
- if (queue == IEEE80211_TX_QUEUE_BEACON) {
- rt2x00pci_register_read(rt2x00dev, CSR14, ®);
- if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
- rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
- rt2x00pci_register_write(rt2x00dev, CSR14, reg);
- }
- return;
- }
-
- rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
- if (queue == IEEE80211_TX_QUEUE_DATA0)
- rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
- else if (queue == IEEE80211_TX_QUEUE_DATA1)
- rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
- else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
- rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
- rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-}
-
-/*
- * RX control handlers
- */
-static void rt2400pci_fill_rxdone(struct data_entry *entry,
- struct rxdata_entry_desc *desc)
-{
- struct data_desc *rxd = entry->priv;
- u32 word0;
- u32 word2;
-
- rt2x00_desc_read(rxd, 0, &word0);
- rt2x00_desc_read(rxd, 2, &word2);
-
- desc->flags = 0;
- if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
- desc->flags |= RX_FLAG_FAILED_FCS_CRC;
- if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
- desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
-
- /*
- * Obtain the status about this packet.
- */
- desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
- desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
- entry->ring->rt2x00dev->rssi_offset;
- desc->ofdm = 0;
- desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
-}
-
-/*
- * Interrupt functions.
- */
-static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
-{
- struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
- struct data_entry *entry;
- struct data_desc *txd;
- u32 word;
- int tx_status;
- int retry;
-
- while (!rt2x00_ring_empty(ring)) {
- entry = rt2x00_get_data_entry_done(ring);
- txd = entry->priv;
- rt2x00_desc_read(txd, 0, &word);
-
- if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
- !rt2x00_get_field32(word, TXD_W0_VALID))
- break;
-
- /*
- * Obtain the status about this packet.
- */
- tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
- retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
-
- rt2x00lib_txdone(entry, tx_status, retry);
-
- /*
- * Make this entry available for reuse.
- */
- entry->flags = 0;
- rt2x00_set_field32(&word, TXD_W0_VALID, 0);
- rt2x00_desc_write(txd, 0, word);
- rt2x00_ring_index_done_inc(ring);
- }
-
- /*
- * If the data ring was full before the txdone handler
- * we must make sure the packet queue in the mac80211 stack
- * is reenabled when the txdone handler has finished.
- */
- entry = ring->entry;
- if (!rt2x00_ring_full(ring))
- ieee80211_wake_queue(rt2x00dev->hw,
- entry->tx_status.control.queue);
-}
-
-static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
-{
- struct rt2x00_dev *rt2x00dev = dev_instance;
- u32 reg;
-
- /*
- * Get the interrupt sources & saved to local variable.
- * Write register value back to clear pending interrupts.
- */
- rt2x00pci_register_read(rt2x00dev, CSR7, ®);
- rt2x00pci_register_write(rt2x00dev, CSR7, reg);
-
- if (!reg)
- return IRQ_NONE;
-
- if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
- return IRQ_HANDLED;
-
- /*
- * Handle interrupts, walk through all bits
- * and run the tasks, the bits are checked in order of
- * priority.
- */
-
- /*
- * 1 - Beacon timer expired interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
- rt2x00lib_beacondone(rt2x00dev);
-
- /*
- * 2 - Rx ring done interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_RXDONE))
- rt2x00pci_rxdone(rt2x00dev);
-
- /*
- * 3 - Atim ring transmit done interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
- rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
-
- /*
- * 4 - Priority ring transmit done interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
- rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
-
- /*
- * 5 - Tx ring transmit done interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
- rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
-
- return IRQ_HANDLED;
-}
-
-/*
- * Device probe functions.
- */
-static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- struct eeprom_93cx6 eeprom;
- u32 reg;
- u16 word;
- u8 *mac;
-
- rt2x00pci_register_read(rt2x00dev, CSR21, ®);
-
- eeprom.data = rt2x00dev;
- eeprom.register_read = rt2400pci_eepromregister_read;
- eeprom.register_write = rt2400pci_eepromregister_write;
- eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
- PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
- eeprom.reg_data_in = 0;
- eeprom.reg_data_out = 0;
- eeprom.reg_data_clock = 0;
- eeprom.reg_chip_select = 0;
-
- eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
- EEPROM_SIZE / sizeof(u16));
-
- /*
- * Start validation of the data that has been read.
- */
- mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
- if (!is_valid_ether_addr(mac)) {
- DECLARE_MAC_BUF(macbuf);
-
- random_ether_addr(mac);
- EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
- if (word == 0xffff) {
- ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- u16 value;
- u16 eeprom;
-
- /*
- * Read EEPROM word for configuration.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-
- /*
- * Identify RF chipset.
- */
- value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
- rt2x00pci_register_read(rt2x00dev, CSR0, ®);
- rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
-
- if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
- ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
- return -ENODEV;
- }
-
- /*
- * Identify default antenna configuration.
- */
- rt2x00dev->hw->conf.antenna_sel_tx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
- rt2x00dev->hw->conf.antenna_sel_rx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
-
- /*
- * Store led mode, for correct led behaviour.
- */
- rt2x00dev->led_mode =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
-
- /*
- * Detect if this device has an hardware controlled radio.
- */
-#ifdef CONFIG_RT2400PCI_RFKILL
- if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
- __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
-#endif /* CONFIG_RT2400PCI_RFKILL */
-
- /*
- * Check if the BBP tuning should be enabled.
- */
- if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
- __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
-
- return 0;
-}
-
-/*
- * RF value list for RF2420 & RF2421
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg[] = {
- { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
- { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
- { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
- { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
- { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
- { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
- { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
- { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
- { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
- { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
- { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
- { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
- { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
- { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
-};
-
-static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
-{
- struct hw_mode_spec *spec = &rt2x00dev->spec;
- u8 *txpower;
- unsigned int i;
-
- /*
- * Initialize all hw fields.
- */
- rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
- rt2x00dev->hw->extra_tx_headroom = 0;
- rt2x00dev->hw->max_signal = MAX_SIGNAL;
- rt2x00dev->hw->max_rssi = MAX_RX_SSI;
- rt2x00dev->hw->queues = 2;
-
- SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
- SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
- rt2x00_eeprom_addr(rt2x00dev,
- EEPROM_MAC_ADDR_0));
-
- /*
- * Convert tx_power array in eeprom.
- */
- txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
- for (i = 0; i < 14; i++)
- txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
- /*
- * Initialize hw_mode information.
- */
- spec->num_modes = 1;
- spec->num_rates = 4;
- spec->tx_power_a = NULL;
- spec->tx_power_bg = txpower;
- spec->tx_power_default = DEFAULT_TXPOWER;
-
- spec->num_channels = ARRAY_SIZE(rf_vals_bg);
- spec->channels = rf_vals_bg;
-}
-
-static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
-{
- int retval;
-
- /*
- * Allocate eeprom data.
- */
- retval = rt2400pci_validate_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- retval = rt2400pci_init_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- /*
- * Initialize hw specifications.
- */
- rt2400pci_probe_hw_mode(rt2x00dev);
-
- /*
- * This device requires the beacon ring
- */
- __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
-
- /*
- * Set the rssi offset.
- */
- rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
-
- return 0;
-}
-
-/*
- * IEEE80211 stack callback functions.
- */
-static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed_flags,
- unsigned int *total_flags,
- int mc_count,
- struct dev_addr_list *mc_list)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct interface *intf = &rt2x00dev->interface;
- u32 reg;
-
- /*
- * Mask off any flags we are going to ignore from
- * the total_flags field.
- */
- *total_flags &=
- FIF_ALLMULTI |
- FIF_FCSFAIL |
- FIF_PLCPFAIL |
- FIF_CONTROL |
- FIF_OTHER_BSS |
- FIF_PROMISC_IN_BSS;
-
- /*
- * Apply some rules to the filters:
- * - Some filters imply different filters to be set.
- * - Some things we can't filter out at all.
- * - Some filters are set based on interface type.
- */
- *total_flags |= FIF_ALLMULTI;
- if (*total_flags & FIF_OTHER_BSS ||
- *total_flags & FIF_PROMISC_IN_BSS)
- *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
- if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
- *total_flags |= FIF_PROMISC_IN_BSS;
-
- /*
- * Check if there is any work left for us.
- */
- if (intf->filter == *total_flags)
- return;
- intf->filter = *total_flags;
-
- /*
- * Start configuration steps.
- * Note that the version error will always be dropped
- * since there is no filter for it at this time.
- */
- rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
- rt2x00_set_field32(®, RXCSR0_DROP_CRC,
- !(*total_flags & FIF_FCSFAIL));
- rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
- !(*total_flags & FIF_PLCPFAIL));
- rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
- !(*total_flags & FIF_CONTROL));
- rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field32(®, RXCSR0_DROP_TODS,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
- rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
-static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
- u32 short_retry, u32 long_retry)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR11, ®);
- rt2x00_set_field32(®, CSR11_LONG_RETRY, long_retry);
- rt2x00_set_field32(®, CSR11_SHORT_RETRY, short_retry);
- rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
- return 0;
-}
-
-static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
- int queue,
- const struct ieee80211_tx_queue_params *params)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- /*
- * We don't support variating cw_min and cw_max variables
- * per queue. So by default we only configure the TX queue,
- * and ignore all other configurations.
- */
- if (queue != IEEE80211_TX_QUEUE_DATA0)
- return -EINVAL;
-
- if (rt2x00mac_conf_tx(hw, queue, params))
- return -EINVAL;
-
- /*
- * Write configuration to register.
- */
- rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
-
- return 0;
-}
-
-static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u64 tsf;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR17, ®);
- tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
- rt2x00pci_register_read(rt2x00dev, CSR16, ®);
- tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
-
- return tsf;
-}
-
-static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- rt2x00pci_register_write(rt2x00dev, CSR16, 0);
- rt2x00pci_register_write(rt2x00dev, CSR17, 0);
-}
-
-static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR15, ®);
- return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
-}
-
-static const struct ieee80211_ops rt2400pci_mac80211_ops = {
- .tx = rt2x00mac_tx,
- .start = rt2x00mac_start,
- .stop = rt2x00mac_stop,
- .add_interface = rt2x00mac_add_interface,
- .remove_interface = rt2x00mac_remove_interface,
- .config = rt2x00mac_config,
- .config_interface = rt2x00mac_config_interface,
- .configure_filter = rt2400pci_configure_filter,
- .get_stats = rt2x00mac_get_stats,
- .set_retry_limit = rt2400pci_set_retry_limit,
- .erp_ie_changed = rt2x00mac_erp_ie_changed,
- .conf_tx = rt2400pci_conf_tx,
- .get_tx_stats = rt2x00mac_get_tx_stats,
- .get_tsf = rt2400pci_get_tsf,
- .reset_tsf = rt2400pci_reset_tsf,
- .beacon_update = rt2x00pci_beacon_update,
- .tx_last_beacon = rt2400pci_tx_last_beacon,
-};
-
-static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
- .irq_handler = rt2400pci_interrupt,
- .probe_hw = rt2400pci_probe_hw,
- .initialize = rt2x00pci_initialize,
- .uninitialize = rt2x00pci_uninitialize,
- .set_device_state = rt2400pci_set_device_state,
- .rfkill_poll = rt2400pci_rfkill_poll,
- .link_stats = rt2400pci_link_stats,
- .reset_tuner = rt2400pci_reset_tuner,
- .link_tuner = rt2400pci_link_tuner,
- .write_tx_desc = rt2400pci_write_tx_desc,
- .write_tx_data = rt2x00pci_write_tx_data,
- .kick_tx_queue = rt2400pci_kick_tx_queue,
- .fill_rxdone = rt2400pci_fill_rxdone,
- .config_mac_addr = rt2400pci_config_mac_addr,
- .config_bssid = rt2400pci_config_bssid,
- .config_type = rt2400pci_config_type,
- .config_preamble = rt2400pci_config_preamble,
- .config = rt2400pci_config,
-};
-
-static const struct rt2x00_ops rt2400pci_ops = {
- .name = DRV_NAME,
- .rxd_size = RXD_DESC_SIZE,
- .txd_size = TXD_DESC_SIZE,
- .eeprom_size = EEPROM_SIZE,
- .rf_size = RF_SIZE,
- .lib = &rt2400pci_rt2x00_ops,
- .hw = &rt2400pci_mac80211_ops,
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
- .debugfs = &rt2400pci_rt2x00debug,
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-};
-
-/*
- * RT2400pci module information.
- */
-static struct pci_device_id rt2400pci_device_table[] = {
- { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
- { 0, }
-};
-
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
-MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
-MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
-MODULE_LICENSE("GPL");
-
-static struct pci_driver rt2400pci_driver = {
- .name = DRV_NAME,
- .id_table = rt2400pci_device_table,
- .probe = rt2x00pci_probe,
- .remove = __devexit_p(rt2x00pci_remove),
- .suspend = rt2x00pci_suspend,
- .resume = rt2x00pci_resume,
-};
-
-static int __init rt2400pci_init(void)
-{
- return pci_register_driver(&rt2400pci_driver);
-}
-
-static void __exit rt2400pci_exit(void)
-{
- pci_unregister_driver(&rt2400pci_driver);
-}
-
-module_init(rt2400pci_init);
-module_exit(rt2400pci_exit);
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2400pci
- Abstract: Data structures and registers for the rt2400pci module.
- Supported chipsets: RT2460.
- */
-
-#ifndef RT2400PCI_H
-#define RT2400PCI_H
-
-/*
- * RF chip defines.
- */
-#define RF2420 0x0000
-#define RF2421 0x0001
-
-/*
- * Signal information.
- * Defaul offset is required for RSSI <-> dBm conversion.
- */
-#define MAX_SIGNAL 100
-#define MAX_RX_SSI -1
-#define DEFAULT_RSSI_OFFSET 100
-
-/*
- * Register layout information.
- */
-#define CSR_REG_BASE 0x0000
-#define CSR_REG_SIZE 0x014c
-#define EEPROM_BASE 0x0000
-#define EEPROM_SIZE 0x0100
-#define BBP_SIZE 0x0020
-#define RF_SIZE 0x0010
-
-/*
- * Control/Status Registers(CSR).
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * CSR0: ASIC revision number.
- */
-#define CSR0 0x0000
-
-/*
- * CSR1: System control register.
- * SOFT_RESET: Software reset, 1: reset, 0: normal.
- * BBP_RESET: Hardware reset, 1: reset, 0, release.
- * HOST_READY: Host ready after initialization.
- */
-#define CSR1 0x0004
-#define CSR1_SOFT_RESET FIELD32(0x00000001)
-#define CSR1_BBP_RESET FIELD32(0x00000002)
-#define CSR1_HOST_READY FIELD32(0x00000004)
-
-/*
- * CSR2: System admin status register (invalid).
- */
-#define CSR2 0x0008
-
-/*
- * CSR3: STA MAC address register 0.
- */
-#define CSR3 0x000c
-#define CSR3_BYTE0 FIELD32(0x000000ff)
-#define CSR3_BYTE1 FIELD32(0x0000ff00)
-#define CSR3_BYTE2 FIELD32(0x00ff0000)
-#define CSR3_BYTE3 FIELD32(0xff000000)
-
-/*
- * CSR4: STA MAC address register 1.
- */
-#define CSR4 0x0010
-#define CSR4_BYTE4 FIELD32(0x000000ff)
-#define CSR4_BYTE5 FIELD32(0x0000ff00)
-
-/*
- * CSR5: BSSID register 0.
- */
-#define CSR5 0x0014
-#define CSR5_BYTE0 FIELD32(0x000000ff)
-#define CSR5_BYTE1 FIELD32(0x0000ff00)
-#define CSR5_BYTE2 FIELD32(0x00ff0000)
-#define CSR5_BYTE3 FIELD32(0xff000000)
-
-/*
- * CSR6: BSSID register 1.
- */
-#define CSR6 0x0018
-#define CSR6_BYTE4 FIELD32(0x000000ff)
-#define CSR6_BYTE5 FIELD32(0x0000ff00)
-
-/*
- * CSR7: Interrupt source register.
- * Write 1 to clear interrupt.
- * TBCN_EXPIRE: Beacon timer expired interrupt.
- * TWAKE_EXPIRE: Wakeup timer expired interrupt.
- * TATIMW_EXPIRE: Timer of atim window expired interrupt.
- * TXDONE_TXRING: Tx ring transmit done interrupt.
- * TXDONE_ATIMRING: Atim ring transmit done interrupt.
- * TXDONE_PRIORING: Priority ring transmit done interrupt.
- * RXDONE: Receive done interrupt.
- */
-#define CSR7 0x001c
-#define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
-#define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
-#define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
-#define CSR7_TXDONE_TXRING FIELD32(0x00000008)
-#define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
-#define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
-#define CSR7_RXDONE FIELD32(0x00000040)
-
-/*
- * CSR8: Interrupt mask register.
- * Write 1 to mask interrupt.
- * TBCN_EXPIRE: Beacon timer expired interrupt.
- * TWAKE_EXPIRE: Wakeup timer expired interrupt.
- * TATIMW_EXPIRE: Timer of atim window expired interrupt.
- * TXDONE_TXRING: Tx ring transmit done interrupt.
- * TXDONE_ATIMRING: Atim ring transmit done interrupt.
- * TXDONE_PRIORING: Priority ring transmit done interrupt.
- * RXDONE: Receive done interrupt.
- */
-#define CSR8 0x0020
-#define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
-#define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
-#define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
-#define CSR8_TXDONE_TXRING FIELD32(0x00000008)
-#define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
-#define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
-#define CSR8_RXDONE FIELD32(0x00000040)
-
-/*
- * CSR9: Maximum frame length register.
- * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
- */
-#define CSR9 0x0024
-#define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
-
-/*
- * CSR11: Back-off control register.
- * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
- * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
- * SLOT_TIME: Slot time, default is 20us for 802.11b.
- * LONG_RETRY: Long retry count.
- * SHORT_RETRY: Short retry count.
- */
-#define CSR11 0x002c
-#define CSR11_CWMIN FIELD32(0x0000000f)
-#define CSR11_CWMAX FIELD32(0x000000f0)
-#define CSR11_SLOT_TIME FIELD32(0x00001f00)
-#define CSR11_LONG_RETRY FIELD32(0x00ff0000)
-#define CSR11_SHORT_RETRY FIELD32(0xff000000)
-
-/*
- * CSR12: Synchronization configuration register 0.
- * All units in 1/16 TU.
- * BEACON_INTERVAL: Beacon interval, default is 100 TU.
- * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
- */
-#define CSR12 0x0030
-#define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
-#define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
-
-/*
- * CSR13: Synchronization configuration register 1.
- * All units in 1/16 TU.
- * ATIMW_DURATION: Atim window duration.
- * CFP_PERIOD: Cfp period, default is 0 TU.
- */
-#define CSR13 0x0034
-#define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
-#define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
-
-/*
- * CSR14: Synchronization control register.
- * TSF_COUNT: Enable tsf auto counting.
- * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
- * TBCN: Enable tbcn with reload value.
- * TCFP: Enable tcfp & cfp / cp switching.
- * TATIMW: Enable tatimw & atim window switching.
- * BEACON_GEN: Enable beacon generator.
- * CFP_COUNT_PRELOAD: Cfp count preload value.
- * TBCM_PRELOAD: Tbcn preload value in units of 64us.
- */
-#define CSR14 0x0038
-#define CSR14_TSF_COUNT FIELD32(0x00000001)
-#define CSR14_TSF_SYNC FIELD32(0x00000006)
-#define CSR14_TBCN FIELD32(0x00000008)
-#define CSR14_TCFP FIELD32(0x00000010)
-#define CSR14_TATIMW FIELD32(0x00000020)
-#define CSR14_BEACON_GEN FIELD32(0x00000040)
-#define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
-#define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
-
-/*
- * CSR15: Synchronization status register.
- * CFP: ASIC is in contention-free period.
- * ATIMW: ASIC is in ATIM window.
- * BEACON_SENT: Beacon is send.
- */
-#define CSR15 0x003c
-#define CSR15_CFP FIELD32(0x00000001)
-#define CSR15_ATIMW FIELD32(0x00000002)
-#define CSR15_BEACON_SENT FIELD32(0x00000004)
-
-/*
- * CSR16: TSF timer register 0.
- */
-#define CSR16 0x0040
-#define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
-
-/*
- * CSR17: TSF timer register 1.
- */
-#define CSR17 0x0044
-#define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
-
-/*
- * CSR18: IFS timer register 0.
- * SIFS: Sifs, default is 10 us.
- * PIFS: Pifs, default is 30 us.
- */
-#define CSR18 0x0048
-#define CSR18_SIFS FIELD32(0x0000ffff)
-#define CSR18_PIFS FIELD32(0xffff0000)
-
-/*
- * CSR19: IFS timer register 1.
- * DIFS: Difs, default is 50 us.
- * EIFS: Eifs, default is 364 us.
- */
-#define CSR19 0x004c
-#define CSR19_DIFS FIELD32(0x0000ffff)
-#define CSR19_EIFS FIELD32(0xffff0000)
-
-/*
- * CSR20: Wakeup timer register.
- * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
- * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
- * AUTOWAKE: Enable auto wakeup / sleep mechanism.
- */
-#define CSR20 0x0050
-#define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
-#define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
-#define CSR20_AUTOWAKE FIELD32(0x01000000)
-
-/*
- * CSR21: EEPROM control register.
- * RELOAD: Write 1 to reload eeprom content.
- * TYPE_93C46: 1: 93c46, 0:93c66.
- */
-#define CSR21 0x0054
-#define CSR21_RELOAD FIELD32(0x00000001)
-#define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
-#define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
-#define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
-#define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
-#define CSR21_TYPE_93C46 FIELD32(0x00000020)
-
-/*
- * CSR22: CFP control register.
- * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
- * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
- */
-#define CSR22 0x0058
-#define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
-#define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
-
-/*
- * Transmit related CSRs.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * TXCSR0: TX Control Register.
- * KICK_TX: Kick tx ring.
- * KICK_ATIM: Kick atim ring.
- * KICK_PRIO: Kick priority ring.
- * ABORT: Abort all transmit related ring operation.
- */
-#define TXCSR0 0x0060
-#define TXCSR0_KICK_TX FIELD32(0x00000001)
-#define TXCSR0_KICK_ATIM FIELD32(0x00000002)
-#define TXCSR0_KICK_PRIO FIELD32(0x00000004)
-#define TXCSR0_ABORT FIELD32(0x00000008)
-
-/*
- * TXCSR1: TX Configuration Register.
- * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
- * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
- * TSF_OFFSET: Insert tsf offset.
- * AUTORESPONDER: Enable auto responder which include ack & cts.
- */
-#define TXCSR1 0x0064
-#define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
-#define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
-#define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
-#define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
-
-/*
- * TXCSR2: Tx descriptor configuration register.
- * TXD_SIZE: Tx descriptor size, default is 48.
- * NUM_TXD: Number of tx entries in ring.
- * NUM_ATIM: Number of atim entries in ring.
- * NUM_PRIO: Number of priority entries in ring.
- */
-#define TXCSR2 0x0068
-#define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
-#define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
-#define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
-#define TXCSR2_NUM_PRIO FIELD32(0xff000000)
-
-/*
- * TXCSR3: TX Ring Base address register.
- */
-#define TXCSR3 0x006c
-#define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * TXCSR4: TX Atim Ring Base address register.
- */
-#define TXCSR4 0x0070
-#define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * TXCSR5: TX Prio Ring Base address register.
- */
-#define TXCSR5 0x0074
-#define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * TXCSR6: Beacon Base address register.
- */
-#define TXCSR6 0x0078
-#define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * TXCSR7: Auto responder control register.
- * AR_POWERMANAGEMENT: Auto responder power management bit.
- */
-#define TXCSR7 0x007c
-#define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
-
-/*
- * Receive related CSRs.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * RXCSR0: RX Control Register.
- * DISABLE_RX: Disable rx engine.
- * DROP_CRC: Drop crc error.
- * DROP_PHYSICAL: Drop physical error.
- * DROP_CONTROL: Drop control frame.
- * DROP_NOT_TO_ME: Drop not to me unicast frame.
- * DROP_TODS: Drop frame tods bit is true.
- * DROP_VERSION_ERROR: Drop version error frame.
- * PASS_CRC: Pass all packets with crc attached.
- */
-#define RXCSR0 0x0080
-#define RXCSR0_DISABLE_RX FIELD32(0x00000001)
-#define RXCSR0_DROP_CRC FIELD32(0x00000002)
-#define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
-#define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
-#define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
-#define RXCSR0_DROP_TODS FIELD32(0x00000020)
-#define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
-#define RXCSR0_PASS_CRC FIELD32(0x00000080)
-
-/*
- * RXCSR1: RX descriptor configuration register.
- * RXD_SIZE: Rx descriptor size, default is 32b.
- * NUM_RXD: Number of rx entries in ring.
- */
-#define RXCSR1 0x0084
-#define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
-#define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
-
-/*
- * RXCSR2: RX Ring base address register.
- */
-#define RXCSR2 0x0088
-#define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * RXCSR3: BBP ID register for Rx operation.
- * BBP_ID#: BBP register # id.
- * BBP_ID#_VALID: BBP register # id is valid or not.
- */
-#define RXCSR3 0x0090
-#define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
-#define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
-#define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
-#define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
-#define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
-#define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
-#define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
-#define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
-
-/*
- * RXCSR4: BBP ID register for Rx operation.
- * BBP_ID#: BBP register # id.
- * BBP_ID#_VALID: BBP register # id is valid or not.
- */
-#define RXCSR4 0x0094
-#define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
-#define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
-#define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
-#define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
-
-/*
- * ARCSR0: Auto Responder PLCP config register 0.
- * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
- * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
- */
-#define ARCSR0 0x0098
-#define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
-#define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
-#define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
-#define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
-
-/*
- * ARCSR1: Auto Responder PLCP config register 1.
- * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
- * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
- */
-#define ARCSR1 0x009c
-#define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
-#define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
-#define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
-#define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
-
-/*
- * Miscellaneous Registers.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * PCICSR: PCI control register.
- * BIG_ENDIAN: 1: big endian, 0: little endian.
- * RX_TRESHOLD: Rx threshold in dw to start pci access
- * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
- * TX_TRESHOLD: Tx threshold in dw to start pci access
- * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
- * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
- * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
- */
-#define PCICSR 0x008c
-#define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
-#define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
-#define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
-#define PCICSR_BURST_LENTH FIELD32(0x00000060)
-#define PCICSR_ENABLE_CLK FIELD32(0x00000080)
-
-/*
- * CNT0: FCS error count.
- * FCS_ERROR: FCS error count, cleared when read.
- */
-#define CNT0 0x00a0
-#define CNT0_FCS_ERROR FIELD32(0x0000ffff)
-
-/*
- * Statistic Register.
- * CNT1: PLCP error count.
- * CNT2: Long error count.
- * CNT3: CCA false alarm count.
- * CNT4: Rx FIFO overflow count.
- * CNT5: Tx FIFO underrun count.
- */
-#define TIMECSR2 0x00a8
-#define CNT1 0x00ac
-#define CNT2 0x00b0
-#define TIMECSR3 0x00b4
-#define CNT3 0x00b8
-#define CNT4 0x00bc
-#define CNT5 0x00c0
-
-/*
- * Baseband Control Register.
- */
-
-/*
- * PWRCSR0: Power mode configuration register.
- */
-#define PWRCSR0 0x00c4
-
-/*
- * Power state transition time registers.
- */
-#define PSCSR0 0x00c8
-#define PSCSR1 0x00cc
-#define PSCSR2 0x00d0
-#define PSCSR3 0x00d4
-
-/*
- * PWRCSR1: Manual power control / status register.
- * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
- * SET_STATE: Set state. Write 1 to trigger, self cleared.
- * BBP_DESIRE_STATE: BBP desired state.
- * RF_DESIRE_STATE: RF desired state.
- * BBP_CURR_STATE: BBP current state.
- * RF_CURR_STATE: RF current state.
- * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
- */
-#define PWRCSR1 0x00d8
-#define PWRCSR1_SET_STATE FIELD32(0x00000001)
-#define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
-#define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
-#define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
-#define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
-#define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
-
-/*
- * TIMECSR: Timer control register.
- * US_COUNT: 1 us timer count in units of clock cycles.
- * US_64_COUNT: 64 us timer count in units of 1 us timer.
- * BEACON_EXPECT: Beacon expect window.
- */
-#define TIMECSR 0x00dc
-#define TIMECSR_US_COUNT FIELD32(0x000000ff)
-#define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
-#define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
-
-/*
- * MACCSR0: MAC configuration register 0.
- */
-#define MACCSR0 0x00e0
-
-/*
- * MACCSR1: MAC configuration register 1.
- * KICK_RX: Kick one-shot rx in one-shot rx mode.
- * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
- * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
- * AUTO_TXBBP: Auto tx logic access bbp control register.
- * AUTO_RXBBP: Auto rx logic access bbp control register.
- * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
- * INTERSIL_IF: Intersil if calibration pin.
- */
-#define MACCSR1 0x00e4
-#define MACCSR1_KICK_RX FIELD32(0x00000001)
-#define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
-#define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
-#define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
-#define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
-#define MACCSR1_LOOPBACK FIELD32(0x00000060)
-#define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
-
-/*
- * RALINKCSR: Ralink Rx auto-reset BBCR.
- * AR_BBP_DATA#: Auto reset BBP register # data.
- * AR_BBP_ID#: Auto reset BBP register # id.
- */
-#define RALINKCSR 0x00e8
-#define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
-#define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
-#define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
-#define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
-
-/*
- * BCNCSR: Beacon interval control register.
- * CHANGE: Write one to change beacon interval.
- * DELTATIME: The delta time value.
- * NUM_BEACON: Number of beacon according to mode.
- * MODE: Please refer to asic specs.
- * PLUS: Plus or minus delta time value.
- */
-#define BCNCSR 0x00ec
-#define BCNCSR_CHANGE FIELD32(0x00000001)
-#define BCNCSR_DELTATIME FIELD32(0x0000001e)
-#define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
-#define BCNCSR_MODE FIELD32(0x00006000)
-#define BCNCSR_PLUS FIELD32(0x00008000)
-
-/*
- * BBP / RF / IF Control Register.
- */
-
-/*
- * BBPCSR: BBP serial control register.
- * VALUE: Register value to program into BBP.
- * REGNUM: Selected BBP register.
- * BUSY: 1: asic is busy execute BBP programming.
- * WRITE_CONTROL: 1: write BBP, 0: read BBP.
- */
-#define BBPCSR 0x00f0
-#define BBPCSR_VALUE FIELD32(0x000000ff)
-#define BBPCSR_REGNUM FIELD32(0x00007f00)
-#define BBPCSR_BUSY FIELD32(0x00008000)
-#define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
-
-/*
- * RFCSR: RF serial control register.
- * VALUE: Register value + id to program into rf/if.
- * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
- * IF_SELECT: Chip to program: 0: rf, 1: if.
- * PLL_LD: Rf pll_ld status.
- * BUSY: 1: asic is busy execute rf programming.
- */
-#define RFCSR 0x00f4
-#define RFCSR_VALUE FIELD32(0x00ffffff)
-#define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
-#define RFCSR_IF_SELECT FIELD32(0x20000000)
-#define RFCSR_PLL_LD FIELD32(0x40000000)
-#define RFCSR_BUSY FIELD32(0x80000000)
-
-/*
- * LEDCSR: LED control register.
- * ON_PERIOD: On period, default 70ms.
- * OFF_PERIOD: Off period, default 30ms.
- * LINK: 0: linkoff, 1: linkup.
- * ACTIVITY: 0: idle, 1: active.
- */
-#define LEDCSR 0x00f8
-#define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
-#define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
-#define LEDCSR_LINK FIELD32(0x00010000)
-#define LEDCSR_ACTIVITY FIELD32(0x00020000)
-
-/*
- * ASIC pointer information.
- * RXPTR: Current RX ring address.
- * TXPTR: Current Tx ring address.
- * PRIPTR: Current Priority ring address.
- * ATIMPTR: Current ATIM ring address.
- */
-#define RXPTR 0x0100
-#define TXPTR 0x0104
-#define PRIPTR 0x0108
-#define ATIMPTR 0x010c
-
-/*
- * GPIO and others.
- */
-
-/*
- * GPIOCSR: GPIO control register.
- */
-#define GPIOCSR 0x0120
-#define GPIOCSR_BIT0 FIELD32(0x00000001)
-#define GPIOCSR_BIT1 FIELD32(0x00000002)
-#define GPIOCSR_BIT2 FIELD32(0x00000004)
-#define GPIOCSR_BIT3 FIELD32(0x00000008)
-#define GPIOCSR_BIT4 FIELD32(0x00000010)
-#define GPIOCSR_BIT5 FIELD32(0x00000020)
-#define GPIOCSR_BIT6 FIELD32(0x00000040)
-#define GPIOCSR_BIT7 FIELD32(0x00000080)
-
-/*
- * BBPPCSR: BBP Pin control register.
- */
-#define BBPPCSR 0x0124
-
-/*
- * BCNCSR1: Tx BEACON offset time control register.
- * PRELOAD: Beacon timer offset in units of usec.
- */
-#define BCNCSR1 0x0130
-#define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
-
-/*
- * MACCSR2: TX_PE to RX_PE turn-around time control register
- * DELAY: RX_PE low width, in units of pci clock cycle.
- */
-#define MACCSR2 0x0134
-#define MACCSR2_DELAY FIELD32(0x000000ff)
-
-/*
- * ARCSR2: 1 Mbps ACK/CTS PLCP.
- */
-#define ARCSR2 0x013c
-#define ARCSR2_SIGNAL FIELD32(0x000000ff)
-#define ARCSR2_SERVICE FIELD32(0x0000ff00)
-#define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
-#define ARCSR2_LENGTH FIELD32(0xffff0000)
-
-/*
- * ARCSR3: 2 Mbps ACK/CTS PLCP.
- */
-#define ARCSR3 0x0140
-#define ARCSR3_SIGNAL FIELD32(0x000000ff)
-#define ARCSR3_SERVICE FIELD32(0x0000ff00)
-#define ARCSR3_LENGTH FIELD32(0xffff0000)
-
-/*
- * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
- */
-#define ARCSR4 0x0144
-#define ARCSR4_SIGNAL FIELD32(0x000000ff)
-#define ARCSR4_SERVICE FIELD32(0x0000ff00)
-#define ARCSR4_LENGTH FIELD32(0xffff0000)
-
-/*
- * ARCSR5: 11 Mbps ACK/CTS PLCP.
- */
-#define ARCSR5 0x0148
-#define ARCSR5_SIGNAL FIELD32(0x000000ff)
-#define ARCSR5_SERVICE FIELD32(0x0000ff00)
-#define ARCSR5_LENGTH FIELD32(0xffff0000)
-
-/*
- * BBP registers.
- * The wordsize of the BBP is 8 bits.
- */
-
-/*
- * R1: TX antenna control
- */
-#define BBP_R1_TX_ANTENNA FIELD8(0x03)
-
-/*
- * R4: RX antenna control
- */
-#define BBP_R4_RX_ANTENNA FIELD8(0x06)
-
-/*
- * RF registers
- */
-
-/*
- * RF 1
- */
-#define RF1_TUNER FIELD32(0x00020000)
-
-/*
- * RF 3
- */
-#define RF3_TUNER FIELD32(0x00000100)
-#define RF3_TXPOWER FIELD32(0x00003e00)
-
-/*
- * EEPROM content.
- * The wordsize of the EEPROM is 16 bits.
- */
-
-/*
- * HW MAC address.
- */
-#define EEPROM_MAC_ADDR_0 0x0002
-#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR1 0x0003
-#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR_2 0x0004
-#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
-
-/*
- * EEPROM antenna.
- * ANTENNA_NUM: Number of antenna's.
- * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * RF_TYPE: Rf_type of this adapter.
- * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
- * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
- * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
- */
-#define EEPROM_ANTENNA 0x0b
-#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
-#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
-#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
-#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040)
-#define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180)
-#define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
-#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
-
-/*
- * EEPROM BBP.
- */
-#define EEPROM_BBP_START 0x0c
-#define EEPROM_BBP_SIZE 7
-#define EEPROM_BBP_VALUE FIELD16(0x00ff)
-#define EEPROM_BBP_REG_ID FIELD16(0xff00)
-
-/*
- * EEPROM TXPOWER
- */
-#define EEPROM_TXPOWER_START 0x13
-#define EEPROM_TXPOWER_SIZE 7
-#define EEPROM_TXPOWER_1 FIELD16(0x00ff)
-#define EEPROM_TXPOWER_2 FIELD16(0xff00)
-
-/*
- * DMA descriptor defines.
- */
-#define TXD_DESC_SIZE ( 8 * sizeof(struct data_desc) )
-#define RXD_DESC_SIZE ( 8 * sizeof(struct data_desc) )
-
-/*
- * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
- */
-
-/*
- * Word0
- */
-#define TXD_W0_OWNER_NIC FIELD32(0x00000001)
-#define TXD_W0_VALID FIELD32(0x00000002)
-#define TXD_W0_RESULT FIELD32(0x0000001c)
-#define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
-#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
-#define TXD_W0_ACK FIELD32(0x00000200)
-#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
-#define TXD_W0_RTS FIELD32(0x00000800)
-#define TXD_W0_IFS FIELD32(0x00006000)
-#define TXD_W0_RETRY_MODE FIELD32(0x00008000)
-#define TXD_W0_AGC FIELD32(0x00ff0000)
-#define TXD_W0_R2 FIELD32(0xff000000)
-
-/*
- * Word1
- */
-#define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
-
-/*
- * Word2
- */
-#define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
-#define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
-
-/*
- * Word3 & 4: PLCP information
- */
-#define TXD_W3_PLCP_SIGNAL FIELD32(0x0000ffff)
-#define TXD_W3_PLCP_SERVICE FIELD32(0xffff0000)
-#define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x0000ffff)
-#define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0xffff0000)
-
-/*
- * Word5
- */
-#define TXD_W5_BBCR4 FIELD32(0x0000ffff)
-#define TXD_W5_AGC_REG FIELD32(0x007f0000)
-#define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
-#define TXD_W5_XXX_REG FIELD32(0x7f000000)
-#define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
-
-/*
- * Word6
- */
-#define TXD_W6_SK_BUFF FIELD32(0xffffffff)
-
-/*
- * Word7
- */
-#define TXD_W7_RESERVED FIELD32(0xffffffff)
-
-/*
- * RX descriptor format for RX Ring.
- */
-
-/*
- * Word0
- */
-#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
-#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
-#define RXD_W0_MULTICAST FIELD32(0x00000004)
-#define RXD_W0_BROADCAST FIELD32(0x00000008)
-#define RXD_W0_MY_BSS FIELD32(0x00000010)
-#define RXD_W0_CRC_ERROR FIELD32(0x00000020)
-#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
-#define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
-
-/*
- * Word1
- */
-#define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
-
-/*
- * Word2
- */
-#define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
-#define RXD_W2_SIGNAL FIELD32(0x00ff0000)
-#define RXD_W2_RSSI FIELD32(0xff000000)
-
-/*
- * Word3
- */
-#define RXD_W3_BBR2 FIELD32(0x000000ff)
-#define RXD_W3_BBR3 FIELD32(0x0000ff00)
-#define RXD_W3_BBR4 FIELD32(0x00ff0000)
-#define RXD_W3_BBR5 FIELD32(0xff000000)
-
-/*
- * Word4
- */
-#define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
-
-/*
- * Word5 & 6 & 7: Reserved
- */
-#define RXD_W5_RESERVED FIELD32(0xffffffff)
-#define RXD_W6_RESERVED FIELD32(0xffffffff)
-#define RXD_W7_RESERVED FIELD32(0xffffffff)
-
-/*
- * Macro's for converting txpower from EEPROM to dscape value
- * and from dscape value to register value.
- * NOTE: Logics in rt2400pci for txpower are reversed
- * compared to the other rt2x00 drivers. A higher txpower
- * value means that the txpower must be lowered. This is
- * important when converting the value coming from the
- * dscape stack to the rt2400 acceptable value.
- */
-#define MIN_TXPOWER 31
-#define MAX_TXPOWER 62
-#define DEFAULT_TXPOWER 39
-
-#define TXPOWER_FROM_DEV(__txpower) \
-({ \
- ((__txpower) > MAX_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \
- ((__txpower) < MIN_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \
- (((__txpower) - MAX_TXPOWER) + MIN_TXPOWER); \
-})
-
-#define TXPOWER_TO_DEV(__txpower) \
-({ \
- (__txpower) += MIN_TXPOWER; \
- ((__txpower) <= MIN_TXPOWER) ? MAX_TXPOWER : \
- (((__txpower) >= MAX_TXPOWER) ? MIN_TXPOWER : \
- (MAX_TXPOWER - ((__txpower) - MIN_TXPOWER))); \
-})
-
-#endif /* RT2400PCI_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2500pci
- Abstract: rt2500pci device specific routines.
- Supported chipsets: RT2560.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2500pci"
-
-#include <linux/delay.h>
-#include <linux/etherdevice.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/eeprom_93cx6.h>
-
-#include "rt2x00.h"
-#include "rt2x00pci.h"
-#include "rt2500pci.h"
-
-/*
- * Register access.
- * All access to the CSR registers will go through the methods
- * rt2x00pci_register_read and rt2x00pci_register_write.
- * BBP and RF register require indirect register access,
- * and use the CSR registers BBPCSR and RFCSR to achieve this.
- * These indirect registers work with busy bits,
- * and we will try maximal REGISTER_BUSY_COUNT times to access
- * the register while taking a REGISTER_BUSY_DELAY us delay
- * between each attampt. When the busy bit is still set at that time,
- * the access attempt is considered to have failed,
- * and we will print an error.
- */
-static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- unsigned int i;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
- if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
- break;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- return reg;
-}
-
-static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u8 value)
-{
- u32 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt2500pci_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
- ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
- return;
- }
-
- /*
- * Write the data into the BBP.
- */
- reg = 0;
- rt2x00_set_field32(®, BBPCSR_VALUE, value);
- rt2x00_set_field32(®, BBPCSR_REGNUM, word);
- rt2x00_set_field32(®, BBPCSR_BUSY, 1);
- rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
-
- rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
-}
-
-static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u8 *value)
-{
- u32 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt2500pci_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
- ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
- return;
- }
-
- /*
- * Write the request into the BBP.
- */
- reg = 0;
- rt2x00_set_field32(®, BBPCSR_REGNUM, word);
- rt2x00_set_field32(®, BBPCSR_BUSY, 1);
- rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
-
- rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt2500pci_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
- ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
- *value = 0xff;
- return;
- }
-
- *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
-}
-
-static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u32 value)
-{
- u32 reg;
- unsigned int i;
-
- if (!word)
- return;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
- if (!rt2x00_get_field32(reg, RFCSR_BUSY))
- goto rf_write;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
- return;
-
-rf_write:
- reg = 0;
- rt2x00_set_field32(®, RFCSR_VALUE, value);
- rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
- rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
- rt2x00_set_field32(®, RFCSR_BUSY, 1);
-
- rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
- rt2x00_rf_write(rt2x00dev, word, value);
-}
-
-static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
-{
- struct rt2x00_dev *rt2x00dev = eeprom->data;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR21, ®);
-
- eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
- eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
- eeprom->reg_data_clock =
- !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
- eeprom->reg_chip_select =
- !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
-}
-
-static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
-{
- struct rt2x00_dev *rt2x00dev = eeprom->data;
- u32 reg = 0;
-
- rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
- rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
- rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
- !!eeprom->reg_data_clock);
- rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
- !!eeprom->reg_chip_select);
-
- rt2x00pci_register_write(rt2x00dev, CSR21, reg);
-}
-
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
-
-static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 *data)
-{
- rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 data)
-{
- rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static const struct rt2x00debug rt2500pci_rt2x00debug = {
- .owner = THIS_MODULE,
- .csr = {
- .read = rt2500pci_read_csr,
- .write = rt2500pci_write_csr,
- .word_size = sizeof(u32),
- .word_count = CSR_REG_SIZE / sizeof(u32),
- },
- .eeprom = {
- .read = rt2x00_eeprom_read,
- .write = rt2x00_eeprom_write,
- .word_size = sizeof(u16),
- .word_count = EEPROM_SIZE / sizeof(u16),
- },
- .bbp = {
- .read = rt2500pci_bbp_read,
- .write = rt2500pci_bbp_write,
- .word_size = sizeof(u8),
- .word_count = BBP_SIZE / sizeof(u8),
- },
- .rf = {
- .read = rt2x00_rf_read,
- .write = rt2500pci_rf_write,
- .word_size = sizeof(u32),
- .word_count = RF_SIZE / sizeof(u32),
- },
-};
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
-#ifdef CONFIG_RT2500PCI_RFKILL
-static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
- return rt2x00_get_field32(reg, GPIOCSR_BIT0);
-}
-#else
-#define rt2500pci_rfkill_poll NULL
-#endif /* CONFIG_RT2500PCI_RFKILL */
-
-/*
- * Configuration handlers.
- */
-static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
- __le32 *mac)
-{
- rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
- (2 * sizeof(__le32)));
-}
-
-static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
- __le32 *bssid)
-{
- rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
- (2 * sizeof(__le32)));
-}
-
-static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
- const int tsf_sync)
-{
- u32 reg;
-
- rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-
- /*
- * Enable beacon config
- */
- rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
- rt2x00_set_field32(®, BCNCSR1_PRELOAD,
- PREAMBLE + get_duration(IEEE80211_HEADER, 20));
- rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN,
- rt2x00lib_get_ring(rt2x00dev,
- IEEE80211_TX_QUEUE_BEACON)
- ->tx_params.cw_min);
- rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
-
- /*
- * Enable synchronisation.
- */
- rt2x00pci_register_read(rt2x00dev, CSR14, ®);
- rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
- rt2x00_set_field32(®, CSR14_TBCN, 1);
- rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
- rt2x00_set_field32(®, CSR14_TSF_SYNC, tsf_sync);
- rt2x00pci_register_write(rt2x00dev, CSR14, reg);
-}
-
-static void rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
- const int short_preamble,
- const int ack_timeout,
- const int ack_consume_time)
-{
- int preamble_mask;
- u32 reg;
-
- /*
- * When short preamble is enabled, we should set bit 0x08
- */
- preamble_mask = short_preamble << 3;
-
- rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
- rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, ack_timeout);
- rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
- rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
- rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble_mask);
- rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
- rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
- rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
- rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
- rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
- rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
- rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
- rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
- rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
- rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
- rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
-}
-
-static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
- const int basic_rate_mask)
-{
- rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
-}
-
-static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
- struct rf_channel *rf, const int txpower)
-{
- u8 r70;
-
- /*
- * Set TXpower.
- */
- rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
-
- /*
- * Switch on tuning bits.
- * For RT2523 devices we do not need to update the R1 register.
- */
- if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
- rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
- rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
-
- /*
- * For RT2525 we should first set the channel to half band higher.
- */
- if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
- static const u32 vals[] = {
- 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
- 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
- 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
- 0x00080d2e, 0x00080d3a
- };
-
- rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
- rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
- rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
- if (rf->rf4)
- rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
- }
-
- rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
- rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
- rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
- if (rf->rf4)
- rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
-
- /*
- * Channel 14 requires the Japan filter bit to be set.
- */
- r70 = 0x46;
- rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
- rt2500pci_bbp_write(rt2x00dev, 70, r70);
-
- msleep(1);
-
- /*
- * Switch off tuning bits.
- * For RT2523 devices we do not need to update the R1 register.
- */
- if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
- rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
- rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
- }
-
- rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
- rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
-
- /*
- * Clear false CRC during channel switch.
- */
- rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
-}
-
-static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
- const int txpower)
-{
- u32 rf3;
-
- rt2x00_rf_read(rt2x00dev, 3, &rf3);
- rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
- rt2500pci_rf_write(rt2x00dev, 3, rf3);
-}
-
-static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx, const int antenna_rx)
-{
- u32 reg;
- u8 r14;
- u8 r2;
-
- rt2x00pci_register_read(rt2x00dev, BBPCSR1, ®);
- rt2500pci_bbp_read(rt2x00dev, 14, &r14);
- rt2500pci_bbp_read(rt2x00dev, 2, &r2);
-
- /*
- * Configure the TX antenna.
- */
- switch (antenna_tx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
- rt2x00_set_field32(®, BBPCSR1_CCK, 2);
- rt2x00_set_field32(®, BBPCSR1_OFDM, 2);
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
- rt2x00_set_field32(®, BBPCSR1_CCK, 0);
- rt2x00_set_field32(®, BBPCSR1_OFDM, 0);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
- rt2x00_set_field32(®, BBPCSR1_CCK, 2);
- rt2x00_set_field32(®, BBPCSR1_OFDM, 2);
- break;
- }
-
- /*
- * Configure the RX antenna.
- */
- switch (antenna_rx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
- break;
- }
-
- /*
- * RT2525E and RT5222 need to flip TX I/Q
- */
- if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
- rt2x00_rf(&rt2x00dev->chip, RF5222)) {
- rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
- rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1);
- rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1);
-
- /*
- * RT2525E does not need RX I/Q Flip.
- */
- if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
- rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
- } else {
- rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0);
- rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0);
- }
-
- rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
- rt2500pci_bbp_write(rt2x00dev, 14, r14);
- rt2500pci_bbp_write(rt2x00dev, 2, r2);
-}
-
-static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
- struct rt2x00lib_conf *libconf)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR11, ®);
- rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
- rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR18, ®);
- rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
- rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
- rt2x00pci_register_write(rt2x00dev, CSR18, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR19, ®);
- rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
- rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
- rt2x00pci_register_write(rt2x00dev, CSR19, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
- rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
- rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
- rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR12, ®);
- rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
- libconf->conf->beacon_int * 16);
- rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
- libconf->conf->beacon_int * 16);
- rt2x00pci_register_write(rt2x00dev, CSR12, reg);
-}
-
-static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
- const unsigned int flags,
- struct rt2x00lib_conf *libconf)
-{
- if (flags & CONFIG_UPDATE_PHYMODE)
- rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
- if (flags & CONFIG_UPDATE_CHANNEL)
- rt2500pci_config_channel(rt2x00dev, &libconf->rf,
- libconf->conf->power_level);
- if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
- rt2500pci_config_txpower(rt2x00dev,
- libconf->conf->power_level);
- if (flags & CONFIG_UPDATE_ANTENNA)
- rt2500pci_config_antenna(rt2x00dev,
- libconf->conf->antenna_sel_tx,
- libconf->conf->antenna_sel_rx);
- if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
- rt2500pci_config_duration(rt2x00dev, libconf);
-}
-
-/*
- * LED functions.
- */
-static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
-
- rt2x00_set_field32(®, LEDCSR_ON_PERIOD, 70);
- rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, 30);
-
- if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
- rt2x00_set_field32(®, LEDCSR_LINK, 1);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0);
- } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
- rt2x00_set_field32(®, LEDCSR_LINK, 0);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 1);
- } else {
- rt2x00_set_field32(®, LEDCSR_LINK, 1);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 1);
- }
-
- rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
-}
-
-static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
- rt2x00_set_field32(®, LEDCSR_LINK, 0);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0);
- rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
-}
-
-/*
- * Link tuning
- */
-static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Update FCS error count from register.
- */
- rt2x00pci_register_read(rt2x00dev, CNT0, ®);
- rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
-
- /*
- * Update False CCA count from register.
- */
- rt2x00pci_register_read(rt2x00dev, CNT3, ®);
- rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
-}
-
-static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
-{
- rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
- rt2x00dev->link.vgc_level = 0x48;
-}
-
-static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
- int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
- u8 r17;
-
- /*
- * To prevent collisions with MAC ASIC on chipsets
- * up to version C the link tuning should halt after 20
- * seconds.
- */
- if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
- rt2x00dev->link.count > 20)
- return;
-
- rt2500pci_bbp_read(rt2x00dev, 17, &r17);
-
- /*
- * Chipset versions C and lower should directly continue
- * to the dynamic CCA tuning.
- */
- if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
- goto dynamic_cca_tune;
-
- /*
- * A too low RSSI will cause too much false CCA which will
- * then corrupt the R17 tuning. To remidy this the tuning should
- * be stopped (While making sure the R17 value will not exceed limits)
- */
- if (rssi < -80 && rt2x00dev->link.count > 20) {
- if (r17 >= 0x41) {
- r17 = rt2x00dev->link.vgc_level;
- rt2500pci_bbp_write(rt2x00dev, 17, r17);
- }
- return;
- }
-
- /*
- * Special big-R17 for short distance
- */
- if (rssi >= -58) {
- if (r17 != 0x50)
- rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
- return;
- }
-
- /*
- * Special mid-R17 for middle distance
- */
- if (rssi >= -74) {
- if (r17 != 0x41)
- rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
- return;
- }
-
- /*
- * Leave short or middle distance condition, restore r17
- * to the dynamic tuning range.
- */
- if (r17 >= 0x41) {
- rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
- return;
- }
-
-dynamic_cca_tune:
-
- /*
- * R17 is inside the dynamic tuning range,
- * start tuning the link based on the false cca counter.
- */
- if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
- rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
- rt2x00dev->link.vgc_level = r17;
- } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
- rt2500pci_bbp_write(rt2x00dev, 17, --r17);
- rt2x00dev->link.vgc_level = r17;
- }
-}
-
-/*
- * Initialization functions.
- */
-static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring = rt2x00dev->rx;
- struct data_desc *rxd;
- unsigned int i;
- u32 word;
-
- memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
- for (i = 0; i < ring->stats.limit; i++) {
- rxd = ring->entry[i].priv;
-
- rt2x00_desc_read(rxd, 1, &word);
- rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
- ring->entry[i].data_dma);
- rt2x00_desc_write(rxd, 1, word);
-
- rt2x00_desc_read(rxd, 0, &word);
- rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
- rt2x00_desc_write(rxd, 0, word);
- }
-
- rt2x00_ring_index_clear(rt2x00dev->rx);
-}
-
-static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
-{
- struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
- struct data_desc *txd;
- unsigned int i;
- u32 word;
-
- memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
- for (i = 0; i < ring->stats.limit; i++) {
- txd = ring->entry[i].priv;
-
- rt2x00_desc_read(txd, 1, &word);
- rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
- ring->entry[i].data_dma);
- rt2x00_desc_write(txd, 1, word);
-
- rt2x00_desc_read(txd, 0, &word);
- rt2x00_set_field32(&word, TXD_W0_VALID, 0);
- rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
- rt2x00_desc_write(txd, 0, word);
- }
-
- rt2x00_ring_index_clear(ring);
-}
-
-static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Initialize rings.
- */
- rt2500pci_init_rxring(rt2x00dev);
- rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
- rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
- rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
- rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
-
- /*
- * Initialize registers.
- */
- rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
- rt2x00_set_field32(®, TXCSR2_TXD_SIZE,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
- rt2x00_set_field32(®, TXCSR2_NUM_TXD,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
- rt2x00_set_field32(®, TXCSR2_NUM_ATIM,
- rt2x00dev->bcn[1].stats.limit);
- rt2x00_set_field32(®, TXCSR2_NUM_PRIO,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
- rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
- rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
- rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
- rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
- rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
- rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
- rt2x00dev->bcn[1].data_dma);
- rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
- rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
- rt2x00dev->bcn[0].data_dma);
- rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
-
- rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
- rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
- rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
- rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
- rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
- rt2x00dev->rx->data_dma);
- rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
-
- return 0;
-}
-
-static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
- rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
- rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
- rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
-
- rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
- rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
- rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
- rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
- rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR9, ®);
- rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
- rt2x00dev->rx->data_size / 128);
- rt2x00pci_register_write(rt2x00dev, CSR9, reg);
-
- /*
- * Always use CWmin and CWmax set in descriptor.
- */
- rt2x00pci_register_read(rt2x00dev, CSR11, ®);
- rt2x00_set_field32(®, CSR11_CW_SELECT, 0);
- rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
- rt2x00pci_register_write(rt2x00dev, CNT3, 0);
-
- rt2x00pci_register_read(rt2x00dev, TXCSR8, ®);
- rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10);
- rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1);
- rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11);
- rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1);
- rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13);
- rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1);
- rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12);
- rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1);
- rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®);
- rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112);
- rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56);
- rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20);
- rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10);
- rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®);
- rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45);
- rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37);
- rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33);
- rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29);
- rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®);
- rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29);
- rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25);
- rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25);
- rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25);
- rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
-
- rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
- rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */
- rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
- rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */
- rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
- rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
- rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
- rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */
- rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1);
- rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
-
- rt2x00pci_register_read(rt2x00dev, PCICSR, ®);
- rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0);
- rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0);
- rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3);
- rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1);
- rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1);
- rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1);
- rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1);
- rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
-
- rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
-
- rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
- rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
-
- if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
- return -EBUSY;
-
- rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
- rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
-
- rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
- rt2x00_set_field32(®, MACCSR2_DELAY, 64);
- rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
-
- rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26);
- rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1);
- rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
-
- rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
-
- rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
-
- rt2x00pci_register_read(rt2x00dev, CSR1, ®);
- rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
- rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
- rt2x00_set_field32(®, CSR1_HOST_READY, 0);
- rt2x00pci_register_write(rt2x00dev, CSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, CSR1, ®);
- rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
- rt2x00_set_field32(®, CSR1_HOST_READY, 1);
- rt2x00pci_register_write(rt2x00dev, CSR1, reg);
-
- /*
- * We must clear the FCS and FIFO error count.
- * These registers are cleared on read,
- * so we may pass a useless variable to store the value.
- */
- rt2x00pci_register_read(rt2x00dev, CNT0, ®);
- rt2x00pci_register_read(rt2x00dev, CNT4, ®);
-
- return 0;
-}
-
-static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
-{
- unsigned int i;
- u16 eeprom;
- u8 reg_id;
- u8 value;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2500pci_bbp_read(rt2x00dev, 0, &value);
- if ((value != 0xff) && (value != 0x00))
- goto continue_csr_init;
- NOTICE(rt2x00dev, "Waiting for BBP register.\n");
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
- return -EACCES;
-
-continue_csr_init:
- rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
- rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
- rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
- rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
- rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
- rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
- rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
- rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
- rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
- rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
- rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
- rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
- rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
- rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
- rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
- rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
- rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
- rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
- rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
- rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
- rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
- rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
- rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
- rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
- rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
- rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
- rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
- rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
- rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
- rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
-
- DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
- for (i = 0; i < EEPROM_BBP_SIZE; i++) {
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
-
- if (eeprom != 0xffff && eeprom != 0x0000) {
- reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
- value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
- DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
- reg_id, value);
- rt2500pci_bbp_write(rt2x00dev, reg_id, value);
- }
- }
- DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
-
- return 0;
-}
-
-/*
- * Device state switch handlers.
- */
-static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
- rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
- state == STATE_RADIO_RX_OFF);
- rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
-static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- int mask = (state == STATE_RADIO_IRQ_OFF);
- u32 reg;
-
- /*
- * When interrupts are being enabled, the interrupt registers
- * should clear the register to assure a clean state.
- */
- if (state == STATE_RADIO_IRQ_ON) {
- rt2x00pci_register_read(rt2x00dev, CSR7, ®);
- rt2x00pci_register_write(rt2x00dev, CSR7, reg);
- }
-
- /*
- * Only toggle the interrupts bits we are going to use.
- * Non-checked interrupt bits are disabled by default.
- */
- rt2x00pci_register_read(rt2x00dev, CSR8, ®);
- rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
- rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
- rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
- rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
- rt2x00_set_field32(®, CSR8_RXDONE, mask);
- rt2x00pci_register_write(rt2x00dev, CSR8, reg);
-}
-
-static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
- /*
- * Initialize all registers.
- */
- if (rt2500pci_init_rings(rt2x00dev) ||
- rt2500pci_init_registers(rt2x00dev) ||
- rt2500pci_init_bbp(rt2x00dev)) {
- ERROR(rt2x00dev, "Register initialization failed.\n");
- return -EIO;
- }
-
- /*
- * Enable interrupts.
- */
- rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
-
- /*
- * Enable LED
- */
- rt2500pci_enable_led(rt2x00dev);
-
- return 0;
-}
-
-static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Disable LED
- */
- rt2500pci_disable_led(rt2x00dev);
-
- rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
-
- /*
- * Disable synchronisation.
- */
- rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-
- /*
- * Cancel RX and TX.
- */
- rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
- rt2x00_set_field32(®, TXCSR0_ABORT, 1);
- rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-
- /*
- * Disable interrupts.
- */
- rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
-}
-
-static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- u32 reg;
- unsigned int i;
- char put_to_sleep;
- char bbp_state;
- char rf_state;
-
- put_to_sleep = (state != STATE_AWAKE);
-
- rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
- rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
- rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
- rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
- rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
- rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
-
- /*
- * Device is not guaranteed to be in the requested state yet.
- * We must wait until the register indicates that the
- * device has entered the correct state.
- */
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
- bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
- rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
- if (bbp_state == state && rf_state == state)
- return 0;
- msleep(10);
- }
-
- NOTICE(rt2x00dev, "Device failed to enter state %d, "
- "current device state: bbp %d and rf %d.\n",
- state, bbp_state, rf_state);
-
- return -EBUSY;
-}
-
-static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- int retval = 0;
-
- switch (state) {
- case STATE_RADIO_ON:
- retval = rt2500pci_enable_radio(rt2x00dev);
- break;
- case STATE_RADIO_OFF:
- rt2500pci_disable_radio(rt2x00dev);
- break;
- case STATE_RADIO_RX_ON:
- case STATE_RADIO_RX_OFF:
- rt2500pci_toggle_rx(rt2x00dev, state);
- break;
- case STATE_DEEP_SLEEP:
- case STATE_SLEEP:
- case STATE_STANDBY:
- case STATE_AWAKE:
- retval = rt2500pci_set_state(rt2x00dev, state);
- break;
- default:
- retval = -ENOTSUPP;
- break;
- }
-
- return retval;
-}
-
-/*
- * TX descriptor initialization
- */
-static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
- struct data_desc *txd,
- struct txdata_entry_desc *desc,
- struct ieee80211_hdr *ieee80211hdr,
- unsigned int length,
- struct ieee80211_tx_control *control)
-{
- u32 word;
-
- /*
- * Start writing the descriptor words.
- */
- rt2x00_desc_read(txd, 2, &word);
- rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
- rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
- rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
- rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
- rt2x00_desc_write(txd, 2, word);
-
- rt2x00_desc_read(txd, 3, &word);
- rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
- rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
- rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
- rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
- rt2x00_desc_write(txd, 3, word);
-
- rt2x00_desc_read(txd, 10, &word);
- rt2x00_set_field32(&word, TXD_W10_RTS,
- test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
- rt2x00_desc_write(txd, 10, word);
-
- rt2x00_desc_read(txd, 0, &word);
- rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
- rt2x00_set_field32(&word, TXD_W0_VALID, 1);
- rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
- test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_ACK,
- !(control->flags & IEEE80211_TXCTL_NO_ACK));
- rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
- test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_OFDM,
- test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
- rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
- rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
- !!(control->flags &
- IEEE80211_TXCTL_LONG_RETRY_LIMIT));
- rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
- rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
- rt2x00_desc_write(txd, 0, word);
-}
-
-/*
- * TX data initialization
- */
-static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
- unsigned int queue)
-{
- u32 reg;
-
- if (queue == IEEE80211_TX_QUEUE_BEACON) {
- rt2x00pci_register_read(rt2x00dev, CSR14, ®);
- if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
- rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
- rt2x00pci_register_write(rt2x00dev, CSR14, reg);
- }
- return;
- }
-
- rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
- if (queue == IEEE80211_TX_QUEUE_DATA0)
- rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
- else if (queue == IEEE80211_TX_QUEUE_DATA1)
- rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
- else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
- rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
- rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-}
-
-/*
- * RX control handlers
- */
-static void rt2500pci_fill_rxdone(struct data_entry *entry,
- struct rxdata_entry_desc *desc)
-{
- struct data_desc *rxd = entry->priv;
- u32 word0;
- u32 word2;
-
- rt2x00_desc_read(rxd, 0, &word0);
- rt2x00_desc_read(rxd, 2, &word2);
-
- desc->flags = 0;
- if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
- desc->flags |= RX_FLAG_FAILED_FCS_CRC;
- if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
- desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
-
- desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
- desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
- entry->ring->rt2x00dev->rssi_offset;
- desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
- desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
-}
-
-/*
- * Interrupt functions.
- */
-static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
-{
- struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
- struct data_entry *entry;
- struct data_desc *txd;
- u32 word;
- int tx_status;
- int retry;
-
- while (!rt2x00_ring_empty(ring)) {
- entry = rt2x00_get_data_entry_done(ring);
- txd = entry->priv;
- rt2x00_desc_read(txd, 0, &word);
-
- if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
- !rt2x00_get_field32(word, TXD_W0_VALID))
- break;
-
- /*
- * Obtain the status about this packet.
- */
- tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
- retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
-
- rt2x00lib_txdone(entry, tx_status, retry);
-
- /*
- * Make this entry available for reuse.
- */
- entry->flags = 0;
- rt2x00_set_field32(&word, TXD_W0_VALID, 0);
- rt2x00_desc_write(txd, 0, word);
- rt2x00_ring_index_done_inc(ring);
- }
-
- /*
- * If the data ring was full before the txdone handler
- * we must make sure the packet queue in the mac80211 stack
- * is reenabled when the txdone handler has finished.
- */
- entry = ring->entry;
- if (!rt2x00_ring_full(ring))
- ieee80211_wake_queue(rt2x00dev->hw,
- entry->tx_status.control.queue);
-}
-
-static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
-{
- struct rt2x00_dev *rt2x00dev = dev_instance;
- u32 reg;
-
- /*
- * Get the interrupt sources & saved to local variable.
- * Write register value back to clear pending interrupts.
- */
- rt2x00pci_register_read(rt2x00dev, CSR7, ®);
- rt2x00pci_register_write(rt2x00dev, CSR7, reg);
-
- if (!reg)
- return IRQ_NONE;
-
- if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
- return IRQ_HANDLED;
-
- /*
- * Handle interrupts, walk through all bits
- * and run the tasks, the bits are checked in order of
- * priority.
- */
-
- /*
- * 1 - Beacon timer expired interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
- rt2x00lib_beacondone(rt2x00dev);
-
- /*
- * 2 - Rx ring done interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_RXDONE))
- rt2x00pci_rxdone(rt2x00dev);
-
- /*
- * 3 - Atim ring transmit done interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
- rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
-
- /*
- * 4 - Priority ring transmit done interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
- rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
-
- /*
- * 5 - Tx ring transmit done interrupt.
- */
- if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
- rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
-
- return IRQ_HANDLED;
-}
-
-/*
- * Device probe functions.
- */
-static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- struct eeprom_93cx6 eeprom;
- u32 reg;
- u16 word;
- u8 *mac;
-
- rt2x00pci_register_read(rt2x00dev, CSR21, ®);
-
- eeprom.data = rt2x00dev;
- eeprom.register_read = rt2500pci_eepromregister_read;
- eeprom.register_write = rt2500pci_eepromregister_write;
- eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
- PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
- eeprom.reg_data_in = 0;
- eeprom.reg_data_out = 0;
- eeprom.reg_data_clock = 0;
- eeprom.reg_chip_select = 0;
-
- eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
- EEPROM_SIZE / sizeof(u16));
-
- /*
- * Start validation of the data that has been read.
- */
- mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
- if (!is_valid_ether_addr(mac)) {
- DECLARE_MAC_BUF(macbuf);
-
- random_ether_addr(mac);
- EEPROM(rt2x00dev, "MAC: %s\n",
- print_mac(macbuf, mac));
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
- EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
- rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
- rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
- EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
- DEFAULT_RSSI_OFFSET);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
- EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
- }
-
- return 0;
-}
-
-static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- u16 value;
- u16 eeprom;
-
- /*
- * Read EEPROM word for configuration.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-
- /*
- * Identify RF chipset.
- */
- value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
- rt2x00pci_register_read(rt2x00dev, CSR0, ®);
- rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
-
- if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
- !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
- ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
- return -ENODEV;
- }
-
- /*
- * Identify default antenna configuration.
- */
- rt2x00dev->hw->conf.antenna_sel_tx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
- rt2x00dev->hw->conf.antenna_sel_rx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
-
- /*
- * Store led mode, for correct led behaviour.
- */
- rt2x00dev->led_mode =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
-
- /*
- * Detect if this device has an hardware controlled radio.
- */
-#ifdef CONFIG_RT2500PCI_RFKILL
- if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
- __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
-#endif /* CONFIG_RT2500PCI_RFKILL */
-
- /*
- * Check if the BBP tuning should be enabled.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
-
- if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
- __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
-
- /*
- * Read the RSSI <-> dBm offset information.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
- rt2x00dev->rssi_offset =
- rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
-
- return 0;
-}
-
-/*
- * RF value list for RF2522
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2522[] = {
- { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
- { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
- { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
- { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
- { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
- { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
- { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
- { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
- { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
- { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
- { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
- { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
- { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
- { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
-};
-
-/*
- * RF value list for RF2523
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2523[] = {
- { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
- { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
- { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
- { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
- { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
- { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
- { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
- { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
- { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
- { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
- { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
- { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
- { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
- { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2524
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2524[] = {
- { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
- { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
- { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
- { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
- { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
- { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
- { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
- { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
- { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
- { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
- { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
- { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
- { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
- { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2525
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2525[] = {
- { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
- { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
- { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
- { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
- { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
- { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
- { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
- { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
- { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
- { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
- { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
- { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
- { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
- { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2525e
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2525e[] = {
- { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
- { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
- { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
- { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
- { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
- { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
- { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
- { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
- { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
- { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
- { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
- { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
- { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
- { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
-};
-
-/*
- * RF value list for RF5222
- * Supports: 2.4 GHz & 5.2 GHz
- */
-static const struct rf_channel rf_vals_5222[] = {
- { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
- { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
- { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
- { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
- { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
- { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
- { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
- { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
- { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
- { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
- { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
- { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
- { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
- { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
-
- /* 802.11 UNI / HyperLan 2 */
- { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
- { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
- { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
- { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
- { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
- { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
- { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
- { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
-
- /* 802.11 HyperLan 2 */
- { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
- { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
- { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
- { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
- { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
- { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
- { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
- { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
- { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
- { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
-
- /* 802.11 UNII */
- { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
- { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
- { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
- { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
- { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
-};
-
-static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
-{
- struct hw_mode_spec *spec = &rt2x00dev->spec;
- u8 *txpower;
- unsigned int i;
-
- /*
- * Initialize all hw fields.
- */
- rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
- rt2x00dev->hw->extra_tx_headroom = 0;
- rt2x00dev->hw->max_signal = MAX_SIGNAL;
- rt2x00dev->hw->max_rssi = MAX_RX_SSI;
- rt2x00dev->hw->queues = 2;
-
- SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
- SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
- rt2x00_eeprom_addr(rt2x00dev,
- EEPROM_MAC_ADDR_0));
-
- /*
- * Convert tx_power array in eeprom.
- */
- txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
- for (i = 0; i < 14; i++)
- txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
- /*
- * Initialize hw_mode information.
- */
- spec->num_modes = 2;
- spec->num_rates = 12;
- spec->tx_power_a = NULL;
- spec->tx_power_bg = txpower;
- spec->tx_power_default = DEFAULT_TXPOWER;
-
- if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
- spec->channels = rf_vals_bg_2522;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
- spec->channels = rf_vals_bg_2523;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
- spec->channels = rf_vals_bg_2524;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
- spec->channels = rf_vals_bg_2525;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
- spec->channels = rf_vals_bg_2525e;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_5222);
- spec->channels = rf_vals_5222;
- spec->num_modes = 3;
- }
-}
-
-static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
-{
- int retval;
-
- /*
- * Allocate eeprom data.
- */
- retval = rt2500pci_validate_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- retval = rt2500pci_init_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- /*
- * Initialize hw specifications.
- */
- rt2500pci_probe_hw_mode(rt2x00dev);
-
- /*
- * This device requires the beacon ring
- */
- __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
-
- /*
- * Set the rssi offset.
- */
- rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
-
- return 0;
-}
-
-/*
- * IEEE80211 stack callback functions.
- */
-static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed_flags,
- unsigned int *total_flags,
- int mc_count,
- struct dev_addr_list *mc_list)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct interface *intf = &rt2x00dev->interface;
- u32 reg;
-
- /*
- * Mask off any flags we are going to ignore from
- * the total_flags field.
- */
- *total_flags &=
- FIF_ALLMULTI |
- FIF_FCSFAIL |
- FIF_PLCPFAIL |
- FIF_CONTROL |
- FIF_OTHER_BSS |
- FIF_PROMISC_IN_BSS;
-
- /*
- * Apply some rules to the filters:
- * - Some filters imply different filters to be set.
- * - Some things we can't filter out at all.
- * - Some filters are set based on interface type.
- */
- if (mc_count)
- *total_flags |= FIF_ALLMULTI;
- if (*total_flags & FIF_OTHER_BSS ||
- *total_flags & FIF_PROMISC_IN_BSS)
- *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
- if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
- *total_flags |= FIF_PROMISC_IN_BSS;
-
- /*
- * Check if there is any work left for us.
- */
- if (intf->filter == *total_flags)
- return;
- intf->filter = *total_flags;
-
- /*
- * Start configuration steps.
- * Note that the version error will always be dropped
- * and broadcast frames will always be accepted since
- * there is no filter for it at this time.
- */
- rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
- rt2x00_set_field32(®, RXCSR0_DROP_CRC,
- !(*total_flags & FIF_FCSFAIL));
- rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
- !(*total_flags & FIF_PLCPFAIL));
- rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
- !(*total_flags & FIF_CONTROL));
- rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field32(®, RXCSR0_DROP_TODS,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
- rt2x00_set_field32(®, RXCSR0_DROP_MCAST,
- !(*total_flags & FIF_ALLMULTI));
- rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0);
- rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
-static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
- u32 short_retry, u32 long_retry)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR11, ®);
- rt2x00_set_field32(®, CSR11_LONG_RETRY, long_retry);
- rt2x00_set_field32(®, CSR11_SHORT_RETRY, short_retry);
- rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
- return 0;
-}
-
-static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u64 tsf;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR17, ®);
- tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
- rt2x00pci_register_read(rt2x00dev, CSR16, ®);
- tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
-
- return tsf;
-}
-
-static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- rt2x00pci_register_write(rt2x00dev, CSR16, 0);
- rt2x00pci_register_write(rt2x00dev, CSR17, 0);
-}
-
-static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, CSR15, ®);
- return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
-}
-
-static const struct ieee80211_ops rt2500pci_mac80211_ops = {
- .tx = rt2x00mac_tx,
- .start = rt2x00mac_start,
- .stop = rt2x00mac_stop,
- .add_interface = rt2x00mac_add_interface,
- .remove_interface = rt2x00mac_remove_interface,
- .config = rt2x00mac_config,
- .config_interface = rt2x00mac_config_interface,
- .configure_filter = rt2500pci_configure_filter,
- .get_stats = rt2x00mac_get_stats,
- .set_retry_limit = rt2500pci_set_retry_limit,
- .erp_ie_changed = rt2x00mac_erp_ie_changed,
- .conf_tx = rt2x00mac_conf_tx,
- .get_tx_stats = rt2x00mac_get_tx_stats,
- .get_tsf = rt2500pci_get_tsf,
- .reset_tsf = rt2500pci_reset_tsf,
- .beacon_update = rt2x00pci_beacon_update,
- .tx_last_beacon = rt2500pci_tx_last_beacon,
-};
-
-static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
- .irq_handler = rt2500pci_interrupt,
- .probe_hw = rt2500pci_probe_hw,
- .initialize = rt2x00pci_initialize,
- .uninitialize = rt2x00pci_uninitialize,
- .set_device_state = rt2500pci_set_device_state,
- .rfkill_poll = rt2500pci_rfkill_poll,
- .link_stats = rt2500pci_link_stats,
- .reset_tuner = rt2500pci_reset_tuner,
- .link_tuner = rt2500pci_link_tuner,
- .write_tx_desc = rt2500pci_write_tx_desc,
- .write_tx_data = rt2x00pci_write_tx_data,
- .kick_tx_queue = rt2500pci_kick_tx_queue,
- .fill_rxdone = rt2500pci_fill_rxdone,
- .config_mac_addr = rt2500pci_config_mac_addr,
- .config_bssid = rt2500pci_config_bssid,
- .config_type = rt2500pci_config_type,
- .config_preamble = rt2500pci_config_preamble,
- .config = rt2500pci_config,
-};
-
-static const struct rt2x00_ops rt2500pci_ops = {
- .name = DRV_NAME,
- .rxd_size = RXD_DESC_SIZE,
- .txd_size = TXD_DESC_SIZE,
- .eeprom_size = EEPROM_SIZE,
- .rf_size = RF_SIZE,
- .lib = &rt2500pci_rt2x00_ops,
- .hw = &rt2500pci_mac80211_ops,
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
- .debugfs = &rt2500pci_rt2x00debug,
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-};
-
-/*
- * RT2500pci module information.
- */
-static struct pci_device_id rt2500pci_device_table[] = {
- { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
- { 0, }
-};
-
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
-MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
-MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
-MODULE_LICENSE("GPL");
-
-static struct pci_driver rt2500pci_driver = {
- .name = DRV_NAME,
- .id_table = rt2500pci_device_table,
- .probe = rt2x00pci_probe,
- .remove = __devexit_p(rt2x00pci_remove),
- .suspend = rt2x00pci_suspend,
- .resume = rt2x00pci_resume,
-};
-
-static int __init rt2500pci_init(void)
-{
- return pci_register_driver(&rt2500pci_driver);
-}
-
-static void __exit rt2500pci_exit(void)
-{
- pci_unregister_driver(&rt2500pci_driver);
-}
-
-module_init(rt2500pci_init);
-module_exit(rt2500pci_exit);
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2500pci
- Abstract: Data structures and registers for the rt2500pci module.
- Supported chipsets: RT2560.
- */
-
-#ifndef RT2500PCI_H
-#define RT2500PCI_H
-
-/*
- * RF chip defines.
- */
-#define RF2522 0x0000
-#define RF2523 0x0001
-#define RF2524 0x0002
-#define RF2525 0x0003
-#define RF2525E 0x0004
-#define RF5222 0x0010
-
-/*
- * RT2560 version
- */
-#define RT2560_VERSION_B 2
-#define RT2560_VERSION_C 3
-#define RT2560_VERSION_D 4
-
-/*
- * Signal information.
- * Defaul offset is required for RSSI <-> dBm conversion.
- */
-#define MAX_SIGNAL 100
-#define MAX_RX_SSI -1
-#define DEFAULT_RSSI_OFFSET 121
-
-/*
- * Register layout information.
- */
-#define CSR_REG_BASE 0x0000
-#define CSR_REG_SIZE 0x0174
-#define EEPROM_BASE 0x0000
-#define EEPROM_SIZE 0x0200
-#define BBP_SIZE 0x0040
-#define RF_SIZE 0x0014
-
-/*
- * Control/Status Registers(CSR).
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * CSR0: ASIC revision number.
- */
-#define CSR0 0x0000
-
-/*
- * CSR1: System control register.
- * SOFT_RESET: Software reset, 1: reset, 0: normal.
- * BBP_RESET: Hardware reset, 1: reset, 0, release.
- * HOST_READY: Host ready after initialization.
- */
-#define CSR1 0x0004
-#define CSR1_SOFT_RESET FIELD32(0x00000001)
-#define CSR1_BBP_RESET FIELD32(0x00000002)
-#define CSR1_HOST_READY FIELD32(0x00000004)
-
-/*
- * CSR2: System admin status register (invalid).
- */
-#define CSR2 0x0008
-
-/*
- * CSR3: STA MAC address register 0.
- */
-#define CSR3 0x000c
-#define CSR3_BYTE0 FIELD32(0x000000ff)
-#define CSR3_BYTE1 FIELD32(0x0000ff00)
-#define CSR3_BYTE2 FIELD32(0x00ff0000)
-#define CSR3_BYTE3 FIELD32(0xff000000)
-
-/*
- * CSR4: STA MAC address register 1.
- */
-#define CSR4 0x0010
-#define CSR4_BYTE4 FIELD32(0x000000ff)
-#define CSR4_BYTE5 FIELD32(0x0000ff00)
-
-/*
- * CSR5: BSSID register 0.
- */
-#define CSR5 0x0014
-#define CSR5_BYTE0 FIELD32(0x000000ff)
-#define CSR5_BYTE1 FIELD32(0x0000ff00)
-#define CSR5_BYTE2 FIELD32(0x00ff0000)
-#define CSR5_BYTE3 FIELD32(0xff000000)
-
-/*
- * CSR6: BSSID register 1.
- */
-#define CSR6 0x0018
-#define CSR6_BYTE4 FIELD32(0x000000ff)
-#define CSR6_BYTE5 FIELD32(0x0000ff00)
-
-/*
- * CSR7: Interrupt source register.
- * Write 1 to clear.
- * TBCN_EXPIRE: Beacon timer expired interrupt.
- * TWAKE_EXPIRE: Wakeup timer expired interrupt.
- * TATIMW_EXPIRE: Timer of atim window expired interrupt.
- * TXDONE_TXRING: Tx ring transmit done interrupt.
- * TXDONE_ATIMRING: Atim ring transmit done interrupt.
- * TXDONE_PRIORING: Priority ring transmit done interrupt.
- * RXDONE: Receive done interrupt.
- * DECRYPTION_DONE: Decryption done interrupt.
- * ENCRYPTION_DONE: Encryption done interrupt.
- * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
- * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
- * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
- * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
- * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
- * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
- * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
- * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
- * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
- * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
- * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
-
- */
-#define CSR7 0x001c
-#define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
-#define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
-#define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
-#define CSR7_TXDONE_TXRING FIELD32(0x00000008)
-#define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
-#define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
-#define CSR7_RXDONE FIELD32(0x00000040)
-#define CSR7_DECRYPTION_DONE FIELD32(0x00000080)
-#define CSR7_ENCRYPTION_DONE FIELD32(0x00000100)
-#define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200)
-#define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400)
-#define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
-#define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
-#define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
-#define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000)
-#define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000)
-#define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
-#define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
-#define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
-#define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
-
-/*
- * CSR8: Interrupt mask register.
- * Write 1 to mask interrupt.
- * TBCN_EXPIRE: Beacon timer expired interrupt.
- * TWAKE_EXPIRE: Wakeup timer expired interrupt.
- * TATIMW_EXPIRE: Timer of atim window expired interrupt.
- * TXDONE_TXRING: Tx ring transmit done interrupt.
- * TXDONE_ATIMRING: Atim ring transmit done interrupt.
- * TXDONE_PRIORING: Priority ring transmit done interrupt.
- * RXDONE: Receive done interrupt.
- * DECRYPTION_DONE: Decryption done interrupt.
- * ENCRYPTION_DONE: Encryption done interrupt.
- * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
- * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
- * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
- * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
- * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
- * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
- * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
- * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
- * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
- * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
- * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
- */
-#define CSR8 0x0020
-#define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
-#define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
-#define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
-#define CSR8_TXDONE_TXRING FIELD32(0x00000008)
-#define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
-#define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
-#define CSR8_RXDONE FIELD32(0x00000040)
-#define CSR8_DECRYPTION_DONE FIELD32(0x00000080)
-#define CSR8_ENCRYPTION_DONE FIELD32(0x00000100)
-#define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200)
-#define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400)
-#define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
-#define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
-#define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
-#define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000)
-#define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000)
-#define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
-#define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
-#define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
-#define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
-
-/*
- * CSR9: Maximum frame length register.
- * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
- */
-#define CSR9 0x0024
-#define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
-
-/*
- * SECCSR0: WEP control register.
- * KICK_DECRYPT: Kick decryption engine, self-clear.
- * ONE_SHOT: 0: ring mode, 1: One shot only mode.
- * DESC_ADDRESS: Descriptor physical address of frame.
- */
-#define SECCSR0 0x0028
-#define SECCSR0_KICK_DECRYPT FIELD32(0x00000001)
-#define SECCSR0_ONE_SHOT FIELD32(0x00000002)
-#define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc)
-
-/*
- * CSR11: Back-off control register.
- * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
- * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
- * SLOT_TIME: Slot time, default is 20us for 802.11b
- * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD.
- * LONG_RETRY: Long retry count.
- * SHORT_RETRY: Short retry count.
- */
-#define CSR11 0x002c
-#define CSR11_CWMIN FIELD32(0x0000000f)
-#define CSR11_CWMAX FIELD32(0x000000f0)
-#define CSR11_SLOT_TIME FIELD32(0x00001f00)
-#define CSR11_CW_SELECT FIELD32(0x00002000)
-#define CSR11_LONG_RETRY FIELD32(0x00ff0000)
-#define CSR11_SHORT_RETRY FIELD32(0xff000000)
-
-/*
- * CSR12: Synchronization configuration register 0.
- * All units in 1/16 TU.
- * BEACON_INTERVAL: Beacon interval, default is 100 TU.
- * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU.
- */
-#define CSR12 0x0030
-#define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
-#define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
-
-/*
- * CSR13: Synchronization configuration register 1.
- * All units in 1/16 TU.
- * ATIMW_DURATION: Atim window duration.
- * CFP_PERIOD: Cfp period, default is 0 TU.
- */
-#define CSR13 0x0034
-#define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
-#define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
-
-/*
- * CSR14: Synchronization control register.
- * TSF_COUNT: Enable tsf auto counting.
- * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
- * TBCN: Enable tbcn with reload value.
- * TCFP: Enable tcfp & cfp / cp switching.
- * TATIMW: Enable tatimw & atim window switching.
- * BEACON_GEN: Enable beacon generator.
- * CFP_COUNT_PRELOAD: Cfp count preload value.
- * TBCM_PRELOAD: Tbcn preload value in units of 64us.
- */
-#define CSR14 0x0038
-#define CSR14_TSF_COUNT FIELD32(0x00000001)
-#define CSR14_TSF_SYNC FIELD32(0x00000006)
-#define CSR14_TBCN FIELD32(0x00000008)
-#define CSR14_TCFP FIELD32(0x00000010)
-#define CSR14_TATIMW FIELD32(0x00000020)
-#define CSR14_BEACON_GEN FIELD32(0x00000040)
-#define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
-#define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
-
-/*
- * CSR15: Synchronization status register.
- * CFP: ASIC is in contention-free period.
- * ATIMW: ASIC is in ATIM window.
- * BEACON_SENT: Beacon is send.
- */
-#define CSR15 0x003c
-#define CSR15_CFP FIELD32(0x00000001)
-#define CSR15_ATIMW FIELD32(0x00000002)
-#define CSR15_BEACON_SENT FIELD32(0x00000004)
-
-/*
- * CSR16: TSF timer register 0.
- */
-#define CSR16 0x0040
-#define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
-
-/*
- * CSR17: TSF timer register 1.
- */
-#define CSR17 0x0044
-#define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
-
-/*
- * CSR18: IFS timer register 0.
- * SIFS: Sifs, default is 10 us.
- * PIFS: Pifs, default is 30 us.
- */
-#define CSR18 0x0048
-#define CSR18_SIFS FIELD32(0x000001ff)
-#define CSR18_PIFS FIELD32(0x001f0000)
-
-/*
- * CSR19: IFS timer register 1.
- * DIFS: Difs, default is 50 us.
- * EIFS: Eifs, default is 364 us.
- */
-#define CSR19 0x004c
-#define CSR19_DIFS FIELD32(0x0000ffff)
-#define CSR19_EIFS FIELD32(0xffff0000)
-
-/*
- * CSR20: Wakeup timer register.
- * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
- * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
- * AUTOWAKE: Enable auto wakeup / sleep mechanism.
- */
-#define CSR20 0x0050
-#define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
-#define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
-#define CSR20_AUTOWAKE FIELD32(0x01000000)
-
-/*
- * CSR21: EEPROM control register.
- * RELOAD: Write 1 to reload eeprom content.
- * TYPE_93C46: 1: 93c46, 0:93c66.
- */
-#define CSR21 0x0054
-#define CSR21_RELOAD FIELD32(0x00000001)
-#define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
-#define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
-#define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
-#define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
-#define CSR21_TYPE_93C46 FIELD32(0x00000020)
-
-/*
- * CSR22: CFP control register.
- * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
- * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
- */
-#define CSR22 0x0058
-#define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
-#define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
-
-/*
- * Transmit related CSRs.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * TXCSR0: TX Control Register.
- * KICK_TX: Kick tx ring.
- * KICK_ATIM: Kick atim ring.
- * KICK_PRIO: Kick priority ring.
- * ABORT: Abort all transmit related ring operation.
- */
-#define TXCSR0 0x0060
-#define TXCSR0_KICK_TX FIELD32(0x00000001)
-#define TXCSR0_KICK_ATIM FIELD32(0x00000002)
-#define TXCSR0_KICK_PRIO FIELD32(0x00000004)
-#define TXCSR0_ABORT FIELD32(0x00000008)
-
-/*
- * TXCSR1: TX Configuration Register.
- * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
- * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
- * TSF_OFFSET: Insert tsf offset.
- * AUTORESPONDER: Enable auto responder which include ack & cts.
- */
-#define TXCSR1 0x0064
-#define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
-#define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
-#define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
-#define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
-
-/*
- * TXCSR2: Tx descriptor configuration register.
- * TXD_SIZE: Tx descriptor size, default is 48.
- * NUM_TXD: Number of tx entries in ring.
- * NUM_ATIM: Number of atim entries in ring.
- * NUM_PRIO: Number of priority entries in ring.
- */
-#define TXCSR2 0x0068
-#define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
-#define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
-#define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
-#define TXCSR2_NUM_PRIO FIELD32(0xff000000)
-
-/*
- * TXCSR3: TX Ring Base address register.
- */
-#define TXCSR3 0x006c
-#define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * TXCSR4: TX Atim Ring Base address register.
- */
-#define TXCSR4 0x0070
-#define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * TXCSR5: TX Prio Ring Base address register.
- */
-#define TXCSR5 0x0074
-#define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * TXCSR6: Beacon Base address register.
- */
-#define TXCSR6 0x0078
-#define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * TXCSR7: Auto responder control register.
- * AR_POWERMANAGEMENT: Auto responder power management bit.
- */
-#define TXCSR7 0x007c
-#define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
-
-/*
- * TXCSR8: CCK Tx BBP register.
- */
-#define TXCSR8 0x0098
-#define TXCSR8_BBP_ID0 FIELD32(0x0000007f)
-#define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080)
-#define TXCSR8_BBP_ID1 FIELD32(0x00007f00)
-#define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000)
-#define TXCSR8_BBP_ID2 FIELD32(0x007f0000)
-#define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000)
-#define TXCSR8_BBP_ID3 FIELD32(0x7f000000)
-#define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000)
-
-/*
- * TXCSR9: OFDM TX BBP registers
- * OFDM_SIGNAL: BBP rate field address for OFDM.
- * OFDM_SERVICE: BBP service field address for OFDM.
- * OFDM_LENGTH_LOW: BBP length low byte address for OFDM.
- * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM.
- */
-#define TXCSR9 0x0094
-#define TXCSR9_OFDM_RATE FIELD32(0x000000ff)
-#define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00)
-#define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000)
-#define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000)
-
-/*
- * Receive related CSRs.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * RXCSR0: RX Control Register.
- * DISABLE_RX: Disable rx engine.
- * DROP_CRC: Drop crc error.
- * DROP_PHYSICAL: Drop physical error.
- * DROP_CONTROL: Drop control frame.
- * DROP_NOT_TO_ME: Drop not to me unicast frame.
- * DROP_TODS: Drop frame tods bit is true.
- * DROP_VERSION_ERROR: Drop version error frame.
- * PASS_CRC: Pass all packets with crc attached.
- * PASS_CRC: Pass all packets with crc attached.
- * PASS_PLCP: Pass all packets with 4 bytes PLCP attached.
- * DROP_MCAST: Drop multicast frames.
- * DROP_BCAST: Drop broadcast frames.
- * ENABLE_QOS: Accept QOS data frame and parse QOS field.
- */
-#define RXCSR0 0x0080
-#define RXCSR0_DISABLE_RX FIELD32(0x00000001)
-#define RXCSR0_DROP_CRC FIELD32(0x00000002)
-#define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
-#define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
-#define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
-#define RXCSR0_DROP_TODS FIELD32(0x00000020)
-#define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
-#define RXCSR0_PASS_CRC FIELD32(0x00000080)
-#define RXCSR0_PASS_PLCP FIELD32(0x00000100)
-#define RXCSR0_DROP_MCAST FIELD32(0x00000200)
-#define RXCSR0_DROP_BCAST FIELD32(0x00000400)
-#define RXCSR0_ENABLE_QOS FIELD32(0x00000800)
-
-/*
- * RXCSR1: RX descriptor configuration register.
- * RXD_SIZE: Rx descriptor size, default is 32b.
- * NUM_RXD: Number of rx entries in ring.
- */
-#define RXCSR1 0x0084
-#define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
-#define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
-
-/*
- * RXCSR2: RX Ring base address register.
- */
-#define RXCSR2 0x0088
-#define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * RXCSR3: BBP ID register for Rx operation.
- * BBP_ID#: BBP register # id.
- * BBP_ID#_VALID: BBP register # id is valid or not.
- */
-#define RXCSR3 0x0090
-#define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
-#define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
-#define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
-#define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
-#define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
-#define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
-#define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
-#define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
-
-/*
- * ARCSR1: Auto Responder PLCP config register 1.
- * AR_BBP_DATA#: Auto responder BBP register # data.
- * AR_BBP_ID#: Auto responder BBP register # Id.
- */
-#define ARCSR1 0x009c
-#define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
-#define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
-#define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
-#define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
-
-/*
- * Miscellaneous Registers.
- * Some values are set in TU, whereas 1 TU == 1024 us.
-
- */
-
-/*
- * PCICSR: PCI control register.
- * BIG_ENDIAN: 1: big endian, 0: little endian.
- * RX_TRESHOLD: Rx threshold in dw to start pci access
- * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
- * TX_TRESHOLD: Tx threshold in dw to start pci access
- * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
- * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
- * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
- * READ_MULTIPLE: Enable memory read multiple.
- * WRITE_INVALID: Enable memory write & invalid.
- */
-#define PCICSR 0x008c
-#define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
-#define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
-#define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
-#define PCICSR_BURST_LENTH FIELD32(0x00000060)
-#define PCICSR_ENABLE_CLK FIELD32(0x00000080)
-#define PCICSR_READ_MULTIPLE FIELD32(0x00000100)
-#define PCICSR_WRITE_INVALID FIELD32(0x00000200)
-
-/*
- * CNT0: FCS error count.
- * FCS_ERROR: FCS error count, cleared when read.
- */
-#define CNT0 0x00a0
-#define CNT0_FCS_ERROR FIELD32(0x0000ffff)
-
-/*
- * Statistic Register.
- * CNT1: PLCP error count.
- * CNT2: Long error count.
- */
-#define TIMECSR2 0x00a8
-#define CNT1 0x00ac
-#define CNT2 0x00b0
-#define TIMECSR3 0x00b4
-
-/*
- * CNT3: CCA false alarm count.
- */
-#define CNT3 0x00b8
-#define CNT3_FALSE_CCA FIELD32(0x0000ffff)
-
-/*
- * Statistic Register.
- * CNT4: Rx FIFO overflow count.
- * CNT5: Tx FIFO underrun count.
- */
-#define CNT4 0x00bc
-#define CNT5 0x00c0
-
-/*
- * Baseband Control Register.
- */
-
-/*
- * PWRCSR0: Power mode configuration register.
- */
-#define PWRCSR0 0x00c4
-
-/*
- * Power state transition time registers.
- */
-#define PSCSR0 0x00c8
-#define PSCSR1 0x00cc
-#define PSCSR2 0x00d0
-#define PSCSR3 0x00d4
-
-/*
- * PWRCSR1: Manual power control / status register.
- * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
- * SET_STATE: Set state. Write 1 to trigger, self cleared.
- * BBP_DESIRE_STATE: BBP desired state.
- * RF_DESIRE_STATE: RF desired state.
- * BBP_CURR_STATE: BBP current state.
- * RF_CURR_STATE: RF current state.
- * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
- */
-#define PWRCSR1 0x00d8
-#define PWRCSR1_SET_STATE FIELD32(0x00000001)
-#define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
-#define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
-#define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
-#define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
-#define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
-
-/*
- * TIMECSR: Timer control register.
- * US_COUNT: 1 us timer count in units of clock cycles.
- * US_64_COUNT: 64 us timer count in units of 1 us timer.
- * BEACON_EXPECT: Beacon expect window.
- */
-#define TIMECSR 0x00dc
-#define TIMECSR_US_COUNT FIELD32(0x000000ff)
-#define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
-#define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
-
-/*
- * MACCSR0: MAC configuration register 0.
- */
-#define MACCSR0 0x00e0
-
-/*
- * MACCSR1: MAC configuration register 1.
- * KICK_RX: Kick one-shot rx in one-shot rx mode.
- * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
- * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
- * AUTO_TXBBP: Auto tx logic access bbp control register.
- * AUTO_RXBBP: Auto rx logic access bbp control register.
- * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
- * INTERSIL_IF: Intersil if calibration pin.
- */
-#define MACCSR1 0x00e4
-#define MACCSR1_KICK_RX FIELD32(0x00000001)
-#define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
-#define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
-#define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
-#define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
-#define MACCSR1_LOOPBACK FIELD32(0x00000060)
-#define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
-
-/*
- * RALINKCSR: Ralink Rx auto-reset BBCR.
- * AR_BBP_DATA#: Auto reset BBP register # data.
- * AR_BBP_ID#: Auto reset BBP register # id.
- */
-#define RALINKCSR 0x00e8
-#define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
-#define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00)
-#define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000)
-#define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
-#define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000)
-#define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000)
-
-/*
- * BCNCSR: Beacon interval control register.
- * CHANGE: Write one to change beacon interval.
- * DELTATIME: The delta time value.
- * NUM_BEACON: Number of beacon according to mode.
- * MODE: Please refer to asic specs.
- * PLUS: Plus or minus delta time value.
- */
-#define BCNCSR 0x00ec
-#define BCNCSR_CHANGE FIELD32(0x00000001)
-#define BCNCSR_DELTATIME FIELD32(0x0000001e)
-#define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
-#define BCNCSR_MODE FIELD32(0x00006000)
-#define BCNCSR_PLUS FIELD32(0x00008000)
-
-/*
- * BBP / RF / IF Control Register.
- */
-
-/*
- * BBPCSR: BBP serial control register.
- * VALUE: Register value to program into BBP.
- * REGNUM: Selected BBP register.
- * BUSY: 1: asic is busy execute BBP programming.
- * WRITE_CONTROL: 1: write BBP, 0: read BBP.
- */
-#define BBPCSR 0x00f0
-#define BBPCSR_VALUE FIELD32(0x000000ff)
-#define BBPCSR_REGNUM FIELD32(0x00007f00)
-#define BBPCSR_BUSY FIELD32(0x00008000)
-#define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
-
-/*
- * RFCSR: RF serial control register.
- * VALUE: Register value + id to program into rf/if.
- * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
- * IF_SELECT: Chip to program: 0: rf, 1: if.
- * PLL_LD: Rf pll_ld status.
- * BUSY: 1: asic is busy execute rf programming.
- */
-#define RFCSR 0x00f4
-#define RFCSR_VALUE FIELD32(0x00ffffff)
-#define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
-#define RFCSR_IF_SELECT FIELD32(0x20000000)
-#define RFCSR_PLL_LD FIELD32(0x40000000)
-#define RFCSR_BUSY FIELD32(0x80000000)
-
-/*
- * LEDCSR: LED control register.
- * ON_PERIOD: On period, default 70ms.
- * OFF_PERIOD: Off period, default 30ms.
- * LINK: 0: linkoff, 1: linkup.
- * ACTIVITY: 0: idle, 1: active.
- * LINK_POLARITY: 0: active low, 1: active high.
- * ACTIVITY_POLARITY: 0: active low, 1: active high.
- * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF.
- */
-#define LEDCSR 0x00f8
-#define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
-#define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
-#define LEDCSR_LINK FIELD32(0x00010000)
-#define LEDCSR_ACTIVITY FIELD32(0x00020000)
-#define LEDCSR_LINK_POLARITY FIELD32(0x00040000)
-#define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000)
-#define LEDCSR_LED_DEFAULT FIELD32(0x00100000)
-
-/*
- * AES control register.
- */
-#define SECCSR3 0x00fc
-
-/*
- * ASIC pointer information.
- * RXPTR: Current RX ring address.
- * TXPTR: Current Tx ring address.
- * PRIPTR: Current Priority ring address.
- * ATIMPTR: Current ATIM ring address.
- */
-#define RXPTR 0x0100
-#define TXPTR 0x0104
-#define PRIPTR 0x0108
-#define ATIMPTR 0x010c
-
-/*
- * TXACKCSR0: TX ACK timeout.
- */
-#define TXACKCSR0 0x0110
-
-/*
- * ACK timeout count registers.
- * ACKCNT0: TX ACK timeout count.
- * ACKCNT1: RX ACK timeout count.
- */
-#define ACKCNT0 0x0114
-#define ACKCNT1 0x0118
-
-/*
- * GPIO and others.
- */
-
-/*
- * GPIOCSR: GPIO control register.
- */
-#define GPIOCSR 0x0120
-#define GPIOCSR_BIT0 FIELD32(0x00000001)
-#define GPIOCSR_BIT1 FIELD32(0x00000002)
-#define GPIOCSR_BIT2 FIELD32(0x00000004)
-#define GPIOCSR_BIT3 FIELD32(0x00000008)
-#define GPIOCSR_BIT4 FIELD32(0x00000010)
-#define GPIOCSR_BIT5 FIELD32(0x00000020)
-#define GPIOCSR_BIT6 FIELD32(0x00000040)
-#define GPIOCSR_BIT7 FIELD32(0x00000080)
-#define GPIOCSR_DIR0 FIELD32(0x00000100)
-#define GPIOCSR_DIR1 FIELD32(0x00000200)
-#define GPIOCSR_DIR2 FIELD32(0x00000400)
-#define GPIOCSR_DIR3 FIELD32(0x00000800)
-#define GPIOCSR_DIR4 FIELD32(0x00001000)
-#define GPIOCSR_DIR5 FIELD32(0x00002000)
-#define GPIOCSR_DIR6 FIELD32(0x00004000)
-#define GPIOCSR_DIR7 FIELD32(0x00008000)
-
-/*
- * FIFO pointer registers.
- * FIFOCSR0: TX FIFO pointer.
- * FIFOCSR1: RX FIFO pointer.
- */
-#define FIFOCSR0 0x0128
-#define FIFOCSR1 0x012c
-
-/*
- * BCNCSR1: Tx BEACON offset time control register.
- * PRELOAD: Beacon timer offset in units of usec.
- * BEACON_CWMIN: 2^CwMin.
- */
-#define BCNCSR1 0x0130
-#define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
-#define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000)
-
-/*
- * MACCSR2: TX_PE to RX_PE turn-around time control register
- * DELAY: RX_PE low width, in units of pci clock cycle.
- */
-#define MACCSR2 0x0134
-#define MACCSR2_DELAY FIELD32(0x000000ff)
-
-/*
- * TESTCSR: TEST mode selection register.
- */
-#define TESTCSR 0x0138
-
-/*
- * ARCSR2: 1 Mbps ACK/CTS PLCP.
- */
-#define ARCSR2 0x013c
-#define ARCSR2_SIGNAL FIELD32(0x000000ff)
-#define ARCSR2_SERVICE FIELD32(0x0000ff00)
-#define ARCSR2_LENGTH FIELD32(0xffff0000)
-
-/*
- * ARCSR3: 2 Mbps ACK/CTS PLCP.
- */
-#define ARCSR3 0x0140
-#define ARCSR3_SIGNAL FIELD32(0x000000ff)
-#define ARCSR3_SERVICE FIELD32(0x0000ff00)
-#define ARCSR3_LENGTH FIELD32(0xffff0000)
-
-/*
- * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
- */
-#define ARCSR4 0x0144
-#define ARCSR4_SIGNAL FIELD32(0x000000ff)
-#define ARCSR4_SERVICE FIELD32(0x0000ff00)
-#define ARCSR4_LENGTH FIELD32(0xffff0000)
-
-/*
- * ARCSR5: 11 Mbps ACK/CTS PLCP.
- */
-#define ARCSR5 0x0148
-#define ARCSR5_SIGNAL FIELD32(0x000000ff)
-#define ARCSR5_SERVICE FIELD32(0x0000ff00)
-#define ARCSR5_LENGTH FIELD32(0xffff0000)
-
-/*
- * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps.
- */
-#define ARTCSR0 0x014c
-#define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff)
-#define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00)
-#define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000)
-#define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000)
-
-
-/*
- * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
- */
-#define ARTCSR1 0x0150
-#define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff)
-#define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00)
-#define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000)
-#define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000)
-
-/*
- * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
- */
-#define ARTCSR2 0x0154
-#define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff)
-#define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00)
-#define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000)
-#define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000)
-
-/*
- * SECCSR1_RT2509: WEP control register.
- * KICK_ENCRYPT: Kick encryption engine, self-clear.
- * ONE_SHOT: 0: ring mode, 1: One shot only mode.
- * DESC_ADDRESS: Descriptor physical address of frame.
- */
-#define SECCSR1 0x0158
-#define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001)
-#define SECCSR1_ONE_SHOT FIELD32(0x00000002)
-#define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc)
-
-/*
- * BBPCSR1: BBP TX configuration.
- */
-#define BBPCSR1 0x015c
-#define BBPCSR1_CCK FIELD32(0x00000003)
-#define BBPCSR1_CCK_FLIP FIELD32(0x00000004)
-#define BBPCSR1_OFDM FIELD32(0x00030000)
-#define BBPCSR1_OFDM_FLIP FIELD32(0x00040000)
-
-/*
- * Dual band configuration registers.
- * DBANDCSR0: Dual band configuration register 0.
- * DBANDCSR1: Dual band configuration register 1.
- */
-#define DBANDCSR0 0x0160
-#define DBANDCSR1 0x0164
-
-/*
- * BBPPCSR: BBP Pin control register.
- */
-#define BBPPCSR 0x0168
-
-/*
- * MAC special debug mode selection registers.
- * DBGSEL0: MAC special debug mode selection register 0.
- * DBGSEL1: MAC special debug mode selection register 1.
- */
-#define DBGSEL0 0x016c
-#define DBGSEL1 0x0170
-
-/*
- * BISTCSR: BBP BIST register.
- */
-#define BISTCSR 0x0174
-
-/*
- * Multicast filter registers.
- * MCAST0: Multicast filter register 0.
- * MCAST1: Multicast filter register 1.
- */
-#define MCAST0 0x0178
-#define MCAST1 0x017c
-
-/*
- * UART registers.
- * UARTCSR0: UART1 TX register.
- * UARTCSR1: UART1 RX register.
- * UARTCSR3: UART1 frame control register.
- * UARTCSR4: UART1 buffer control register.
- * UART2CSR0: UART2 TX register.
- * UART2CSR1: UART2 RX register.
- * UART2CSR3: UART2 frame control register.
- * UART2CSR4: UART2 buffer control register.
- */
-#define UARTCSR0 0x0180
-#define UARTCSR1 0x0184
-#define UARTCSR3 0x0188
-#define UARTCSR4 0x018c
-#define UART2CSR0 0x0190
-#define UART2CSR1 0x0194
-#define UART2CSR3 0x0198
-#define UART2CSR4 0x019c
-
-/*
- * BBP registers.
- * The wordsize of the BBP is 8 bits.
- */
-
-/*
- * R2: TX antenna control
- */
-#define BBP_R2_TX_ANTENNA FIELD8(0x03)
-#define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
-
-/*
- * R14: RX antenna control
- */
-#define BBP_R14_RX_ANTENNA FIELD8(0x03)
-#define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
-
-/*
- * BBP_R70
- */
-#define BBP_R70_JAPAN_FILTER FIELD8(0x08)
-
-/*
- * RF registers
- */
-
-/*
- * RF 1
- */
-#define RF1_TUNER FIELD32(0x00020000)
-
-/*
- * RF 3
- */
-#define RF3_TUNER FIELD32(0x00000100)
-#define RF3_TXPOWER FIELD32(0x00003e00)
-
-/*
- * EEPROM content.
- * The wordsize of the EEPROM is 16 bits.
- */
-
-/*
- * HW MAC address.
- */
-#define EEPROM_MAC_ADDR_0 0x0002
-#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR1 0x0003
-#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR_2 0x0004
-#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
-
-/*
- * EEPROM antenna.
- * ANTENNA_NUM: Number of antenna's.
- * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
- * DYN_TXAGC: Dynamic TX AGC control.
- * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
- * RF_TYPE: Rf_type of this adapter.
- */
-#define EEPROM_ANTENNA 0x10
-#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
-#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
-#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
-#define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
-#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
-#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
-#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
-
-/*
- * EEPROM NIC config.
- * CARDBUS_ACCEL: 0: enable, 1: disable.
- * DYN_BBP_TUNE: 0: enable, 1: disable.
- * CCK_TX_POWER: CCK TX power compensation.
- */
-#define EEPROM_NIC 0x11
-#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
-#define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
-#define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
-
-/*
- * EEPROM geography.
- * GEO: Default geography setting for device.
- */
-#define EEPROM_GEOGRAPHY 0x12
-#define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
-
-/*
- * EEPROM BBP.
- */
-#define EEPROM_BBP_START 0x13
-#define EEPROM_BBP_SIZE 16
-#define EEPROM_BBP_VALUE FIELD16(0x00ff)
-#define EEPROM_BBP_REG_ID FIELD16(0xff00)
-
-/*
- * EEPROM TXPOWER
- */
-#define EEPROM_TXPOWER_START 0x23
-#define EEPROM_TXPOWER_SIZE 7
-#define EEPROM_TXPOWER_1 FIELD16(0x00ff)
-#define EEPROM_TXPOWER_2 FIELD16(0xff00)
-
-/*
- * RSSI <-> dBm offset calibration
- */
-#define EEPROM_CALIBRATE_OFFSET 0x3e
-#define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
-
-/*
- * DMA descriptor defines.
- */
-#define TXD_DESC_SIZE ( 11 * sizeof(struct data_desc) )
-#define RXD_DESC_SIZE ( 11 * sizeof(struct data_desc) )
-
-/*
- * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
- */
-
-/*
- * Word0
- */
-#define TXD_W0_OWNER_NIC FIELD32(0x00000001)
-#define TXD_W0_VALID FIELD32(0x00000002)
-#define TXD_W0_RESULT FIELD32(0x0000001c)
-#define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
-#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
-#define TXD_W0_ACK FIELD32(0x00000200)
-#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
-#define TXD_W0_OFDM FIELD32(0x00000800)
-#define TXD_W0_CIPHER_OWNER FIELD32(0x00001000)
-#define TXD_W0_IFS FIELD32(0x00006000)
-#define TXD_W0_RETRY_MODE FIELD32(0x00008000)
-#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
-#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
-
-/*
- * Word1
- */
-#define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
-
-/*
- * Word2
- */
-#define TXD_W2_IV_OFFSET FIELD32(0x0000003f)
-#define TXD_W2_AIFS FIELD32(0x000000c0)
-#define TXD_W2_CWMIN FIELD32(0x00000f00)
-#define TXD_W2_CWMAX FIELD32(0x0000f000)
-
-/*
- * Word3: PLCP information
- */
-#define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
-#define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00)
-#define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
-#define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000)
-
-/*
- * Word4
- */
-#define TXD_W4_IV FIELD32(0xffffffff)
-
-/*
- * Word5
- */
-#define TXD_W5_EIV FIELD32(0xffffffff)
-
-/*
- * Word6-9: Key
- */
-#define TXD_W6_KEY FIELD32(0xffffffff)
-#define TXD_W7_KEY FIELD32(0xffffffff)
-#define TXD_W8_KEY FIELD32(0xffffffff)
-#define TXD_W9_KEY FIELD32(0xffffffff)
-
-/*
- * Word10
- */
-#define TXD_W10_RTS FIELD32(0x00000001)
-#define TXD_W10_TX_RATE FIELD32(0x000000fe)
-
-/*
- * RX descriptor format for RX Ring.
- */
-
-/*
- * Word0
- */
-#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
-#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
-#define RXD_W0_MULTICAST FIELD32(0x00000004)
-#define RXD_W0_BROADCAST FIELD32(0x00000008)
-#define RXD_W0_MY_BSS FIELD32(0x00000010)
-#define RXD_W0_CRC_ERROR FIELD32(0x00000020)
-#define RXD_W0_OFDM FIELD32(0x00000040)
-#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
-#define RXD_W0_CIPHER_OWNER FIELD32(0x00000100)
-#define RXD_W0_ICV_ERROR FIELD32(0x00000200)
-#define RXD_W0_IV_OFFSET FIELD32(0x0000fc00)
-#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
-#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
-
-/*
- * Word1
- */
-#define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
-
-/*
- * Word2
- */
-#define RXD_W2_SIGNAL FIELD32(0x000000ff)
-#define RXD_W2_RSSI FIELD32(0x0000ff00)
-#define RXD_W2_TA FIELD32(0xffff0000)
-
-/*
- * Word3
- */
-#define RXD_W3_TA FIELD32(0xffffffff)
-
-/*
- * Word4
- */
-#define RXD_W4_IV FIELD32(0xffffffff)
-
-/*
- * Word5
- */
-#define RXD_W5_EIV FIELD32(0xffffffff)
-
-/*
- * Word6-9: Key
- */
-#define RXD_W6_KEY FIELD32(0xffffffff)
-#define RXD_W7_KEY FIELD32(0xffffffff)
-#define RXD_W8_KEY FIELD32(0xffffffff)
-#define RXD_W9_KEY FIELD32(0xffffffff)
-
-/*
- * Word10
- */
-#define RXD_W10_DROP FIELD32(0x00000001)
-
-/*
- * Macro's for converting txpower from EEPROM to dscape value
- * and from dscape value to register value.
- */
-#define MIN_TXPOWER 0
-#define MAX_TXPOWER 31
-#define DEFAULT_TXPOWER 24
-
-#define TXPOWER_FROM_DEV(__txpower) \
-({ \
- ((__txpower) > MAX_TXPOWER) ? \
- DEFAULT_TXPOWER : (__txpower); \
-})
-
-#define TXPOWER_TO_DEV(__txpower) \
-({ \
- ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
- (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
- (__txpower)); \
-})
-
-#endif /* RT2500PCI_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2500usb
- Abstract: rt2500usb device specific routines.
- Supported chipsets: RT2570.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2500usb"
-
-#include <linux/delay.h>
-#include <linux/etherdevice.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/usb.h>
-
-#include "rt2x00.h"
-#include "rt2x00usb.h"
-#include "rt2500usb.h"
-
-/*
- * Register access.
- * All access to the CSR registers will go through the methods
- * rt2500usb_register_read and rt2500usb_register_write.
- * BBP and RF register require indirect register access,
- * and use the CSR registers BBPCSR and RFCSR to achieve this.
- * These indirect registers work with busy bits,
- * and we will try maximal REGISTER_BUSY_COUNT times to access
- * the register while taking a REGISTER_BUSY_DELAY us delay
- * between each attampt. When the busy bit is still set at that time,
- * the access attempt is considered to have failed,
- * and we will print an error.
- */
-static inline void rt2500usb_register_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned int offset,
- u16 *value)
-{
- __le16 reg;
- rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
- USB_VENDOR_REQUEST_IN, offset,
- ®, sizeof(u16), REGISTER_TIMEOUT);
- *value = le16_to_cpu(reg);
-}
-
-static inline void rt2500usb_register_multiread(const struct rt2x00_dev
- *rt2x00dev,
- const unsigned int offset,
- void *value, const u16 length)
-{
- int timeout = REGISTER_TIMEOUT * (length / sizeof(u16));
- rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
- USB_VENDOR_REQUEST_IN, offset,
- value, length, timeout);
-}
-
-static inline void rt2500usb_register_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int offset,
- u16 value)
-{
- __le16 reg = cpu_to_le16(value);
- rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
- USB_VENDOR_REQUEST_OUT, offset,
- ®, sizeof(u16), REGISTER_TIMEOUT);
-}
-
-static inline void rt2500usb_register_multiwrite(const struct rt2x00_dev
- *rt2x00dev,
- const unsigned int offset,
- void *value, const u16 length)
-{
- int timeout = REGISTER_TIMEOUT * (length / sizeof(u16));
- rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
- USB_VENDOR_REQUEST_OUT, offset,
- value, length, timeout);
-}
-
-static u16 rt2500usb_bbp_check(const struct rt2x00_dev *rt2x00dev)
-{
- u16 reg;
- unsigned int i;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2500usb_register_read(rt2x00dev, PHY_CSR8, ®);
- if (!rt2x00_get_field16(reg, PHY_CSR8_BUSY))
- break;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- return reg;
-}
-
-static void rt2500usb_bbp_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u8 value)
-{
- u16 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt2500usb_bbp_check(rt2x00dev);
- if (rt2x00_get_field16(reg, PHY_CSR8_BUSY)) {
- ERROR(rt2x00dev, "PHY_CSR8 register busy. Write failed.\n");
- return;
- }
-
- /*
- * Write the data into the BBP.
- */
- reg = 0;
- rt2x00_set_field16(®, PHY_CSR7_DATA, value);
- rt2x00_set_field16(®, PHY_CSR7_REG_ID, word);
- rt2x00_set_field16(®, PHY_CSR7_READ_CONTROL, 0);
-
- rt2500usb_register_write(rt2x00dev, PHY_CSR7, reg);
-}
-
-static void rt2500usb_bbp_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u8 *value)
-{
- u16 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt2500usb_bbp_check(rt2x00dev);
- if (rt2x00_get_field16(reg, PHY_CSR8_BUSY)) {
- ERROR(rt2x00dev, "PHY_CSR8 register busy. Read failed.\n");
- return;
- }
-
- /*
- * Write the request into the BBP.
- */
- reg = 0;
- rt2x00_set_field16(®, PHY_CSR7_REG_ID, word);
- rt2x00_set_field16(®, PHY_CSR7_READ_CONTROL, 1);
-
- rt2500usb_register_write(rt2x00dev, PHY_CSR7, reg);
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt2500usb_bbp_check(rt2x00dev);
- if (rt2x00_get_field16(reg, PHY_CSR8_BUSY)) {
- ERROR(rt2x00dev, "PHY_CSR8 register busy. Read failed.\n");
- *value = 0xff;
- return;
- }
-
- rt2500usb_register_read(rt2x00dev, PHY_CSR7, ®);
- *value = rt2x00_get_field16(reg, PHY_CSR7_DATA);
-}
-
-static void rt2500usb_rf_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u32 value)
-{
- u16 reg;
- unsigned int i;
-
- if (!word)
- return;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2500usb_register_read(rt2x00dev, PHY_CSR10, ®);
- if (!rt2x00_get_field16(reg, PHY_CSR10_RF_BUSY))
- goto rf_write;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "PHY_CSR10 register busy. Write failed.\n");
- return;
-
-rf_write:
- reg = 0;
- rt2x00_set_field16(®, PHY_CSR9_RF_VALUE, value);
- rt2500usb_register_write(rt2x00dev, PHY_CSR9, reg);
-
- reg = 0;
- rt2x00_set_field16(®, PHY_CSR10_RF_VALUE, value >> 16);
- rt2x00_set_field16(®, PHY_CSR10_RF_NUMBER_OF_BITS, 20);
- rt2x00_set_field16(®, PHY_CSR10_RF_IF_SELECT, 0);
- rt2x00_set_field16(®, PHY_CSR10_RF_BUSY, 1);
-
- rt2500usb_register_write(rt2x00dev, PHY_CSR10, reg);
- rt2x00_rf_write(rt2x00dev, word, value);
-}
-
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u16)) )
-
-static void rt2500usb_read_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 *data)
-{
- rt2500usb_register_read(rt2x00dev, CSR_OFFSET(word), (u16 *) data);
-}
-
-static void rt2500usb_write_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 data)
-{
- rt2500usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static const struct rt2x00debug rt2500usb_rt2x00debug = {
- .owner = THIS_MODULE,
- .csr = {
- .read = rt2500usb_read_csr,
- .write = rt2500usb_write_csr,
- .word_size = sizeof(u16),
- .word_count = CSR_REG_SIZE / sizeof(u16),
- },
- .eeprom = {
- .read = rt2x00_eeprom_read,
- .write = rt2x00_eeprom_write,
- .word_size = sizeof(u16),
- .word_count = EEPROM_SIZE / sizeof(u16),
- },
- .bbp = {
- .read = rt2500usb_bbp_read,
- .write = rt2500usb_bbp_write,
- .word_size = sizeof(u8),
- .word_count = BBP_SIZE / sizeof(u8),
- },
- .rf = {
- .read = rt2x00_rf_read,
- .write = rt2500usb_rf_write,
- .word_size = sizeof(u32),
- .word_count = RF_SIZE / sizeof(u32),
- },
-};
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
-/*
- * Configuration handlers.
- */
-static void rt2500usb_config_mac_addr(struct rt2x00_dev *rt2x00dev,
- __le32 *mac)
-{
- rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
- (3 * sizeof(__le16)));
-}
-
-static void rt2500usb_config_bssid(struct rt2x00_dev *rt2x00dev,
- __le32 *bssid)
-{
- rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR5, bssid,
- (3 * sizeof(__le16)));
-}
-
-static void rt2500usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
- const int tsf_sync)
-{
- u16 reg;
-
- rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
-
- /*
- * Enable beacon config
- */
- rt2500usb_register_read(rt2x00dev, TXRX_CSR20, ®);
- rt2x00_set_field16(®, TXRX_CSR20_OFFSET,
- (PREAMBLE + get_duration(IEEE80211_HEADER, 20)) >> 6);
- if (type == IEEE80211_IF_TYPE_STA)
- rt2x00_set_field16(®, TXRX_CSR20_BCN_EXPECT_WINDOW, 0);
- else
- rt2x00_set_field16(®, TXRX_CSR20_BCN_EXPECT_WINDOW, 2);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR20, reg);
-
- /*
- * Enable synchronisation.
- */
- rt2500usb_register_read(rt2x00dev, TXRX_CSR18, ®);
- rt2x00_set_field16(®, TXRX_CSR18_OFFSET, 0);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR19, ®);
- rt2x00_set_field16(®, TXRX_CSR19_TSF_COUNT, 1);
- rt2x00_set_field16(®, TXRX_CSR19_TBCN, 1);
- rt2x00_set_field16(®, TXRX_CSR19_BEACON_GEN, 0);
- rt2x00_set_field16(®, TXRX_CSR19_TSF_SYNC, tsf_sync);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
-}
-
-static void rt2500usb_config_preamble(struct rt2x00_dev *rt2x00dev,
- const int short_preamble,
- const int ack_timeout,
- const int ack_consume_time)
-{
- u16 reg;
-
- /*
- * When in atomic context, reschedule and let rt2x00lib
- * call this function again.
- */
- if (in_atomic()) {
- queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
- return;
- }
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR1, ®);
- rt2x00_set_field16(®, TXRX_CSR1_ACK_TIMEOUT, ack_timeout);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR10, ®);
- rt2x00_set_field16(®, TXRX_CSR10_AUTORESPOND_PREAMBLE,
- !!short_preamble);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg);
-}
-
-static void rt2500usb_config_phymode(struct rt2x00_dev *rt2x00dev,
- const int phymode,
- const int basic_rate_mask)
-{
- rt2500usb_register_write(rt2x00dev, TXRX_CSR11, basic_rate_mask);
-
- if (phymode == HWMODE_B) {
- rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x000b);
- rt2500usb_register_write(rt2x00dev, MAC_CSR12, 0x0040);
- } else {
- rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x0005);
- rt2500usb_register_write(rt2x00dev, MAC_CSR12, 0x016c);
- }
-}
-
-static void rt2500usb_config_channel(struct rt2x00_dev *rt2x00dev,
- struct rf_channel *rf, const int txpower)
-{
- /*
- * Set TXpower.
- */
- rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
-
- /*
- * For RT2525E we should first set the channel to half band higher.
- */
- if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
- static const u32 vals[] = {
- 0x000008aa, 0x000008ae, 0x000008ae, 0x000008b2,
- 0x000008b2, 0x000008b6, 0x000008b6, 0x000008ba,
- 0x000008ba, 0x000008be, 0x000008b7, 0x00000902,
- 0x00000902, 0x00000906
- };
-
- rt2500usb_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
- if (rf->rf4)
- rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
- }
-
- rt2500usb_rf_write(rt2x00dev, 1, rf->rf1);
- rt2500usb_rf_write(rt2x00dev, 2, rf->rf2);
- rt2500usb_rf_write(rt2x00dev, 3, rf->rf3);
- if (rf->rf4)
- rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
-}
-
-static void rt2500usb_config_txpower(struct rt2x00_dev *rt2x00dev,
- const int txpower)
-{
- u32 rf3;
-
- rt2x00_rf_read(rt2x00dev, 3, &rf3);
- rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
- rt2500usb_rf_write(rt2x00dev, 3, rf3);
-}
-
-static void rt2500usb_config_antenna(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx, const int antenna_rx)
-{
- u8 r2;
- u8 r14;
- u16 csr5;
- u16 csr6;
-
- rt2500usb_bbp_read(rt2x00dev, 2, &r2);
- rt2500usb_bbp_read(rt2x00dev, 14, &r14);
- rt2500usb_register_read(rt2x00dev, PHY_CSR5, &csr5);
- rt2500usb_register_read(rt2x00dev, PHY_CSR6, &csr6);
-
- /*
- * Configure the TX antenna.
- */
- switch (antenna_tx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 1);
- rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 1);
- rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 1);
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
- rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 0);
- rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 0);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
- rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 2);
- rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 2);
- break;
- }
-
- /*
- * Configure the RX antenna.
- */
- switch (antenna_rx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 1);
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
- break;
- }
-
- /*
- * RT2525E and RT5222 need to flip TX I/Q
- */
- if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
- rt2x00_rf(&rt2x00dev->chip, RF5222)) {
- rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
- rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 1);
- rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 1);
-
- /*
- * RT2525E does not need RX I/Q Flip.
- */
- if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
- rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
- } else {
- rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 0);
- rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 0);
- }
-
- rt2500usb_bbp_write(rt2x00dev, 2, r2);
- rt2500usb_bbp_write(rt2x00dev, 14, r14);
- rt2500usb_register_write(rt2x00dev, PHY_CSR5, csr5);
- rt2500usb_register_write(rt2x00dev, PHY_CSR6, csr6);
-}
-
-static void rt2500usb_config_duration(struct rt2x00_dev *rt2x00dev,
- struct rt2x00lib_conf *libconf)
-{
- u16 reg;
-
- rt2500usb_register_write(rt2x00dev, MAC_CSR10, libconf->slot_time);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR18, ®);
- rt2x00_set_field16(®, TXRX_CSR18_INTERVAL,
- libconf->conf->beacon_int * 4);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
-}
-
-static void rt2500usb_config(struct rt2x00_dev *rt2x00dev,
- const unsigned int flags,
- struct rt2x00lib_conf *libconf)
-{
- if (flags & CONFIG_UPDATE_PHYMODE)
- rt2500usb_config_phymode(rt2x00dev, libconf->phymode,
- libconf->basic_rates);
- if (flags & CONFIG_UPDATE_CHANNEL)
- rt2500usb_config_channel(rt2x00dev, &libconf->rf,
- libconf->conf->power_level);
- if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
- rt2500usb_config_txpower(rt2x00dev,
- libconf->conf->power_level);
- if (flags & CONFIG_UPDATE_ANTENNA)
- rt2500usb_config_antenna(rt2x00dev,
- libconf->conf->antenna_sel_tx,
- libconf->conf->antenna_sel_rx);
- if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
- rt2500usb_config_duration(rt2x00dev, libconf);
-}
-
-/*
- * LED functions.
- */
-static void rt2500usb_enable_led(struct rt2x00_dev *rt2x00dev)
-{
- u16 reg;
-
- rt2500usb_register_read(rt2x00dev, MAC_CSR21, ®);
- rt2x00_set_field16(®, MAC_CSR21_ON_PERIOD, 70);
- rt2x00_set_field16(®, MAC_CSR21_OFF_PERIOD, 30);
- rt2500usb_register_write(rt2x00dev, MAC_CSR21, reg);
-
- rt2500usb_register_read(rt2x00dev, MAC_CSR20, ®);
-
- if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
- rt2x00_set_field16(®, MAC_CSR20_LINK, 1);
- rt2x00_set_field16(®, MAC_CSR20_ACTIVITY, 0);
- } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
- rt2x00_set_field16(®, MAC_CSR20_LINK, 0);
- rt2x00_set_field16(®, MAC_CSR20_ACTIVITY, 1);
- } else {
- rt2x00_set_field16(®, MAC_CSR20_LINK, 1);
- rt2x00_set_field16(®, MAC_CSR20_ACTIVITY, 1);
- }
-
- rt2500usb_register_write(rt2x00dev, MAC_CSR20, reg);
-}
-
-static void rt2500usb_disable_led(struct rt2x00_dev *rt2x00dev)
-{
- u16 reg;
-
- rt2500usb_register_read(rt2x00dev, MAC_CSR20, ®);
- rt2x00_set_field16(®, MAC_CSR20_LINK, 0);
- rt2x00_set_field16(®, MAC_CSR20_ACTIVITY, 0);
- rt2500usb_register_write(rt2x00dev, MAC_CSR20, reg);
-}
-
-/*
- * Link tuning
- */
-static void rt2500usb_link_stats(struct rt2x00_dev *rt2x00dev)
-{
- u16 reg;
-
- /*
- * Update FCS error count from register.
- */
- rt2500usb_register_read(rt2x00dev, STA_CSR0, ®);
- rt2x00dev->link.rx_failed = rt2x00_get_field16(reg, STA_CSR0_FCS_ERROR);
-
- /*
- * Update False CCA count from register.
- */
- rt2500usb_register_read(rt2x00dev, STA_CSR3, ®);
- rt2x00dev->link.false_cca =
- rt2x00_get_field16(reg, STA_CSR3_FALSE_CCA_ERROR);
-}
-
-static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
-{
- u16 eeprom;
- u16 value;
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &eeprom);
- value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R24_LOW);
- rt2500usb_bbp_write(rt2x00dev, 24, value);
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &eeprom);
- value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R25_LOW);
- rt2500usb_bbp_write(rt2x00dev, 25, value);
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &eeprom);
- value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R61_LOW);
- rt2500usb_bbp_write(rt2x00dev, 61, value);
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &eeprom);
- value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_VGCUPPER);
- rt2500usb_bbp_write(rt2x00dev, 17, value);
-
- rt2x00dev->link.vgc_level = value;
-}
-
-static void rt2500usb_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
- int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
- u16 bbp_thresh;
- u16 vgc_bound;
- u16 sens;
- u16 r24;
- u16 r25;
- u16 r61;
- u16 r17_sens;
- u8 r17;
- u8 up_bound;
- u8 low_bound;
-
- /*
- * Determine the BBP tuning threshold and correctly
- * set BBP 24, 25 and 61.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE, &bbp_thresh);
- bbp_thresh = rt2x00_get_field16(bbp_thresh, EEPROM_BBPTUNE_THRESHOLD);
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &r24);
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &r25);
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &r61);
-
- if ((rssi + bbp_thresh) > 0) {
- r24 = rt2x00_get_field16(r24, EEPROM_BBPTUNE_R24_HIGH);
- r25 = rt2x00_get_field16(r25, EEPROM_BBPTUNE_R25_HIGH);
- r61 = rt2x00_get_field16(r61, EEPROM_BBPTUNE_R61_HIGH);
- } else {
- r24 = rt2x00_get_field16(r24, EEPROM_BBPTUNE_R24_LOW);
- r25 = rt2x00_get_field16(r25, EEPROM_BBPTUNE_R25_LOW);
- r61 = rt2x00_get_field16(r61, EEPROM_BBPTUNE_R61_LOW);
- }
-
- rt2500usb_bbp_write(rt2x00dev, 24, r24);
- rt2500usb_bbp_write(rt2x00dev, 25, r25);
- rt2500usb_bbp_write(rt2x00dev, 61, r61);
-
- /*
- * Read current r17 value, as well as the sensitivity values
- * for the r17 register.
- */
- rt2500usb_bbp_read(rt2x00dev, 17, &r17);
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &r17_sens);
-
- /*
- * A too low RSSI will cause too much false CCA which will
- * then corrupt the R17 tuning. To remidy this the tuning should
- * be stopped (While making sure the R17 value will not exceed limits)
- */
- if (rssi >= -40) {
- if (r17 != 0x60)
- rt2500usb_bbp_write(rt2x00dev, 17, 0x60);
- return;
- }
-
- /*
- * Special big-R17 for short distance
- */
- if (rssi >= -58) {
- sens = rt2x00_get_field16(r17_sens, EEPROM_BBPTUNE_R17_LOW);
- if (r17 != sens)
- rt2500usb_bbp_write(rt2x00dev, 17, sens);
- return;
- }
-
- /*
- * Special mid-R17 for middle distance
- */
- if (rssi >= -74) {
- sens = rt2x00_get_field16(r17_sens, EEPROM_BBPTUNE_R17_HIGH);
- if (r17 != sens)
- rt2500usb_bbp_write(rt2x00dev, 17, sens);
- return;
- }
-
- /*
- * Leave short or middle distance condition, restore r17
- * to the dynamic tuning range.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &vgc_bound);
- vgc_bound = rt2x00_get_field16(vgc_bound, EEPROM_BBPTUNE_VGCUPPER);
-
- low_bound = 0x32;
- if (rssi >= -77)
- up_bound = vgc_bound;
- else
- up_bound = vgc_bound - (-77 - rssi);
-
- if (up_bound < low_bound)
- up_bound = low_bound;
-
- if (r17 > up_bound) {
- rt2500usb_bbp_write(rt2x00dev, 17, up_bound);
- rt2x00dev->link.vgc_level = up_bound;
- } else if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
- rt2500usb_bbp_write(rt2x00dev, 17, ++r17);
- rt2x00dev->link.vgc_level = r17;
- } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
- rt2500usb_bbp_write(rt2x00dev, 17, --r17);
- rt2x00dev->link.vgc_level = r17;
- }
-}
-
-/*
- * Initialization functions.
- */
-static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
-{
- u16 reg;
-
- rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0x0001,
- USB_MODE_TEST, REGISTER_TIMEOUT);
- rt2x00usb_vendor_request_sw(rt2x00dev, USB_SINGLE_WRITE, 0x0308,
- 0x00f0, REGISTER_TIMEOUT);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR2, ®);
- rt2x00_set_field16(®, TXRX_CSR2_DISABLE_RX, 1);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
-
- rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x1111);
- rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x1e11);
-
- rt2500usb_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field16(®, MAC_CSR1_SOFT_RESET, 1);
- rt2x00_set_field16(®, MAC_CSR1_BBP_RESET, 1);
- rt2x00_set_field16(®, MAC_CSR1_HOST_READY, 0);
- rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
-
- rt2500usb_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field16(®, MAC_CSR1_SOFT_RESET, 0);
- rt2x00_set_field16(®, MAC_CSR1_BBP_RESET, 0);
- rt2x00_set_field16(®, MAC_CSR1_HOST_READY, 0);
- rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR5, ®);
- rt2x00_set_field16(®, TXRX_CSR5_BBP_ID0, 13);
- rt2x00_set_field16(®, TXRX_CSR5_BBP_ID0_VALID, 1);
- rt2x00_set_field16(®, TXRX_CSR5_BBP_ID1, 12);
- rt2x00_set_field16(®, TXRX_CSR5_BBP_ID1_VALID, 1);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR5, reg);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR6, ®);
- rt2x00_set_field16(®, TXRX_CSR6_BBP_ID0, 10);
- rt2x00_set_field16(®, TXRX_CSR6_BBP_ID0_VALID, 1);
- rt2x00_set_field16(®, TXRX_CSR6_BBP_ID1, 11);
- rt2x00_set_field16(®, TXRX_CSR6_BBP_ID1_VALID, 1);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR6, reg);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR7, ®);
- rt2x00_set_field16(®, TXRX_CSR7_BBP_ID0, 7);
- rt2x00_set_field16(®, TXRX_CSR7_BBP_ID0_VALID, 1);
- rt2x00_set_field16(®, TXRX_CSR7_BBP_ID1, 6);
- rt2x00_set_field16(®, TXRX_CSR7_BBP_ID1_VALID, 1);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR7, reg);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR8, ®);
- rt2x00_set_field16(®, TXRX_CSR8_BBP_ID0, 5);
- rt2x00_set_field16(®, TXRX_CSR8_BBP_ID0_VALID, 1);
- rt2x00_set_field16(®, TXRX_CSR8_BBP_ID1, 0);
- rt2x00_set_field16(®, TXRX_CSR8_BBP_ID1_VALID, 0);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR8, reg);
-
- rt2500usb_register_write(rt2x00dev, TXRX_CSR21, 0xe78f);
- rt2500usb_register_write(rt2x00dev, MAC_CSR9, 0xff1d);
-
- if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
- return -EBUSY;
-
- rt2500usb_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field16(®, MAC_CSR1_SOFT_RESET, 0);
- rt2x00_set_field16(®, MAC_CSR1_BBP_RESET, 0);
- rt2x00_set_field16(®, MAC_CSR1_HOST_READY, 1);
- rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
-
- if (rt2x00_rev(&rt2x00dev->chip) >= RT2570_VERSION_C) {
- rt2500usb_register_read(rt2x00dev, PHY_CSR2, ®);
- reg &= ~0x0002;
- } else {
- reg = 0x3002;
- }
- rt2500usb_register_write(rt2x00dev, PHY_CSR2, reg);
-
- rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x0002);
- rt2500usb_register_write(rt2x00dev, MAC_CSR22, 0x0053);
- rt2500usb_register_write(rt2x00dev, MAC_CSR15, 0x01ee);
- rt2500usb_register_write(rt2x00dev, MAC_CSR16, 0x0000);
-
- rt2500usb_register_read(rt2x00dev, MAC_CSR8, ®);
- rt2x00_set_field16(®, MAC_CSR8_MAX_FRAME_UNIT,
- rt2x00dev->rx->data_size);
- rt2500usb_register_write(rt2x00dev, MAC_CSR8, reg);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field16(®, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
- rt2x00_set_field16(®, TXRX_CSR0_KEY_ID, 0xff);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
-
- rt2500usb_register_read(rt2x00dev, MAC_CSR18, ®);
- rt2x00_set_field16(®, MAC_CSR18_DELAY_AFTER_BEACON, 90);
- rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
-
- rt2500usb_register_read(rt2x00dev, PHY_CSR4, ®);
- rt2x00_set_field16(®, PHY_CSR4_LOW_RF_LE, 1);
- rt2500usb_register_write(rt2x00dev, PHY_CSR4, reg);
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR1, ®);
- rt2x00_set_field16(®, TXRX_CSR1_AUTO_SEQUENCE, 1);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg);
-
- return 0;
-}
-
-static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev)
-{
- unsigned int i;
- u16 eeprom;
- u8 value;
- u8 reg_id;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2500usb_bbp_read(rt2x00dev, 0, &value);
- if ((value != 0xff) && (value != 0x00))
- goto continue_csr_init;
- NOTICE(rt2x00dev, "Waiting for BBP register.\n");
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
- return -EACCES;
-
-continue_csr_init:
- rt2500usb_bbp_write(rt2x00dev, 3, 0x02);
- rt2500usb_bbp_write(rt2x00dev, 4, 0x19);
- rt2500usb_bbp_write(rt2x00dev, 14, 0x1c);
- rt2500usb_bbp_write(rt2x00dev, 15, 0x30);
- rt2500usb_bbp_write(rt2x00dev, 16, 0xac);
- rt2500usb_bbp_write(rt2x00dev, 18, 0x18);
- rt2500usb_bbp_write(rt2x00dev, 19, 0xff);
- rt2500usb_bbp_write(rt2x00dev, 20, 0x1e);
- rt2500usb_bbp_write(rt2x00dev, 21, 0x08);
- rt2500usb_bbp_write(rt2x00dev, 22, 0x08);
- rt2500usb_bbp_write(rt2x00dev, 23, 0x08);
- rt2500usb_bbp_write(rt2x00dev, 24, 0x80);
- rt2500usb_bbp_write(rt2x00dev, 25, 0x50);
- rt2500usb_bbp_write(rt2x00dev, 26, 0x08);
- rt2500usb_bbp_write(rt2x00dev, 27, 0x23);
- rt2500usb_bbp_write(rt2x00dev, 30, 0x10);
- rt2500usb_bbp_write(rt2x00dev, 31, 0x2b);
- rt2500usb_bbp_write(rt2x00dev, 32, 0xb9);
- rt2500usb_bbp_write(rt2x00dev, 34, 0x12);
- rt2500usb_bbp_write(rt2x00dev, 35, 0x50);
- rt2500usb_bbp_write(rt2x00dev, 39, 0xc4);
- rt2500usb_bbp_write(rt2x00dev, 40, 0x02);
- rt2500usb_bbp_write(rt2x00dev, 41, 0x60);
- rt2500usb_bbp_write(rt2x00dev, 53, 0x10);
- rt2500usb_bbp_write(rt2x00dev, 54, 0x18);
- rt2500usb_bbp_write(rt2x00dev, 56, 0x08);
- rt2500usb_bbp_write(rt2x00dev, 57, 0x10);
- rt2500usb_bbp_write(rt2x00dev, 58, 0x08);
- rt2500usb_bbp_write(rt2x00dev, 61, 0x60);
- rt2500usb_bbp_write(rt2x00dev, 62, 0x10);
- rt2500usb_bbp_write(rt2x00dev, 75, 0xff);
-
- DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
- for (i = 0; i < EEPROM_BBP_SIZE; i++) {
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
-
- if (eeprom != 0xffff && eeprom != 0x0000) {
- reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
- value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
- DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
- reg_id, value);
- rt2500usb_bbp_write(rt2x00dev, reg_id, value);
- }
- }
- DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
-
- return 0;
-}
-
-/*
- * Device state switch handlers.
- */
-static void rt2500usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- u16 reg;
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR2, ®);
- rt2x00_set_field16(®, TXRX_CSR2_DISABLE_RX,
- state == STATE_RADIO_RX_OFF);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
-}
-
-static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
- /*
- * Initialize all registers.
- */
- if (rt2500usb_init_registers(rt2x00dev) ||
- rt2500usb_init_bbp(rt2x00dev)) {
- ERROR(rt2x00dev, "Register initialization failed.\n");
- return -EIO;
- }
-
- rt2x00usb_enable_radio(rt2x00dev);
-
- /*
- * Enable LED
- */
- rt2500usb_enable_led(rt2x00dev);
-
- return 0;
-}
-
-static void rt2500usb_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
- /*
- * Disable LED
- */
- rt2500usb_disable_led(rt2x00dev);
-
- rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x2121);
- rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x2121);
-
- /*
- * Disable synchronisation.
- */
- rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
-
- rt2x00usb_disable_radio(rt2x00dev);
-}
-
-static int rt2500usb_set_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- u16 reg;
- u16 reg2;
- unsigned int i;
- char put_to_sleep;
- char bbp_state;
- char rf_state;
-
- put_to_sleep = (state != STATE_AWAKE);
-
- reg = 0;
- rt2x00_set_field16(®, MAC_CSR17_BBP_DESIRE_STATE, state);
- rt2x00_set_field16(®, MAC_CSR17_RF_DESIRE_STATE, state);
- rt2x00_set_field16(®, MAC_CSR17_PUT_TO_SLEEP, put_to_sleep);
- rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
- rt2x00_set_field16(®, MAC_CSR17_SET_STATE, 1);
- rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
-
- /*
- * Device is not guaranteed to be in the requested state yet.
- * We must wait until the register indicates that the
- * device has entered the correct state.
- */
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2500usb_register_read(rt2x00dev, MAC_CSR17, ®2);
- bbp_state = rt2x00_get_field16(reg2, MAC_CSR17_BBP_CURR_STATE);
- rf_state = rt2x00_get_field16(reg2, MAC_CSR17_RF_CURR_STATE);
- if (bbp_state == state && rf_state == state)
- return 0;
- rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
- msleep(30);
- }
-
- NOTICE(rt2x00dev, "Device failed to enter state %d, "
- "current device state: bbp %d and rf %d.\n",
- state, bbp_state, rf_state);
-
- return -EBUSY;
-}
-
-static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- int retval = 0;
-
- switch (state) {
- case STATE_RADIO_ON:
- retval = rt2500usb_enable_radio(rt2x00dev);
- break;
- case STATE_RADIO_OFF:
- rt2500usb_disable_radio(rt2x00dev);
- break;
- case STATE_RADIO_RX_ON:
- case STATE_RADIO_RX_OFF:
- rt2500usb_toggle_rx(rt2x00dev, state);
- break;
- case STATE_DEEP_SLEEP:
- case STATE_SLEEP:
- case STATE_STANDBY:
- case STATE_AWAKE:
- retval = rt2500usb_set_state(rt2x00dev, state);
- break;
- default:
- retval = -ENOTSUPP;
- break;
- }
-
- return retval;
-}
-
-/*
- * TX descriptor initialization
- */
-static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
- struct data_desc *txd,
- struct txdata_entry_desc *desc,
- struct ieee80211_hdr *ieee80211hdr,
- unsigned int length,
- struct ieee80211_tx_control *control)
-{
- u32 word;
-
- /*
- * Start writing the descriptor words.
- */
- rt2x00_desc_read(txd, 1, &word);
- rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
- rt2x00_set_field32(&word, TXD_W1_AIFS, desc->aifs);
- rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
- rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
- rt2x00_desc_write(txd, 1, word);
-
- rt2x00_desc_read(txd, 2, &word);
- rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
- rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
- rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
- rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
- rt2x00_desc_write(txd, 2, word);
-
- rt2x00_desc_read(txd, 0, &word);
- rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, control->retry_limit);
- rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
- test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_ACK,
- !(control->flags & IEEE80211_TXCTL_NO_ACK));
- rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
- test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_OFDM,
- test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
- !!(control->flags & IEEE80211_TXCTL_FIRST_FRAGMENT));
- rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
- rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
- rt2x00_set_field32(&word, TXD_W0_CIPHER, CIPHER_NONE);
- rt2x00_desc_write(txd, 0, word);
-}
-
-static int rt2500usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
- struct sk_buff *skb)
-{
- int length;
-
- /*
- * The length _must_ be a multiple of 2,
- * but it must _not_ be a multiple of the USB packet size.
- */
- length = roundup(skb->len, 2);
- length += (2 * !(length % rt2x00dev->usb_maxpacket));
-
- return length;
-}
-
-/*
- * TX data initialization
- */
-static void rt2500usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
- unsigned int queue)
-{
- u16 reg;
-
- if (queue != IEEE80211_TX_QUEUE_BEACON)
- return;
-
- rt2500usb_register_read(rt2x00dev, TXRX_CSR19, ®);
- if (!rt2x00_get_field16(reg, TXRX_CSR19_BEACON_GEN)) {
- rt2x00_set_field16(®, TXRX_CSR19_BEACON_GEN, 1);
- /*
- * Beacon generation will fail initially.
- * To prevent this we need to register the TXRX_CSR19
- * register several times.
- */
- rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
- }
-}
-
-/*
- * RX control handlers
- */
-static void rt2500usb_fill_rxdone(struct data_entry *entry,
- struct rxdata_entry_desc *desc)
-{
- struct urb *urb = entry->priv;
- struct data_desc *rxd = (struct data_desc *)(entry->skb->data +
- (urb->actual_length -
- entry->ring->desc_size));
- u32 word0;
- u32 word1;
-
- rt2x00_desc_read(rxd, 0, &word0);
- rt2x00_desc_read(rxd, 1, &word1);
-
- desc->flags = 0;
- if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
- desc->flags |= RX_FLAG_FAILED_FCS_CRC;
- if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
- desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
-
- /*
- * Obtain the status about this packet.
- */
- desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
- desc->rssi = rt2x00_get_field32(word1, RXD_W1_RSSI) -
- entry->ring->rt2x00dev->rssi_offset;
- desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
- desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
-
- return;
-}
-
-/*
- * Interrupt functions.
- */
-static void rt2500usb_beacondone(struct urb *urb)
-{
- struct data_entry *entry = (struct data_entry *)urb->context;
- struct data_ring *ring = entry->ring;
-
- if (!test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags))
- return;
-
- /*
- * Check if this was the guardian beacon,
- * if that was the case we need to send the real beacon now.
- * Otherwise we should free the sk_buffer, the device
- * should be doing the rest of the work now.
- */
- if (ring->index == 1) {
- rt2x00_ring_index_done_inc(ring);
- entry = rt2x00_get_data_entry(ring);
- usb_submit_urb(entry->priv, GFP_ATOMIC);
- rt2x00_ring_index_inc(ring);
- } else if (ring->index_done == 1) {
- entry = rt2x00_get_data_entry_done(ring);
- if (entry->skb) {
- dev_kfree_skb(entry->skb);
- entry->skb = NULL;
- }
- rt2x00_ring_index_done_inc(ring);
- }
-}
-
-/*
- * Device probe functions.
- */
-static int rt2500usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- u16 word;
- u8 *mac;
-
- rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
-
- /*
- * Start validation of the data that has been read.
- */
- mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
- if (!is_valid_ether_addr(mac)) {
- DECLARE_MAC_BUF(macbuf);
-
- random_ether_addr(mac);
- EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
- EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
- rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
- rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
- EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
- DEFAULT_RSSI_OFFSET);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
- EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_THRESHOLD, 45);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE, word);
- EEPROM(rt2x00dev, "BBPtune: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCUPPER, 0x40);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
- EEPROM(rt2x00dev, "BBPtune vgc: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_LOW, 0x48);
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_HIGH, 0x41);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R17, word);
- EEPROM(rt2x00dev, "BBPtune r17: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_LOW, 0x40);
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_HIGH, 0x80);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R24, word);
- EEPROM(rt2x00dev, "BBPtune r24: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_LOW, 0x40);
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_HIGH, 0x50);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R25, word);
- EEPROM(rt2x00dev, "BBPtune r25: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_LOW, 0x60);
- rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_HIGH, 0x6d);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R61, word);
- EEPROM(rt2x00dev, "BBPtune r61: 0x%04x\n", word);
- }
-
- return 0;
-}
-
-static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- u16 reg;
- u16 value;
- u16 eeprom;
-
- /*
- * Read EEPROM word for configuration.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-
- /*
- * Identify RF chipset.
- */
- value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
- rt2500usb_register_read(rt2x00dev, MAC_CSR0, ®);
- rt2x00_set_chip(rt2x00dev, RT2570, value, reg);
-
- if (!rt2x00_check_rev(&rt2x00dev->chip, 0)) {
- ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
- return -ENODEV;
- }
-
- if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
- !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
- ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
- return -ENODEV;
- }
-
- /*
- * Identify default antenna configuration.
- */
- rt2x00dev->hw->conf.antenna_sel_tx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
- rt2x00dev->hw->conf.antenna_sel_rx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
-
- /*
- * Store led mode, for correct led behaviour.
- */
- rt2x00dev->led_mode =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
-
- /*
- * Check if the BBP tuning should be disabled.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
- if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
- __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
-
- /*
- * Read the RSSI <-> dBm offset information.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
- rt2x00dev->rssi_offset =
- rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
-
- return 0;
-}
-
-/*
- * RF value list for RF2522
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2522[] = {
- { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
- { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
- { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
- { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
- { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
- { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
- { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
- { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
- { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
- { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
- { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
- { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
- { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
- { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
-};
-
-/*
- * RF value list for RF2523
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2523[] = {
- { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
- { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
- { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
- { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
- { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
- { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
- { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
- { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
- { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
- { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
- { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
- { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
- { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
- { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2524
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2524[] = {
- { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
- { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
- { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
- { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
- { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
- { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
- { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
- { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
- { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
- { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
- { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
- { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
- { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
- { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2525
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2525[] = {
- { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
- { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
- { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
- { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
- { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
- { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
- { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
- { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
- { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
- { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
- { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
- { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
- { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
- { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2525e
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2525e[] = {
- { 1, 0x00022010, 0x0000089a, 0x00060111, 0x00000e1b },
- { 2, 0x00022010, 0x0000089e, 0x00060111, 0x00000e07 },
- { 3, 0x00022010, 0x0000089e, 0x00060111, 0x00000e1b },
- { 4, 0x00022010, 0x000008a2, 0x00060111, 0x00000e07 },
- { 5, 0x00022010, 0x000008a2, 0x00060111, 0x00000e1b },
- { 6, 0x00022010, 0x000008a6, 0x00060111, 0x00000e07 },
- { 7, 0x00022010, 0x000008a6, 0x00060111, 0x00000e1b },
- { 8, 0x00022010, 0x000008aa, 0x00060111, 0x00000e07 },
- { 9, 0x00022010, 0x000008aa, 0x00060111, 0x00000e1b },
- { 10, 0x00022010, 0x000008ae, 0x00060111, 0x00000e07 },
- { 11, 0x00022010, 0x000008ae, 0x00060111, 0x00000e1b },
- { 12, 0x00022010, 0x000008b2, 0x00060111, 0x00000e07 },
- { 13, 0x00022010, 0x000008b2, 0x00060111, 0x00000e1b },
- { 14, 0x00022010, 0x000008b6, 0x00060111, 0x00000e23 },
-};
-
-/*
- * RF value list for RF5222
- * Supports: 2.4 GHz & 5.2 GHz
- */
-static const struct rf_channel rf_vals_5222[] = {
- { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
- { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
- { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
- { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
- { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
- { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
- { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
- { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
- { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
- { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
- { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
- { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
- { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
- { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
-
- /* 802.11 UNI / HyperLan 2 */
- { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
- { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
- { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
- { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
- { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
- { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
- { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
- { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
-
- /* 802.11 HyperLan 2 */
- { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
- { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
- { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
- { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
- { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
- { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
- { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
- { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
- { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
- { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
-
- /* 802.11 UNII */
- { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
- { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
- { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
- { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
- { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
-};
-
-static void rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
-{
- struct hw_mode_spec *spec = &rt2x00dev->spec;
- u8 *txpower;
- unsigned int i;
-
- /*
- * Initialize all hw fields.
- */
- rt2x00dev->hw->flags =
- IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
- IEEE80211_HW_RX_INCLUDES_FCS |
- IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
- rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
- rt2x00dev->hw->max_signal = MAX_SIGNAL;
- rt2x00dev->hw->max_rssi = MAX_RX_SSI;
- rt2x00dev->hw->queues = 2;
-
- SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
- SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
- rt2x00_eeprom_addr(rt2x00dev,
- EEPROM_MAC_ADDR_0));
-
- /*
- * Convert tx_power array in eeprom.
- */
- txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
- for (i = 0; i < 14; i++)
- txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
- /*
- * Initialize hw_mode information.
- */
- spec->num_modes = 2;
- spec->num_rates = 12;
- spec->tx_power_a = NULL;
- spec->tx_power_bg = txpower;
- spec->tx_power_default = DEFAULT_TXPOWER;
-
- if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
- spec->channels = rf_vals_bg_2522;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
- spec->channels = rf_vals_bg_2523;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
- spec->channels = rf_vals_bg_2524;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
- spec->channels = rf_vals_bg_2525;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
- spec->channels = rf_vals_bg_2525e;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_5222);
- spec->channels = rf_vals_5222;
- spec->num_modes = 3;
- }
-}
-
-static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
-{
- int retval;
-
- /*
- * Allocate eeprom data.
- */
- retval = rt2500usb_validate_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- retval = rt2500usb_init_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- /*
- * Initialize hw specifications.
- */
- rt2500usb_probe_hw_mode(rt2x00dev);
-
- /*
- * This device requires the beacon ring
- */
- __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
-
- /*
- * Set the rssi offset.
- */
- rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
-
- return 0;
-}
-
-/*
- * IEEE80211 stack callback functions.
- */
-static void rt2500usb_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed_flags,
- unsigned int *total_flags,
- int mc_count,
- struct dev_addr_list *mc_list)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct interface *intf = &rt2x00dev->interface;
- u16 reg;
-
- /*
- * Mask off any flags we are going to ignore from
- * the total_flags field.
- */
- *total_flags &=
- FIF_ALLMULTI |
- FIF_FCSFAIL |
- FIF_PLCPFAIL |
- FIF_CONTROL |
- FIF_OTHER_BSS |
- FIF_PROMISC_IN_BSS;
-
- /*
- * Apply some rules to the filters:
- * - Some filters imply different filters to be set.
- * - Some things we can't filter out at all.
- * - Some filters are set based on interface type.
- */
- if (mc_count)
- *total_flags |= FIF_ALLMULTI;
- if (*total_flags & FIF_OTHER_BSS ||
- *total_flags & FIF_PROMISC_IN_BSS)
- *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
- if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
- *total_flags |= FIF_PROMISC_IN_BSS;
-
- /*
- * Check if there is any work left for us.
- */
- if (intf->filter == *total_flags)
- return;
- intf->filter = *total_flags;
-
- /*
- * When in atomic context, reschedule and let rt2x00lib
- * call this function again.
- */
- if (in_atomic()) {
- queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
- return;
- }
-
- /*
- * Start configuration steps.
- * Note that the version error will always be dropped
- * and broadcast frames will always be accepted since
- * there is no filter for it at this time.
- */
- rt2500usb_register_read(rt2x00dev, TXRX_CSR2, ®);
- rt2x00_set_field16(®, TXRX_CSR2_DROP_CRC,
- !(*total_flags & FIF_FCSFAIL));
- rt2x00_set_field16(®, TXRX_CSR2_DROP_PHYSICAL,
- !(*total_flags & FIF_PLCPFAIL));
- rt2x00_set_field16(®, TXRX_CSR2_DROP_CONTROL,
- !(*total_flags & FIF_CONTROL));
- rt2x00_set_field16(®, TXRX_CSR2_DROP_NOT_TO_ME,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field16(®, TXRX_CSR2_DROP_TODS,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field16(®, TXRX_CSR2_DROP_VERSION_ERROR, 1);
- rt2x00_set_field16(®, TXRX_CSR2_DROP_MULTICAST,
- !(*total_flags & FIF_ALLMULTI));
- rt2x00_set_field16(®, TXRX_CSR2_DROP_BROADCAST, 0);
- rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
-}
-
-static int rt2500usb_beacon_update(struct ieee80211_hw *hw,
- struct sk_buff *skb,
- struct ieee80211_tx_control *control)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct usb_device *usb_dev =
- interface_to_usbdev(rt2x00dev_usb(rt2x00dev));
- struct data_ring *ring =
- rt2x00lib_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
- struct data_entry *beacon;
- struct data_entry *guardian;
- int pipe = usb_sndbulkpipe(usb_dev, 1);
- int length;
-
- /*
- * Just in case the ieee80211 doesn't set this,
- * but we need this queue set for the descriptor
- * initialization.
- */
- control->queue = IEEE80211_TX_QUEUE_BEACON;
-
- /*
- * Obtain 2 entries, one for the guardian byte,
- * the second for the actual beacon.
- */
- guardian = rt2x00_get_data_entry(ring);
- rt2x00_ring_index_inc(ring);
- beacon = rt2x00_get_data_entry(ring);
-
- /*
- * First we create the beacon.
- */
- skb_push(skb, ring->desc_size);
- memset(skb->data, 0, ring->desc_size);
-
- rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
- (struct ieee80211_hdr *)(skb->data +
- ring->desc_size),
- skb->len - ring->desc_size, control);
-
- length = rt2500usb_get_tx_data_len(rt2x00dev, skb);
-
- usb_fill_bulk_urb(beacon->priv, usb_dev, pipe,
- skb->data, length, rt2500usb_beacondone, beacon);
-
- beacon->skb = skb;
-
- /*
- * Second we need to create the guardian byte.
- * We only need a single byte, so lets recycle
- * the 'flags' field we are not using for beacons.
- */
- guardian->flags = 0;
- usb_fill_bulk_urb(guardian->priv, usb_dev, pipe,
- &guardian->flags, 1, rt2500usb_beacondone, guardian);
-
- /*
- * Send out the guardian byte.
- */
- usb_submit_urb(guardian->priv, GFP_ATOMIC);
-
- /*
- * Enable beacon generation.
- */
- rt2500usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
-
- return 0;
-}
-
-static const struct ieee80211_ops rt2500usb_mac80211_ops = {
- .tx = rt2x00mac_tx,
- .start = rt2x00mac_start,
- .stop = rt2x00mac_stop,
- .add_interface = rt2x00mac_add_interface,
- .remove_interface = rt2x00mac_remove_interface,
- .config = rt2x00mac_config,
- .config_interface = rt2x00mac_config_interface,
- .configure_filter = rt2500usb_configure_filter,
- .get_stats = rt2x00mac_get_stats,
- .erp_ie_changed = rt2x00mac_erp_ie_changed,
- .conf_tx = rt2x00mac_conf_tx,
- .get_tx_stats = rt2x00mac_get_tx_stats,
- .beacon_update = rt2500usb_beacon_update,
-};
-
-static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
- .probe_hw = rt2500usb_probe_hw,
- .initialize = rt2x00usb_initialize,
- .uninitialize = rt2x00usb_uninitialize,
- .set_device_state = rt2500usb_set_device_state,
- .link_stats = rt2500usb_link_stats,
- .reset_tuner = rt2500usb_reset_tuner,
- .link_tuner = rt2500usb_link_tuner,
- .write_tx_desc = rt2500usb_write_tx_desc,
- .write_tx_data = rt2x00usb_write_tx_data,
- .get_tx_data_len = rt2500usb_get_tx_data_len,
- .kick_tx_queue = rt2500usb_kick_tx_queue,
- .fill_rxdone = rt2500usb_fill_rxdone,
- .config_mac_addr = rt2500usb_config_mac_addr,
- .config_bssid = rt2500usb_config_bssid,
- .config_type = rt2500usb_config_type,
- .config_preamble = rt2500usb_config_preamble,
- .config = rt2500usb_config,
-};
-
-static const struct rt2x00_ops rt2500usb_ops = {
- .name = DRV_NAME,
- .rxd_size = RXD_DESC_SIZE,
- .txd_size = TXD_DESC_SIZE,
- .eeprom_size = EEPROM_SIZE,
- .rf_size = RF_SIZE,
- .lib = &rt2500usb_rt2x00_ops,
- .hw = &rt2500usb_mac80211_ops,
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
- .debugfs = &rt2500usb_rt2x00debug,
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-};
-
-/*
- * rt2500usb module information.
- */
-static struct usb_device_id rt2500usb_device_table[] = {
- /* ASUS */
- { USB_DEVICE(0x0b05, 0x1706), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x0b05, 0x1707), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Belkin */
- { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x050d, 0x7051), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Cisco Systems */
- { USB_DEVICE(0x13b1, 0x000d), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x13b1, 0x0011), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x13b1, 0x001a), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Conceptronic */
- { USB_DEVICE(0x14b2, 0x3c02), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* D-LINK */
- { USB_DEVICE(0x2001, 0x3c00), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Gigabyte */
- { USB_DEVICE(0x1044, 0x8001), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x1044, 0x8007), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Hercules */
- { USB_DEVICE(0x06f8, 0xe000), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Melco */
- { USB_DEVICE(0x0411, 0x0066), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x0411, 0x0067), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x0411, 0x008b), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x0411, 0x0097), USB_DEVICE_DATA(&rt2500usb_ops) },
-
- /* MSI */
- { USB_DEVICE(0x0db0, 0x6861), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x0db0, 0x6865), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x0db0, 0x6869), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Ralink */
- { USB_DEVICE(0x148f, 0x1706), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x148f, 0x2570), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt2500usb_ops) },
- { USB_DEVICE(0x148f, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Siemens */
- { USB_DEVICE(0x0681, 0x3c06), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* SMC */
- { USB_DEVICE(0x0707, 0xee13), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Spairon */
- { USB_DEVICE(0x114b, 0x0110), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Trust */
- { USB_DEVICE(0x0eb0, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) },
- /* Zinwell */
- { USB_DEVICE(0x5a57, 0x0260), USB_DEVICE_DATA(&rt2500usb_ops) },
- { 0, }
-};
-
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("Ralink RT2500 USB Wireless LAN driver.");
-MODULE_SUPPORTED_DEVICE("Ralink RT2570 USB chipset based cards");
-MODULE_DEVICE_TABLE(usb, rt2500usb_device_table);
-MODULE_LICENSE("GPL");
-
-static struct usb_driver rt2500usb_driver = {
- .name = DRV_NAME,
- .id_table = rt2500usb_device_table,
- .probe = rt2x00usb_probe,
- .disconnect = rt2x00usb_disconnect,
- .suspend = rt2x00usb_suspend,
- .resume = rt2x00usb_resume,
-};
-
-static int __init rt2500usb_init(void)
-{
- return usb_register(&rt2500usb_driver);
-}
-
-static void __exit rt2500usb_exit(void)
-{
- usb_deregister(&rt2500usb_driver);
-}
-
-module_init(rt2500usb_init);
-module_exit(rt2500usb_exit);
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2500usb
- Abstract: Data structures and registers for the rt2500usb module.
- Supported chipsets: RT2570.
- */
-
-#ifndef RT2500USB_H
-#define RT2500USB_H
-
-/*
- * RF chip defines.
- */
-#define RF2522 0x0000
-#define RF2523 0x0001
-#define RF2524 0x0002
-#define RF2525 0x0003
-#define RF2525E 0x0005
-#define RF5222 0x0010
-
-/*
- * RT2570 version
- */
-#define RT2570_VERSION_B 2
-#define RT2570_VERSION_C 3
-#define RT2570_VERSION_D 4
-
-/*
- * Signal information.
- * Defaul offset is required for RSSI <-> dBm conversion.
- */
-#define MAX_SIGNAL 100
-#define MAX_RX_SSI -1
-#define DEFAULT_RSSI_OFFSET 120
-
-/*
- * Register layout information.
- */
-#define CSR_REG_BASE 0x0400
-#define CSR_REG_SIZE 0x0100
-#define EEPROM_BASE 0x0000
-#define EEPROM_SIZE 0x006a
-#define BBP_SIZE 0x0060
-#define RF_SIZE 0x0014
-
-/*
- * Control/Status Registers(CSR).
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * MAC_CSR0: ASIC revision number.
- */
-#define MAC_CSR0 0x0400
-
-/*
- * MAC_CSR1: System control.
- * SOFT_RESET: Software reset, 1: reset, 0: normal.
- * BBP_RESET: Hardware reset, 1: reset, 0, release.
- * HOST_READY: Host ready after initialization.
- */
-#define MAC_CSR1 0x0402
-#define MAC_CSR1_SOFT_RESET FIELD16(0x00000001)
-#define MAC_CSR1_BBP_RESET FIELD16(0x00000002)
-#define MAC_CSR1_HOST_READY FIELD16(0x00000004)
-
-/*
- * MAC_CSR2: STA MAC register 0.
- */
-#define MAC_CSR2 0x0404
-#define MAC_CSR2_BYTE0 FIELD16(0x00ff)
-#define MAC_CSR2_BYTE1 FIELD16(0xff00)
-
-/*
- * MAC_CSR3: STA MAC register 1.
- */
-#define MAC_CSR3 0x0406
-#define MAC_CSR3_BYTE2 FIELD16(0x00ff)
-#define MAC_CSR3_BYTE3 FIELD16(0xff00)
-
-/*
- * MAC_CSR4: STA MAC register 2.
- */
-#define MAC_CSR4 0X0408
-#define MAC_CSR4_BYTE4 FIELD16(0x00ff)
-#define MAC_CSR4_BYTE5 FIELD16(0xff00)
-
-/*
- * MAC_CSR5: BSSID register 0.
- */
-#define MAC_CSR5 0x040a
-#define MAC_CSR5_BYTE0 FIELD16(0x00ff)
-#define MAC_CSR5_BYTE1 FIELD16(0xff00)
-
-/*
- * MAC_CSR6: BSSID register 1.
- */
-#define MAC_CSR6 0x040c
-#define MAC_CSR6_BYTE2 FIELD16(0x00ff)
-#define MAC_CSR6_BYTE3 FIELD16(0xff00)
-
-/*
- * MAC_CSR7: BSSID register 2.
- */
-#define MAC_CSR7 0x040e
-#define MAC_CSR7_BYTE4 FIELD16(0x00ff)
-#define MAC_CSR7_BYTE5 FIELD16(0xff00)
-
-/*
- * MAC_CSR8: Max frame length.
- */
-#define MAC_CSR8 0x0410
-#define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff)
-
-/*
- * Misc MAC_CSR registers.
- * MAC_CSR9: Timer control.
- * MAC_CSR10: Slot time.
- * MAC_CSR11: IFS.
- * MAC_CSR12: EIFS.
- * MAC_CSR13: Power mode0.
- * MAC_CSR14: Power mode1.
- * MAC_CSR15: Power saving transition0
- * MAC_CSR16: Power saving transition1
- */
-#define MAC_CSR9 0x0412
-#define MAC_CSR10 0x0414
-#define MAC_CSR11 0x0416
-#define MAC_CSR12 0x0418
-#define MAC_CSR13 0x041a
-#define MAC_CSR14 0x041c
-#define MAC_CSR15 0x041e
-#define MAC_CSR16 0x0420
-
-/*
- * MAC_CSR17: Manual power control / status register.
- * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
- * SET_STATE: Set state. Write 1 to trigger, self cleared.
- * BBP_DESIRE_STATE: BBP desired state.
- * RF_DESIRE_STATE: RF desired state.
- * BBP_CURRENT_STATE: BBP current state.
- * RF_CURRENT_STATE: RF current state.
- * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
- */
-#define MAC_CSR17 0x0422
-#define MAC_CSR17_SET_STATE FIELD16(0x0001)
-#define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006)
-#define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018)
-#define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060)
-#define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180)
-#define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200)
-
-/*
- * MAC_CSR18: Wakeup timer register.
- * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
- * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
- * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
- */
-#define MAC_CSR18 0x0424
-#define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff)
-#define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
-#define MAC_CSR18_AUTO_WAKE FIELD16(0x8000)
-
-/*
- * MAC_CSR19: GPIO control register.
- */
-#define MAC_CSR19 0x0426
-
-/*
- * MAC_CSR20: LED control register.
- * ACTIVITY: 0: idle, 1: active.
- * LINK: 0: linkoff, 1: linkup.
- * ACTIVITY_POLARITY: 0: active low, 1: active high.
- */
-#define MAC_CSR20 0x0428
-#define MAC_CSR20_ACTIVITY FIELD16(0x0001)
-#define MAC_CSR20_LINK FIELD16(0x0002)
-#define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
-
-/*
- * MAC_CSR21: LED control register.
- * ON_PERIOD: On period, default 70ms.
- * OFF_PERIOD: Off period, default 30ms.
- */
-#define MAC_CSR21 0x042a
-#define MAC_CSR21_ON_PERIOD FIELD16(0x00ff)
-#define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
-
-/*
- * Collision window control register.
- */
-#define MAC_CSR22 0x042c
-
-/*
- * Transmit related CSRs.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * TXRX_CSR0: Security control register.
- */
-#define TXRX_CSR0 0x0440
-#define TXRX_CSR0_ALGORITHM FIELD16(0x0007)
-#define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8)
-#define TXRX_CSR0_KEY_ID FIELD16(0x1e00)
-
-/*
- * TXRX_CSR1: TX configuration.
- * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
- * TSF_OFFSET: TSF offset in MAC header.
- * AUTO_SEQUENCE: Let ASIC control frame sequence number.
- */
-#define TXRX_CSR1 0x0442
-#define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff)
-#define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00)
-#define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000)
-
-/*
- * TXRX_CSR2: RX control.
- * DISABLE_RX: Disable rx engine.
- * DROP_CRC: Drop crc error.
- * DROP_PHYSICAL: Drop physical error.
- * DROP_CONTROL: Drop control frame.
- * DROP_NOT_TO_ME: Drop not to me unicast frame.
- * DROP_TODS: Drop frame tods bit is true.
- * DROP_VERSION_ERROR: Drop version error frame.
- * DROP_MCAST: Drop multicast frames.
- * DROP_BCAST: Drop broadcast frames.
- */
-#define TXRX_CSR2 0x0444
-#define TXRX_CSR2_DISABLE_RX FIELD16(0x0001)
-#define TXRX_CSR2_DROP_CRC FIELD16(0x0002)
-#define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004)
-#define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008)
-#define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010)
-#define TXRX_CSR2_DROP_TODS FIELD16(0x0020)
-#define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040)
-#define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200)
-#define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400)
-
-/*
- * RX BBP ID registers
- * TXRX_CSR3: CCK RX BBP ID.
- * TXRX_CSR4: OFDM RX BBP ID.
- */
-#define TXRX_CSR3 0x0446
-#define TXRX_CSR4 0x0448
-
-/*
- * TXRX_CSR5: CCK TX BBP ID0.
- */
-#define TXRX_CSR5 0x044a
-#define TXRX_CSR5_BBP_ID0 FIELD16(0x007f)
-#define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080)
-#define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00)
-#define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000)
-
-/*
- * TXRX_CSR6: CCK TX BBP ID1.
- */
-#define TXRX_CSR6 0x044c
-#define TXRX_CSR6_BBP_ID0 FIELD16(0x007f)
-#define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080)
-#define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00)
-#define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000)
-
-/*
- * TXRX_CSR7: OFDM TX BBP ID0.
- */
-#define TXRX_CSR7 0x044e
-#define TXRX_CSR7_BBP_ID0 FIELD16(0x007f)
-#define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080)
-#define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00)
-#define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000)
-
-/*
- * TXRX_CSR5: OFDM TX BBP ID1.
- */
-#define TXRX_CSR8 0x0450
-#define TXRX_CSR8_BBP_ID0 FIELD16(0x007f)
-#define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080)
-#define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00)
-#define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000)
-
-/*
- * TXRX_CSR9: TX ACK time-out.
- */
-#define TXRX_CSR9 0x0452
-
-/*
- * TXRX_CSR10: Auto responder control.
- */
-#define TXRX_CSR10 0x0454
-#define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
-
-/*
- * TXRX_CSR11: Auto responder basic rate.
- */
-#define TXRX_CSR11 0x0456
-
-/*
- * ACK/CTS time registers.
- */
-#define TXRX_CSR12 0x0458
-#define TXRX_CSR13 0x045a
-#define TXRX_CSR14 0x045c
-#define TXRX_CSR15 0x045e
-#define TXRX_CSR16 0x0460
-#define TXRX_CSR17 0x0462
-
-/*
- * TXRX_CSR18: Synchronization control register.
- */
-#define TXRX_CSR18 0x0464
-#define TXRX_CSR18_OFFSET FIELD16(0x000f)
-#define TXRX_CSR18_INTERVAL FIELD16(0xfff0)
-
-/*
- * TXRX_CSR19: Synchronization control register.
- * TSF_COUNT: Enable TSF auto counting.
- * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
- * TBCN: Enable Tbcn with reload value.
- * BEACON_GEN: Enable beacon generator.
- */
-#define TXRX_CSR19 0x0466
-#define TXRX_CSR19_TSF_COUNT FIELD16(0x0001)
-#define TXRX_CSR19_TSF_SYNC FIELD16(0x0006)
-#define TXRX_CSR19_TBCN FIELD16(0x0008)
-#define TXRX_CSR19_BEACON_GEN FIELD16(0x0010)
-
-/*
- * TXRX_CSR20: Tx BEACON offset time control register.
- * OFFSET: In units of usec.
- * BCN_EXPECT_WINDOW: Default: 2^CWmin
- */
-#define TXRX_CSR20 0x0468
-#define TXRX_CSR20_OFFSET FIELD16(0x1fff)
-#define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000)
-
-/*
- * TXRX_CSR21
- */
-#define TXRX_CSR21 0x046a
-
-/*
- * Encryption related CSRs.
- *
- */
-
-/*
- * SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7
- */
-#define SEC_CSR0 0x0480
-#define SEC_CSR1 0x0482
-#define SEC_CSR2 0x0484
-#define SEC_CSR3 0x0486
-#define SEC_CSR4 0x0488
-#define SEC_CSR5 0x048a
-#define SEC_CSR6 0x048c
-#define SEC_CSR7 0x048e
-
-/*
- * SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7
- */
-#define SEC_CSR8 0x0490
-#define SEC_CSR9 0x0492
-#define SEC_CSR10 0x0494
-#define SEC_CSR11 0x0496
-#define SEC_CSR12 0x0498
-#define SEC_CSR13 0x049a
-#define SEC_CSR14 0x049c
-#define SEC_CSR15 0x049e
-
-/*
- * SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7
- */
-#define SEC_CSR16 0x04a0
-#define SEC_CSR17 0x04a2
-#define SEC_CSR18 0X04A4
-#define SEC_CSR19 0x04a6
-#define SEC_CSR20 0x04a8
-#define SEC_CSR21 0x04aa
-#define SEC_CSR22 0x04ac
-#define SEC_CSR23 0x04ae
-
-/*
- * SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7
- */
-#define SEC_CSR24 0x04b0
-#define SEC_CSR25 0x04b2
-#define SEC_CSR26 0x04b4
-#define SEC_CSR27 0x04b6
-#define SEC_CSR28 0x04b8
-#define SEC_CSR29 0x04ba
-#define SEC_CSR30 0x04bc
-#define SEC_CSR31 0x04be
-
-/*
- * PHY control registers.
- */
-
-/*
- * PHY_CSR0: RF switching timing control.
- */
-#define PHY_CSR0 0x04c0
-
-/*
- * PHY_CSR1: TX PA configuration.
- */
-#define PHY_CSR1 0x04c2
-
-/*
- * MAC configuration registers.
- * PHY_CSR2: TX MAC configuration.
- * PHY_CSR3: RX MAC configuration.
- */
-#define PHY_CSR2 0x04c4
-#define PHY_CSR3 0x04c6
-
-/*
- * PHY_CSR4: Interface configuration.
- */
-#define PHY_CSR4 0x04c8
-#define PHY_CSR4_LOW_RF_LE FIELD16(0x0001)
-
-/*
- * BBP pre-TX registers.
- * PHY_CSR5: BBP pre-TX CCK.
- */
-#define PHY_CSR5 0x04ca
-#define PHY_CSR5_CCK FIELD16(0x0003)
-#define PHY_CSR5_CCK_FLIP FIELD16(0x0004)
-
-/*
- * BBP pre-TX registers.
- * PHY_CSR6: BBP pre-TX OFDM.
- */
-#define PHY_CSR6 0x04cc
-#define PHY_CSR6_OFDM FIELD16(0x0003)
-#define PHY_CSR6_OFDM_FLIP FIELD16(0x0004)
-
-/*
- * PHY_CSR7: BBP access register 0.
- * BBP_DATA: BBP data.
- * BBP_REG_ID: BBP register ID.
- * BBP_READ_CONTROL: 0: write, 1: read.
- */
-#define PHY_CSR7 0x04ce
-#define PHY_CSR7_DATA FIELD16(0x00ff)
-#define PHY_CSR7_REG_ID FIELD16(0x7f00)
-#define PHY_CSR7_READ_CONTROL FIELD16(0x8000)
-
-/*
- * PHY_CSR8: BBP access register 1.
- * BBP_BUSY: ASIC is busy execute BBP programming.
- */
-#define PHY_CSR8 0x04d0
-#define PHY_CSR8_BUSY FIELD16(0x0001)
-
-/*
- * PHY_CSR9: RF access register.
- * RF_VALUE: Register value + id to program into rf/if.
- */
-#define PHY_CSR9 0x04d2
-#define PHY_CSR9_RF_VALUE FIELD16(0xffff)
-
-/*
- * PHY_CSR10: RF access register.
- * RF_VALUE: Register value + id to program into rf/if.
- * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
- * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
- * RF_PLL_LD: Rf pll_ld status.
- * RF_BUSY: 1: asic is busy execute rf programming.
- */
-#define PHY_CSR10 0x04d4
-#define PHY_CSR10_RF_VALUE FIELD16(0x00ff)
-#define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
-#define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000)
-#define PHY_CSR10_RF_PLL_LD FIELD16(0x4000)
-#define PHY_CSR10_RF_BUSY FIELD16(0x8000)
-
-/*
- * STA_CSR0: FCS error count.
- * FCS_ERROR: FCS error count, cleared when read.
- */
-#define STA_CSR0 0x04e0
-#define STA_CSR0_FCS_ERROR FIELD16(0xffff)
-
-/*
- * STA_CSR1: PLCP error count.
- */
-#define STA_CSR1 0x04e2
-
-/*
- * STA_CSR2: LONG error count.
- */
-#define STA_CSR2 0x04e4
-
-/*
- * STA_CSR3: CCA false alarm.
- * FALSE_CCA_ERROR: False CCA error count, cleared when read.
- */
-#define STA_CSR3 0x04e6
-#define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff)
-
-/*
- * STA_CSR4: RX FIFO overflow.
- */
-#define STA_CSR4 0x04e8
-
-/*
- * STA_CSR5: Beacon sent counter.
- */
-#define STA_CSR5 0x04ea
-
-/*
- * Statistics registers
- */
-#define STA_CSR6 0x04ec
-#define STA_CSR7 0x04ee
-#define STA_CSR8 0x04f0
-#define STA_CSR9 0x04f2
-#define STA_CSR10 0x04f4
-
-/*
- * BBP registers.
- * The wordsize of the BBP is 8 bits.
- */
-
-/*
- * R2: TX antenna control
- */
-#define BBP_R2_TX_ANTENNA FIELD8(0x03)
-#define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
-
-/*
- * R14: RX antenna control
- */
-#define BBP_R14_RX_ANTENNA FIELD8(0x03)
-#define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
-
-/*
- * RF registers.
- */
-
-/*
- * RF 1
- */
-#define RF1_TUNER FIELD32(0x00020000)
-
-/*
- * RF 3
- */
-#define RF3_TUNER FIELD32(0x00000100)
-#define RF3_TXPOWER FIELD32(0x00003e00)
-
-/*
- * EEPROM contents.
- */
-
-/*
- * HW MAC address.
- */
-#define EEPROM_MAC_ADDR_0 0x0002
-#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR1 0x0003
-#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR_2 0x0004
-#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
-
-/*
- * EEPROM antenna.
- * ANTENNA_NUM: Number of antenna's.
- * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
- * DYN_TXAGC: Dynamic TX AGC control.
- * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
- * RF_TYPE: Rf_type of this adapter.
- */
-#define EEPROM_ANTENNA 0x000b
-#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
-#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
-#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
-#define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
-#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
-#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
-#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
-
-/*
- * EEPROM NIC config.
- * CARDBUS_ACCEL: 0: enable, 1: disable.
- * DYN_BBP_TUNE: 0: enable, 1: disable.
- * CCK_TX_POWER: CCK TX power compensation.
- */
-#define EEPROM_NIC 0x000c
-#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
-#define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
-#define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
-
-/*
- * EEPROM geography.
- * GEO: Default geography setting for device.
- */
-#define EEPROM_GEOGRAPHY 0x000d
-#define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
-
-/*
- * EEPROM BBP.
- */
-#define EEPROM_BBP_START 0x000e
-#define EEPROM_BBP_SIZE 16
-#define EEPROM_BBP_VALUE FIELD16(0x00ff)
-#define EEPROM_BBP_REG_ID FIELD16(0xff00)
-
-/*
- * EEPROM TXPOWER
- */
-#define EEPROM_TXPOWER_START 0x001e
-#define EEPROM_TXPOWER_SIZE 7
-#define EEPROM_TXPOWER_1 FIELD16(0x00ff)
-#define EEPROM_TXPOWER_2 FIELD16(0xff00)
-
-/*
- * EEPROM Tuning threshold
- */
-#define EEPROM_BBPTUNE 0x0030
-#define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff)
-
-/*
- * EEPROM BBP R24 Tuning.
- */
-#define EEPROM_BBPTUNE_R24 0x0031
-#define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff)
-#define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00)
-
-/*
- * EEPROM BBP R25 Tuning.
- */
-#define EEPROM_BBPTUNE_R25 0x0032
-#define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff)
-#define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00)
-
-/*
- * EEPROM BBP R24 Tuning.
- */
-#define EEPROM_BBPTUNE_R61 0x0033
-#define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff)
-#define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00)
-
-/*
- * EEPROM BBP VGC Tuning.
- */
-#define EEPROM_BBPTUNE_VGC 0x0034
-#define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff)
-
-/*
- * EEPROM BBP R17 Tuning.
- */
-#define EEPROM_BBPTUNE_R17 0x0035
-#define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff)
-#define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00)
-
-/*
- * RSSI <-> dBm offset calibration
- */
-#define EEPROM_CALIBRATE_OFFSET 0x0036
-#define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
-
-/*
- * DMA descriptor defines.
- */
-#define TXD_DESC_SIZE ( 5 * sizeof(struct data_desc) )
-#define RXD_DESC_SIZE ( 4 * sizeof(struct data_desc) )
-
-/*
- * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
- */
-
-/*
- * Word0
- */
-#define TXD_W0_PACKET_ID FIELD32(0x0000000f)
-#define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
-#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
-#define TXD_W0_ACK FIELD32(0x00000200)
-#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
-#define TXD_W0_OFDM FIELD32(0x00000800)
-#define TXD_W0_NEW_SEQ FIELD32(0x00001000)
-#define TXD_W0_IFS FIELD32(0x00006000)
-#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
-#define TXD_W0_CIPHER FIELD32(0x20000000)
-#define TXD_W0_KEY_ID FIELD32(0xc0000000)
-
-/*
- * Word1
- */
-#define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
-#define TXD_W1_AIFS FIELD32(0x000000c0)
-#define TXD_W1_CWMIN FIELD32(0x00000f00)
-#define TXD_W1_CWMAX FIELD32(0x0000f000)
-
-/*
- * Word2: PLCP information
- */
-#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
-#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
-#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
-#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
-
-/*
- * Word3
- */
-#define TXD_W3_IV FIELD32(0xffffffff)
-
-/*
- * Word4
- */
-#define TXD_W4_EIV FIELD32(0xffffffff)
-
-/*
- * RX descriptor format for RX Ring.
- */
-
-/*
- * Word0
- */
-#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
-#define RXD_W0_MULTICAST FIELD32(0x00000004)
-#define RXD_W0_BROADCAST FIELD32(0x00000008)
-#define RXD_W0_MY_BSS FIELD32(0x00000010)
-#define RXD_W0_CRC_ERROR FIELD32(0x00000020)
-#define RXD_W0_OFDM FIELD32(0x00000040)
-#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
-#define RXD_W0_CIPHER FIELD32(0x00000100)
-#define RXD_W0_CIPHER_ERROR FIELD32(0x00000200)
-#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
-
-/*
- * Word1
- */
-#define RXD_W1_RSSI FIELD32(0x000000ff)
-#define RXD_W1_SIGNAL FIELD32(0x0000ff00)
-
-/*
- * Word2
- */
-#define RXD_W2_IV FIELD32(0xffffffff)
-
-/*
- * Word3
- */
-#define RXD_W3_EIV FIELD32(0xffffffff)
-
-/*
- * Macro's for converting txpower from EEPROM to dscape value
- * and from dscape value to register value.
- */
-#define MIN_TXPOWER 0
-#define MAX_TXPOWER 31
-#define DEFAULT_TXPOWER 24
-
-#define TXPOWER_FROM_DEV(__txpower) \
-({ \
- ((__txpower) > MAX_TXPOWER) ? \
- DEFAULT_TXPOWER : (__txpower); \
-})
-
-#define TXPOWER_TO_DEV(__txpower) \
-({ \
- ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
- (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
- (__txpower)); \
-})
-
-#endif /* RT2500USB_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00
- Abstract: rt2x00 global information.
- */
-
-#ifndef RT2X00_H
-#define RT2X00_H
-
-#include <linux/bitops.h>
-#include <linux/prefetch.h>
-#include <linux/skbuff.h>
-#include <linux/workqueue.h>
-#include <linux/firmware.h>
-
-#include <net/mac80211.h>
-
-#include "rt2x00debug.h"
-#include "rt2x00reg.h"
-#include "rt2x00ring.h"
-
-/*
- * Module information.
- * DRV_NAME should be set within the individual module source files.
- */
-#define DRV_VERSION "2.0.10"
-#define DRV_PROJECT "http://rt2x00.serialmonkey.com"
-
-/*
- * Debug definitions.
- * Debug output has to be enabled during compile time.
- */
-#define DEBUG_PRINTK_MSG(__dev, __kernlvl, __lvl, __msg, __args...) \
- printk(__kernlvl "%s -> %s: %s - " __msg, \
- wiphy_name((__dev)->hw->wiphy), __FUNCTION__, __lvl, ##__args)
-
-#define DEBUG_PRINTK_PROBE(__kernlvl, __lvl, __msg, __args...) \
- printk(__kernlvl "%s -> %s: %s - " __msg, \
- DRV_NAME, __FUNCTION__, __lvl, ##__args)
-
-#ifdef CONFIG_RT2X00_DEBUG
-#define DEBUG_PRINTK(__dev, __kernlvl, __lvl, __msg, __args...) \
- DEBUG_PRINTK_MSG(__dev, __kernlvl, __lvl, __msg, ##__args);
-#else
-#define DEBUG_PRINTK(__dev, __kernlvl, __lvl, __msg, __args...) \
- do { } while (0)
-#endif /* CONFIG_RT2X00_DEBUG */
-
-/*
- * Various debug levels.
- * The debug levels PANIC and ERROR both indicate serious problems,
- * for this reason they should never be ignored.
- * The special ERROR_PROBE message is for messages that are generated
- * when the rt2x00_dev is not yet initialized.
- */
-#define PANIC(__dev, __msg, __args...) \
- DEBUG_PRINTK_MSG(__dev, KERN_CRIT, "Panic", __msg, ##__args)
-#define ERROR(__dev, __msg, __args...) \
- DEBUG_PRINTK_MSG(__dev, KERN_ERR, "Error", __msg, ##__args)
-#define ERROR_PROBE(__msg, __args...) \
- DEBUG_PRINTK_PROBE(KERN_ERR, "Error", __msg, ##__args)
-#define WARNING(__dev, __msg, __args...) \
- DEBUG_PRINTK(__dev, KERN_WARNING, "Warning", __msg, ##__args)
-#define NOTICE(__dev, __msg, __args...) \
- DEBUG_PRINTK(__dev, KERN_NOTICE, "Notice", __msg, ##__args)
-#define INFO(__dev, __msg, __args...) \
- DEBUG_PRINTK(__dev, KERN_INFO, "Info", __msg, ##__args)
-#define DEBUG(__dev, __msg, __args...) \
- DEBUG_PRINTK(__dev, KERN_DEBUG, "Debug", __msg, ##__args)
-#define EEPROM(__dev, __msg, __args...) \
- DEBUG_PRINTK(__dev, KERN_DEBUG, "EEPROM recovery", __msg, ##__args)
-
-/*
- * Ring sizes.
- * Ralink PCI devices demand the Frame size to be a multiple of 128 bytes.
- * DATA_FRAME_SIZE is used for TX, RX, ATIM and PRIO rings.
- * MGMT_FRAME_SIZE is used for the BEACON ring.
- */
-#define DATA_FRAME_SIZE 2432
-#define MGMT_FRAME_SIZE 256
-
-/*
- * Number of entries in a packet ring.
- * PCI devices only need 1 Beacon entry,
- * but USB devices require a second because they
- * have to send a Guardian byte first.
- */
-#define RX_ENTRIES 12
-#define TX_ENTRIES 12
-#define ATIM_ENTRIES 1
-#define BEACON_ENTRIES 2
-
-/*
- * Standard timing and size defines.
- * These values should follow the ieee80211 specifications.
- */
-#define ACK_SIZE 14
-#define IEEE80211_HEADER 24
-#define PLCP 48
-#define BEACON 100
-#define PREAMBLE 144
-#define SHORT_PREAMBLE 72
-#define SLOT_TIME 20
-#define SHORT_SLOT_TIME 9
-#define SIFS 10
-#define PIFS ( SIFS + SLOT_TIME )
-#define SHORT_PIFS ( SIFS + SHORT_SLOT_TIME )
-#define DIFS ( PIFS + SLOT_TIME )
-#define SHORT_DIFS ( SHORT_PIFS + SHORT_SLOT_TIME )
-#define EIFS ( SIFS + (8 * (IEEE80211_HEADER + ACK_SIZE)) )
-
-/*
- * IEEE802.11 header defines
- */
-static inline int is_rts_frame(u16 fc)
-{
- return !!(((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) &&
- ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_RTS));
-}
-
-static inline int is_cts_frame(u16 fc)
-{
- return !!(((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) &&
- ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_CTS));
-}
-
-static inline int is_probe_resp(u16 fc)
-{
- return !!(((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) &&
- ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PROBE_RESP));
-}
-
-/*
- * Chipset identification
- * The chipset on the device is composed of a RT and RF chip.
- * The chipset combination is important for determining device capabilities.
- */
-struct rt2x00_chip {
- u16 rt;
-#define RT2460 0x0101
-#define RT2560 0x0201
-#define RT2570 0x1201
-#define RT2561s 0x0301 /* Turbo */
-#define RT2561 0x0302
-#define RT2661 0x0401
-#define RT2571 0x1300
-
- u16 rf;
- u32 rev;
-};
-
-/*
- * RF register values that belong to a particular channel.
- */
-struct rf_channel {
- int channel;
- u32 rf1;
- u32 rf2;
- u32 rf3;
- u32 rf4;
-};
-
-/*
- * To optimize the quality of the link we need to store
- * the quality of received frames and periodically
- * optimize the link.
- */
-struct link {
- /*
- * Link tuner counter
- * The number of times the link has been tuned
- * since the radio has been switched on.
- */
- u32 count;
-
- /*
- * Statistics required for Link tuning.
- * For the average RSSI value we use the "Walking average" approach.
- * When adding RSSI to the average value the following calculation
- * is needed:
- *
- * avg_rssi = ((avg_rssi * 7) + rssi) / 8;
- *
- * The advantage of this approach is that we only need 1 variable
- * to store the average in (No need for a count and a total).
- * But more importantly, normal average values will over time
- * move less and less towards newly added values this results
- * that with link tuning, the device can have a very good RSSI
- * for a few minutes but when the device is moved away from the AP
- * the average will not decrease fast enough to compensate.
- * The walking average compensates this and will move towards
- * the new values correctly allowing a effective link tuning.
- */
- int avg_rssi;
- int vgc_level;
- int false_cca;
-
- /*
- * Statistics required for Signal quality calculation.
- * For calculating the Signal quality we have to determine
- * the total number of success and failed RX and TX frames.
- * After that we also use the average RSSI value to help
- * determining the signal quality.
- * For the calculation we will use the following algorithm:
- *
- * rssi_percentage = (avg_rssi * 100) / rssi_offset
- * rx_percentage = (rx_success * 100) / rx_total
- * tx_percentage = (tx_success * 100) / tx_total
- * avg_signal = ((WEIGHT_RSSI * avg_rssi) +
- * (WEIGHT_TX * tx_percentage) +
- * (WEIGHT_RX * rx_percentage)) / 100
- *
- * This value should then be checked to not be greated then 100.
- */
- int rx_percentage;
- int rx_success;
- int rx_failed;
- int tx_percentage;
- int tx_success;
- int tx_failed;
-#define WEIGHT_RSSI 20
-#define WEIGHT_RX 40
-#define WEIGHT_TX 40
-
- /*
- * Work structure for scheduling periodic link tuning.
- */
- struct delayed_work work;
-};
-
-/*
- * Clear all counters inside the link structure.
- * This can be easiest achieved by memsetting everything
- * except for the work structure at the end.
- */
-static inline void rt2x00_clear_link(struct link *link)
-{
- memset(link, 0x00, sizeof(*link) - sizeof(link->work));
- link->rx_percentage = 50;
- link->tx_percentage = 50;
-}
-
-/*
- * Update the rssi using the walking average approach.
- */
-static inline void rt2x00_update_link_rssi(struct link *link, int rssi)
-{
- if (!link->avg_rssi)
- link->avg_rssi = rssi;
- else
- link->avg_rssi = ((link->avg_rssi * 7) + rssi) / 8;
-}
-
-/*
- * When the avg_rssi is unset or no frames have been received),
- * we need to return the default value which needs to be less
- * than -80 so the device will select the maximum sensitivity.
- */
-static inline int rt2x00_get_link_rssi(struct link *link)
-{
- return (link->avg_rssi && link->rx_success) ? link->avg_rssi : -128;
-}
-
-/*
- * Interface structure
- * Configuration details about the current interface.
- */
-struct interface {
- /*
- * Interface identification. The value is assigned
- * to us by the 80211 stack, and is used to request
- * new beacons.
- */
- int id;
-
- /*
- * Current working type (IEEE80211_IF_TYPE_*).
- * When set to INVALID_INTERFACE, no interface is configured.
- */
- int type;
-#define INVALID_INTERFACE IEEE80211_IF_TYPE_INVALID
-
- /*
- * MAC of the device.
- */
- u8 mac[ETH_ALEN];
-
- /*
- * BBSID of the AP to associate with.
- */
- u8 bssid[ETH_ALEN];
-
- /*
- * Store the packet filter mode for the current interface.
- */
- unsigned int filter;
-};
-
-static inline int is_interface_present(struct interface *intf)
-{
- return !!intf->id;
-}
-
-static inline int is_interface_type(struct interface *intf, int type)
-{
- return intf->type == type;
-}
-
-/*
- * Details about the supported modes, rates and channels
- * of a particular chipset. This is used by rt2x00lib
- * to build the ieee80211_hw_mode array for mac80211.
- */
-struct hw_mode_spec {
- /*
- * Number of modes, rates and channels.
- */
- int num_modes;
- int num_rates;
- int num_channels;
-
- /*
- * txpower values.
- */
- const u8 *tx_power_a;
- const u8 *tx_power_bg;
- u8 tx_power_default;
-
- /*
- * Device/chipset specific value.
- */
- const struct rf_channel *channels;
-};
-
-/*
- * Configuration structure wrapper around the
- * mac80211 configuration structure.
- * When mac80211 configures the driver, rt2x00lib
- * can precalculate values which are equal for all
- * rt2x00 drivers. Those values can be stored in here.
- */
-struct rt2x00lib_conf {
- struct ieee80211_conf *conf;
- struct rf_channel rf;
-
- int phymode;
-
- int basic_rates;
- int slot_time;
-
- short sifs;
- short pifs;
- short difs;
- short eifs;
-};
-
-/*
- * rt2x00lib callback functions.
- */
-struct rt2x00lib_ops {
- /*
- * Interrupt handlers.
- */
- irq_handler_t irq_handler;
-
- /*
- * Device init handlers.
- */
- int (*probe_hw) (struct rt2x00_dev *rt2x00dev);
- char *(*get_firmware_name) (struct rt2x00_dev *rt2x00dev);
- int (*load_firmware) (struct rt2x00_dev *rt2x00dev, void *data,
- const size_t len);
-
- /*
- * Device initialization/deinitialization handlers.
- */
- int (*initialize) (struct rt2x00_dev *rt2x00dev);
- void (*uninitialize) (struct rt2x00_dev *rt2x00dev);
-
- /*
- * Radio control handlers.
- */
- int (*set_device_state) (struct rt2x00_dev *rt2x00dev,
- enum dev_state state);
- int (*rfkill_poll) (struct rt2x00_dev *rt2x00dev);
- void (*link_stats) (struct rt2x00_dev *rt2x00dev);
- void (*reset_tuner) (struct rt2x00_dev *rt2x00dev);
- void (*link_tuner) (struct rt2x00_dev *rt2x00dev);
-
- /*
- * TX control handlers
- */
- void (*write_tx_desc) (struct rt2x00_dev *rt2x00dev,
- struct data_desc *txd,
- struct txdata_entry_desc *desc,
- struct ieee80211_hdr *ieee80211hdr,
- unsigned int length,
- struct ieee80211_tx_control *control);
- int (*write_tx_data) (struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring, struct sk_buff *skb,
- struct ieee80211_tx_control *control);
- int (*get_tx_data_len) (struct rt2x00_dev *rt2x00dev,
- struct sk_buff *skb);
- void (*kick_tx_queue) (struct rt2x00_dev *rt2x00dev,
- unsigned int queue);
-
- /*
- * RX control handlers
- */
- void (*fill_rxdone) (struct data_entry *entry,
- struct rxdata_entry_desc *desc);
-
- /*
- * Configuration handlers.
- */
- void (*config_mac_addr) (struct rt2x00_dev *rt2x00dev, __le32 *mac);
- void (*config_bssid) (struct rt2x00_dev *rt2x00dev, __le32 *bssid);
- void (*config_type) (struct rt2x00_dev *rt2x00dev, const int type,
- const int tsf_sync);
- void (*config_preamble) (struct rt2x00_dev *rt2x00dev,
- const int short_preamble,
- const int ack_timeout,
- const int ack_consume_time);
- void (*config) (struct rt2x00_dev *rt2x00dev, const unsigned int flags,
- struct rt2x00lib_conf *libconf);
-#define CONFIG_UPDATE_PHYMODE ( 1 << 1 )
-#define CONFIG_UPDATE_CHANNEL ( 1 << 2 )
-#define CONFIG_UPDATE_TXPOWER ( 1 << 3 )
-#define CONFIG_UPDATE_ANTENNA ( 1 << 4 )
-#define CONFIG_UPDATE_SLOT_TIME ( 1 << 5 )
-#define CONFIG_UPDATE_BEACON_INT ( 1 << 6 )
-#define CONFIG_UPDATE_ALL 0xffff
-};
-
-/*
- * rt2x00 driver callback operation structure.
- */
-struct rt2x00_ops {
- const char *name;
- const unsigned int rxd_size;
- const unsigned int txd_size;
- const unsigned int eeprom_size;
- const unsigned int rf_size;
- const struct rt2x00lib_ops *lib;
- const struct ieee80211_ops *hw;
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
- const struct rt2x00debug *debugfs;
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-};
-
-/*
- * rt2x00 device flags
- */
-enum rt2x00_flags {
- /*
- * Device state flags
- */
- DEVICE_PRESENT,
- DEVICE_REGISTERED_HW,
- DEVICE_INITIALIZED,
- DEVICE_STARTED,
- DEVICE_STARTED_SUSPEND,
- DEVICE_ENABLED_RADIO,
- DEVICE_DISABLED_RADIO_HW,
-
- /*
- * Driver features
- */
- DRIVER_REQUIRE_FIRMWARE,
- DRIVER_REQUIRE_BEACON_RING,
-
- /*
- * Driver configuration
- */
- CONFIG_SUPPORT_HW_BUTTON,
- CONFIG_FRAME_TYPE,
- CONFIG_RF_SEQUENCE,
- CONFIG_EXTERNAL_LNA_A,
- CONFIG_EXTERNAL_LNA_BG,
- CONFIG_DOUBLE_ANTENNA,
- CONFIG_DISABLE_LINK_TUNING,
- CONFIG_SHORT_PREAMBLE,
-};
-
-/*
- * rt2x00 device structure.
- */
-struct rt2x00_dev {
- /*
- * Device structure.
- * The structure stored in here depends on the
- * system bus (PCI or USB).
- * When accessing this variable, the rt2x00dev_{pci,usb}
- * macro's should be used for correct typecasting.
- */
- void *dev;
-#define rt2x00dev_pci(__dev) ( (struct pci_dev*)(__dev)->dev )
-#define rt2x00dev_usb(__dev) ( (struct usb_interface*)(__dev)->dev )
-
- /*
- * Callback functions.
- */
- const struct rt2x00_ops *ops;
-
- /*
- * IEEE80211 control structure.
- */
- struct ieee80211_hw *hw;
- struct ieee80211_hw_mode *hwmodes;
- unsigned int curr_hwmode;
-#define HWMODE_B 0
-#define HWMODE_G 1
-#define HWMODE_A 2
-
- /*
- * rfkill structure for RF state switching support.
- * This will only be compiled in when required.
- */
-#ifdef CONFIG_RT2X00_LIB_RFKILL
- struct rfkill *rfkill;
- struct input_polled_dev *poll_dev;
-#endif /* CONFIG_RT2X00_LIB_RFKILL */
-
- /*
- * If enabled, the debugfs interface structures
- * required for deregistration of debugfs.
- */
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
- const struct rt2x00debug_intf *debugfs_intf;
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
- /*
- * Device flags.
- * In these flags the current status and some
- * of the device capabilities are stored.
- */
- unsigned long flags;
-
- /*
- * Chipset identification.
- */
- struct rt2x00_chip chip;
-
- /*
- * hw capability specifications.
- */
- struct hw_mode_spec spec;
-
- /*
- * Register pointers
- * csr_addr: Base register address. (PCI)
- * csr_cache: CSR cache for usb_control_msg. (USB)
- */
- void __iomem *csr_addr;
- void *csr_cache;
-
- /*
- * Interface configuration.
- */
- struct interface interface;
-
- /*
- * Link quality
- */
- struct link link;
-
- /*
- * EEPROM data.
- */
- __le16 *eeprom;
-
- /*
- * Active RF register values.
- * These are stored here so we don't need
- * to read the rf registers and can directly
- * use this value instead.
- * This field should be accessed by using
- * rt2x00_rf_read() and rt2x00_rf_write().
- */
- u32 *rf;
-
- /*
- * USB Max frame size (for rt2500usb & rt73usb).
- */
- u16 usb_maxpacket;
-
- /*
- * Current TX power value.
- */
- u16 tx_power;
-
- /*
- * LED register (for rt61pci & rt73usb).
- */
- u16 led_reg;
-
- /*
- * Led mode (LED_MODE_*)
- */
- u8 led_mode;
-
- /*
- * Rssi <-> Dbm offset
- */
- u8 rssi_offset;
-
- /*
- * Frequency offset (for rt61pci & rt73usb).
- */
- u8 freq_offset;
-
- /*
- * Low level statistics which will have
- * to be kept up to date while device is running.
- */
- struct ieee80211_low_level_stats low_level_stats;
-
- /*
- * RX configuration information.
- */
- struct ieee80211_rx_status rx_status;
-
- /*
- * Scheduled work.
- */
- struct work_struct beacon_work;
- struct work_struct filter_work;
- struct work_struct config_work;
-
- /*
- * Data ring arrays for RX, TX and Beacon.
- * The Beacon array also contains the Atim ring
- * if that is supported by the device.
- */
- int data_rings;
- struct data_ring *rx;
- struct data_ring *tx;
- struct data_ring *bcn;
-
- /*
- * Firmware image.
- */
- const struct firmware *fw;
-};
-
-/*
- * For-each loop for the ring array.
- * All rings have been allocated as a single array,
- * this means we can create a very simply loop macro
- * that is capable of looping through all rings.
- * ring_end(), txring_end() and ring_loop() are helper macro's which
- * should not be used directly. Instead the following should be used:
- * ring_for_each() - Loops through all rings (RX, TX, Beacon & Atim)
- * txring_for_each() - Loops through TX data rings (TX only)
- * txringall_for_each() - Loops through all TX rings (TX, Beacon & Atim)
- */
-#define ring_end(__dev) \
- &(__dev)->rx[(__dev)->data_rings]
-
-#define txring_end(__dev) \
- &(__dev)->tx[(__dev)->hw->queues]
-
-#define ring_loop(__entry, __start, __end) \
- for ((__entry) = (__start); \
- prefetch(&(__entry)[1]), (__entry) != (__end); \
- (__entry) = &(__entry)[1])
-
-#define ring_for_each(__dev, __entry) \
- ring_loop(__entry, (__dev)->rx, ring_end(__dev))
-
-#define txring_for_each(__dev, __entry) \
- ring_loop(__entry, (__dev)->tx, txring_end(__dev))
-
-#define txringall_for_each(__dev, __entry) \
- ring_loop(__entry, (__dev)->tx, ring_end(__dev))
-
-/*
- * Generic RF access.
- * The RF is being accessed by word index.
- */
-static inline void rt2x00_rf_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 *data)
-{
- *data = rt2x00dev->rf[word];
-}
-
-static inline void rt2x00_rf_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 data)
-{
- rt2x00dev->rf[word] = data;
-}
-
-/*
- * Generic EEPROM access.
- * The EEPROM is being accessed by word index.
- */
-static inline void *rt2x00_eeprom_addr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word)
-{
- return (void *)&rt2x00dev->eeprom[word];
-}
-
-static inline void rt2x00_eeprom_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u16 *data)
-{
- *data = le16_to_cpu(rt2x00dev->eeprom[word]);
-}
-
-static inline void rt2x00_eeprom_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u16 data)
-{
- rt2x00dev->eeprom[word] = cpu_to_le16(data);
-}
-
-/*
- * Chipset handlers
- */
-static inline void rt2x00_set_chip(struct rt2x00_dev *rt2x00dev,
- const u16 rt, const u16 rf, const u32 rev)
-{
- INFO(rt2x00dev,
- "Chipset detected - rt: %04x, rf: %04x, rev: %08x.\n",
- rt, rf, rev);
-
- rt2x00dev->chip.rt = rt;
- rt2x00dev->chip.rf = rf;
- rt2x00dev->chip.rev = rev;
-}
-
-static inline char rt2x00_rt(const struct rt2x00_chip *chipset, const u16 chip)
-{
- return (chipset->rt == chip);
-}
-
-static inline char rt2x00_rf(const struct rt2x00_chip *chipset, const u16 chip)
-{
- return (chipset->rf == chip);
-}
-
-static inline u16 rt2x00_rev(const struct rt2x00_chip *chipset)
-{
- return chipset->rev;
-}
-
-static inline u16 rt2x00_check_rev(const struct rt2x00_chip *chipset,
- const u32 rev)
-{
- return (((chipset->rev & 0xffff0) == rev) &&
- !!(chipset->rev & 0x0000f));
-}
-
-/*
- * Duration calculations
- * The rate variable passed is: 100kbs.
- * To convert from bytes to bits we multiply size with 8,
- * then the size is multiplied with 10 to make the
- * real rate -> rate argument correction.
- */
-static inline u16 get_duration(const unsigned int size, const u8 rate)
-{
- return ((size * 8 * 10) / rate);
-}
-
-static inline u16 get_duration_res(const unsigned int size, const u8 rate)
-{
- return ((size * 8 * 10) % rate);
-}
-
-/*
- * Library functions.
- */
-struct data_ring *rt2x00lib_get_ring(struct rt2x00_dev *rt2x00dev,
- const unsigned int queue);
-
-/*
- * Interrupt context handlers.
- */
-void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_txdone(struct data_entry *entry,
- const int status, const int retry);
-void rt2x00lib_rxdone(struct data_entry *entry, struct sk_buff *skb,
- struct rxdata_entry_desc *desc);
-
-/*
- * TX descriptor initializer
- */
-void rt2x00lib_write_tx_desc(struct rt2x00_dev *rt2x00dev,
- struct data_desc *txd,
- struct ieee80211_hdr *ieee80211hdr,
- unsigned int length,
- struct ieee80211_tx_control *control);
-
-/*
- * mac80211 handlers.
- */
-int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
- struct ieee80211_tx_control *control);
-int rt2x00mac_start(struct ieee80211_hw *hw);
-void rt2x00mac_stop(struct ieee80211_hw *hw);
-int rt2x00mac_add_interface(struct ieee80211_hw *hw,
- struct ieee80211_if_init_conf *conf);
-void rt2x00mac_remove_interface(struct ieee80211_hw *hw,
- struct ieee80211_if_init_conf *conf);
-int rt2x00mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
-int rt2x00mac_config_interface(struct ieee80211_hw *hw, int if_id,
- struct ieee80211_if_conf *conf);
-int rt2x00mac_get_stats(struct ieee80211_hw *hw,
- struct ieee80211_low_level_stats *stats);
-int rt2x00mac_get_tx_stats(struct ieee80211_hw *hw,
- struct ieee80211_tx_queue_stats *stats);
-void rt2x00mac_erp_ie_changed(struct ieee80211_hw *hw, u8 changes,
- int cts_protection, int preamble);
-int rt2x00mac_conf_tx(struct ieee80211_hw *hw, int queue,
- const struct ieee80211_tx_queue_params *params);
-
-/*
- * Driver allocation handlers.
- */
-int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev);
-#ifdef CONFIG_PM
-int rt2x00lib_suspend(struct rt2x00_dev *rt2x00dev, pm_message_t state);
-int rt2x00lib_resume(struct rt2x00_dev *rt2x00dev);
-#endif /* CONFIG_PM */
-
-#endif /* RT2X00_H */
+++ /dev/null
-/*
- * RT2X00 Compatability fixes for specific kernels.
- */
-#ifndef RT2X00_COMPAT_H
-#define RT2X00_COMPAT_H
-
-/*
- * First include the 2 config headers.
- * The rt2x00_config.h should overrule
- * the kernel configuration.
- */
-#include <linux/autoconf.h>
-#include "rt2x00_config.h"
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-
-/*
- * Check minimal requirements.
- */
-#if (!defined(CONFIG_MAC80211) && !defined(CONFIG_MAC80211_MODULE))
-#error mac80211 support not enabled in kernel!
-#endif
-
-#if !defined(CONFIG_WLAN_80211)
-#error 802.11 wlan card support not enabled in kernel!
-#endif
-
-#if (defined(CONFIG_RT2400PCI) || defined(CONFIG_RT2500PCI) || defined(CONFIG_RT61PCI))
-#if (!defined(CONFIG_PCI) && !defined(CONFIG_PCI_MODULE))
-#error PCI has been disabled in your kernel!
-#endif
-#if (!defined(CONFIG_EEPROM_93CX6) && !defined(CONFIG_EEPROM_93CX6_MODULE))
-#error EEPROM_93CX6 has been disabled in your kernel!
-#endif
-#endif
-
-#if (defined(CONFIG_RT2500USB) || defined(CONFIG_RT73USB))
-#if (!defined(CONFIG_USB) && !defined(CONFIG_USB_MODULE))
-#error USB has been disabled in your kernel!
-#endif
-#endif
-
-#if (defined(CONFIG_RT61PCI) || defined(CONFIG_RT73USB))
-#if (!defined(CONFIG_FW_LOADER) && !defined(CONFIG_FW_LOADER_MODULE))
-#error Firmware loading has been disabled in your kernel!
-#endif
-#if (!defined(CONFIG_CRC_ITU_T) && !defined(CONFIG_CRC_ITU_T_MODULE))
-#error CRC_ITU_T loading has been disabled in your kernel!
-#endif
-#endif
-
-#if (defined(CONFIG_RT2X00_DEBUGFS))
-#if (!defined(CONFIG_MAC80211_DEBUGFS) && !defined(CONFIG_MAC80211_DEBUGFS_MODULE))
-#error mac80211 debugfs support has been disabled in your kernel!
-#endif
-#endif
-
-#if (defined(CONFIG_RT2400PCI_BUTTON) || defined(CONFIG_RT2500PCI_BUTTON) || defined(CONFIG_RT61PCI_BUTTON))
-#if (!defined(CONFIG_RFKILL) && !defined (CONFIG_RFKILL_MODULE))
-#error RFKILL has been disabled in your kernel!
-#endif
-#endif
-
-#endif /* RT2X00_COMPAT_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00lib
- Abstract: rt2x00 generic configuration routines.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2x00lib"
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include "rt2x00.h"
-#include "rt2x00lib.h"
-
-
-/*
- * The MAC and BSSID addressess are simple array of bytes,
- * these arrays are little endian, so when sending the addressess
- * to the drivers, copy the it into a endian-signed variable.
- *
- * Note that all devices (except rt2500usb) have 32 bits
- * register word sizes. This means that whatever variable we
- * pass _must_ be a multiple of 32 bits. Otherwise the device
- * might not accept what we are sending to it.
- * This will also make it easier for the driver to write
- * the data to the device.
- *
- * Also note that when NULL is passed as address the
- * we will send 00:00:00:00:00 to the device to clear the address.
- * This will prevent the device being confused when it wants
- * to ACK frames or consideres itself associated.
- */
-void rt2x00lib_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *mac)
-{
- __le32 reg[2];
-
- memset(®, 0, sizeof(reg));
- if (mac)
- memcpy(®, mac, ETH_ALEN);
-
- rt2x00dev->ops->lib->config_mac_addr(rt2x00dev, ®[0]);
-}
-
-void rt2x00lib_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
-{
- __le32 reg[2];
-
- memset(®, 0, sizeof(reg));
- if (bssid)
- memcpy(®, bssid, ETH_ALEN);
-
- rt2x00dev->ops->lib->config_bssid(rt2x00dev, ®[0]);
-}
-
-void rt2x00lib_config_type(struct rt2x00_dev *rt2x00dev, const int type)
-{
- int tsf_sync;
-
- switch (type) {
- case IEEE80211_IF_TYPE_IBSS:
- case IEEE80211_IF_TYPE_AP:
- tsf_sync = TSF_SYNC_BEACON;
- break;
- case IEEE80211_IF_TYPE_STA:
- tsf_sync = TSF_SYNC_INFRA;
- break;
- default:
- tsf_sync = TSF_SYNC_NONE;
- break;
- }
-
- rt2x00dev->ops->lib->config_type(rt2x00dev, type, tsf_sync);
-}
-
-void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
- struct ieee80211_conf *conf, const int force_config)
-{
- struct rt2x00lib_conf libconf;
- struct ieee80211_hw_mode *mode;
- struct ieee80211_rate *rate;
- int flags = 0;
- int short_slot_time;
-
- /*
- * In some situations we want to force all configurations
- * to be reloaded (When resuming for instance).
- */
- if (force_config) {
- flags = CONFIG_UPDATE_ALL;
- goto config;
- }
-
- /*
- * Check which configuration options have been
- * updated and should be send to the device.
- */
- if (rt2x00dev->rx_status.phymode != conf->phymode)
- flags |= CONFIG_UPDATE_PHYMODE;
- if (rt2x00dev->rx_status.channel != conf->channel)
- flags |= CONFIG_UPDATE_CHANNEL;
- if (rt2x00dev->tx_power != conf->power_level)
- flags |= CONFIG_UPDATE_TXPOWER;
- if (rt2x00dev->rx_status.antenna == conf->antenna_sel_rx)
- flags |= CONFIG_UPDATE_ANTENNA;
-
- /*
- * The following configuration options are never
- * stored anywhere and will always be updated.
- */
- flags |= CONFIG_UPDATE_SLOT_TIME;
- flags |= CONFIG_UPDATE_BEACON_INT;
-
- /*
- * We have determined what options should be updated,
- * now precalculate device configuration values depending
- * on what configuration options need to be updated.
- */
-config:
- memset(&libconf, 0, sizeof(libconf));
-
- if (flags & CONFIG_UPDATE_PHYMODE) {
- switch (conf->phymode) {
- case MODE_IEEE80211A:
- libconf.phymode = HWMODE_A;
- break;
- case MODE_IEEE80211B:
- libconf.phymode = HWMODE_B;
- break;
- case MODE_IEEE80211G:
- libconf.phymode = HWMODE_G;
- break;
- default:
- ERROR(rt2x00dev,
- "Attempt to configure unsupported mode (%d)"
- "Defaulting to 802.11b", conf->phymode);
- libconf.phymode = HWMODE_B;
- }
-
- mode = &rt2x00dev->hwmodes[libconf.phymode];
- rate = &mode->rates[mode->num_rates - 1];
-
- libconf.basic_rates =
- DEVICE_GET_RATE_FIELD(rate->val, RATEMASK) & DEV_BASIC_RATEMASK;
- }
-
- if (flags & CONFIG_UPDATE_CHANNEL) {
- memcpy(&libconf.rf,
- &rt2x00dev->spec.channels[conf->channel_val],
- sizeof(libconf.rf));
- }
-
- if (flags & CONFIG_UPDATE_SLOT_TIME) {
- short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
-
- libconf.slot_time =
- short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME;
- libconf.sifs = SIFS;
- libconf.pifs = short_slot_time ? SHORT_PIFS : PIFS;
- libconf.difs = short_slot_time ? SHORT_DIFS : DIFS;
- libconf.eifs = EIFS;
- }
-
- libconf.conf = conf;
-
- /*
- * Start configuration.
- */
- rt2x00dev->ops->lib->config(rt2x00dev, flags, &libconf);
-
- /*
- * Some configuration changes affect the link quality
- * which means we need to reset the link tuner.
- */
- if (flags & (CONFIG_UPDATE_CHANNEL | CONFIG_UPDATE_ANTENNA))
- rt2x00lib_reset_link_tuner(rt2x00dev);
-
- rt2x00dev->curr_hwmode = libconf.phymode;
- rt2x00dev->rx_status.phymode = conf->phymode;
- rt2x00dev->rx_status.freq = conf->freq;
- rt2x00dev->rx_status.channel = conf->channel;
- rt2x00dev->tx_power = conf->power_level;
- rt2x00dev->rx_status.antenna = conf->antenna_sel_rx;
-}
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00lib
- Abstract: rt2x00 debugfs specific routines.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2x00lib"
-
-#include <linux/debugfs.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/uaccess.h>
-
-#include "rt2x00.h"
-#include "rt2x00lib.h"
-
-#define PRINT_LINE_LEN_MAX 32
-
-struct rt2x00debug_intf {
- /*
- * Pointer to driver structure where
- * this debugfs entry belongs to.
- */
- struct rt2x00_dev *rt2x00dev;
-
- /*
- * Reference to the rt2x00debug structure
- * which can be used to communicate with
- * the registers.
- */
- const struct rt2x00debug *debug;
-
- /*
- * Debugfs entries for:
- * - driver folder
- * - driver file
- * - chipset file
- * - device flags file
- * - register offset/value files
- * - eeprom offset/value files
- * - bbp offset/value files
- * - rf offset/value files
- */
- struct dentry *driver_folder;
- struct dentry *driver_entry;
- struct dentry *chipset_entry;
- struct dentry *dev_flags;
- struct dentry *csr_off_entry;
- struct dentry *csr_val_entry;
- struct dentry *eeprom_off_entry;
- struct dentry *eeprom_val_entry;
- struct dentry *bbp_off_entry;
- struct dentry *bbp_val_entry;
- struct dentry *rf_off_entry;
- struct dentry *rf_val_entry;
-
- /*
- * Driver and chipset files will use a data buffer
- * that has been created in advance. This will simplify
- * the code since we can use the debugfs functions.
- */
- struct debugfs_blob_wrapper driver_blob;
- struct debugfs_blob_wrapper chipset_blob;
-
- /*
- * Requested offset for each register type.
- */
- unsigned int offset_csr;
- unsigned int offset_eeprom;
- unsigned int offset_bbp;
- unsigned int offset_rf;
-};
-
-static int rt2x00debug_file_open(struct inode *inode, struct file *file)
-{
- struct rt2x00debug_intf *intf = inode->i_private;
-
- file->private_data = inode->i_private;
-
- if (!try_module_get(intf->debug->owner))
- return -EBUSY;
-
- return 0;
-}
-
-static int rt2x00debug_file_release(struct inode *inode, struct file *file)
-{
- struct rt2x00debug_intf *intf = file->private_data;
-
- module_put(intf->debug->owner);
-
- return 0;
-}
-
-#define RT2X00DEBUGFS_OPS_READ(__name, __format, __type) \
-static ssize_t rt2x00debug_read_##__name(struct file *file, \
- char __user *buf, \
- size_t length, \
- loff_t *offset) \
-{ \
- struct rt2x00debug_intf *intf = file->private_data; \
- const struct rt2x00debug *debug = intf->debug; \
- char line[16]; \
- size_t size; \
- __type value; \
- \
- if (*offset) \
- return 0; \
- \
- if (intf->offset_##__name >= debug->__name.word_count) \
- return -EINVAL; \
- \
- debug->__name.read(intf->rt2x00dev, \
- intf->offset_##__name, &value); \
- \
- size = sprintf(line, __format, value); \
- \
- if (copy_to_user(buf, line, size)) \
- return -EFAULT; \
- \
- *offset += size; \
- return size; \
-}
-
-#define RT2X00DEBUGFS_OPS_WRITE(__name, __type) \
-static ssize_t rt2x00debug_write_##__name(struct file *file, \
- const char __user *buf,\
- size_t length, \
- loff_t *offset) \
-{ \
- struct rt2x00debug_intf *intf = file->private_data; \
- const struct rt2x00debug *debug = intf->debug; \
- char line[16]; \
- size_t size; \
- __type value; \
- \
- if (*offset) \
- return 0; \
- \
- if (!capable(CAP_NET_ADMIN)) \
- return -EPERM; \
- \
- if (intf->offset_##__name >= debug->__name.word_count) \
- return -EINVAL; \
- \
- if (copy_from_user(line, buf, length)) \
- return -EFAULT; \
- \
- size = strlen(line); \
- value = simple_strtoul(line, NULL, 0); \
- \
- debug->__name.write(intf->rt2x00dev, \
- intf->offset_##__name, value); \
- \
- *offset += size; \
- return size; \
-}
-
-#define RT2X00DEBUGFS_OPS(__name, __format, __type) \
-RT2X00DEBUGFS_OPS_READ(__name, __format, __type); \
-RT2X00DEBUGFS_OPS_WRITE(__name, __type); \
- \
-static const struct file_operations rt2x00debug_fop_##__name = {\
- .owner = THIS_MODULE, \
- .read = rt2x00debug_read_##__name, \
- .write = rt2x00debug_write_##__name, \
- .open = rt2x00debug_file_open, \
- .release = rt2x00debug_file_release, \
-};
-
-RT2X00DEBUGFS_OPS(csr, "0x%.8x\n", u32);
-RT2X00DEBUGFS_OPS(eeprom, "0x%.4x\n", u16);
-RT2X00DEBUGFS_OPS(bbp, "0x%.2x\n", u8);
-RT2X00DEBUGFS_OPS(rf, "0x%.8x\n", u32);
-
-static ssize_t rt2x00debug_read_dev_flags(struct file *file,
- char __user *buf,
- size_t length,
- loff_t *offset)
-{
- struct rt2x00debug_intf *intf = file->private_data;
- char line[16];
- size_t size;
-
- if (*offset)
- return 0;
-
- size = sprintf(line, "0x%.8x\n", (unsigned int)intf->rt2x00dev->flags);
-
- if (copy_to_user(buf, line, size))
- return -EFAULT;
-
- *offset += size;
- return size;
-}
-
-static const struct file_operations rt2x00debug_fop_dev_flags = {
- .owner = THIS_MODULE,
- .read = rt2x00debug_read_dev_flags,
- .open = rt2x00debug_file_open,
- .release = rt2x00debug_file_release,
-};
-
-static struct dentry *rt2x00debug_create_file_driver(const char *name,
- struct rt2x00debug_intf
- *intf,
- struct debugfs_blob_wrapper
- *blob)
-{
- char *data;
-
- data = kzalloc(3 * PRINT_LINE_LEN_MAX, GFP_KERNEL);
- if (!data)
- return NULL;
-
- blob->data = data;
- data += sprintf(data, "driver: %s\n", intf->rt2x00dev->ops->name);
- data += sprintf(data, "version: %s\n", DRV_VERSION);
- data += sprintf(data, "compiled: %s %s\n", __DATE__, __TIME__);
- blob->size = strlen(blob->data);
-
- return debugfs_create_blob(name, S_IRUGO, intf->driver_folder, blob);
-}
-
-static struct dentry *rt2x00debug_create_file_chipset(const char *name,
- struct rt2x00debug_intf
- *intf,
- struct
- debugfs_blob_wrapper
- *blob)
-{
- const struct rt2x00debug *debug = intf->debug;
- char *data;
-
- data = kzalloc(4 * PRINT_LINE_LEN_MAX, GFP_KERNEL);
- if (!data)
- return NULL;
-
- blob->data = data;
- data += sprintf(data, "csr length: %d\n", debug->csr.word_count);
- data += sprintf(data, "eeprom length: %d\n", debug->eeprom.word_count);
- data += sprintf(data, "bbp length: %d\n", debug->bbp.word_count);
- data += sprintf(data, "rf length: %d\n", debug->rf.word_count);
- blob->size = strlen(blob->data);
-
- return debugfs_create_blob(name, S_IRUGO, intf->driver_folder, blob);
-}
-
-void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
-{
- const struct rt2x00debug *debug = rt2x00dev->ops->debugfs;
- struct rt2x00debug_intf *intf;
-
- intf = kzalloc(sizeof(struct rt2x00debug_intf), GFP_KERNEL);
- if (!intf) {
- ERROR(rt2x00dev, "Failed to allocate debug handler.\n");
- return;
- }
-
- intf->debug = debug;
- intf->rt2x00dev = rt2x00dev;
- rt2x00dev->debugfs_intf = intf;
-
- intf->driver_folder =
- debugfs_create_dir(intf->rt2x00dev->ops->name,
- rt2x00dev->hw->wiphy->debugfsdir);
- if (IS_ERR(intf->driver_folder))
- goto exit;
-
- intf->driver_entry =
- rt2x00debug_create_file_driver("driver", intf, &intf->driver_blob);
- if (IS_ERR(intf->driver_entry))
- goto exit;
-
- intf->chipset_entry =
- rt2x00debug_create_file_chipset("chipset",
- intf, &intf->chipset_blob);
- if (IS_ERR(intf->chipset_entry))
- goto exit;
-
- intf->dev_flags = debugfs_create_file("dev_flags", S_IRUGO,
- intf->driver_folder, intf,
- &rt2x00debug_fop_dev_flags);
- if (IS_ERR(intf->dev_flags))
- goto exit;
-
-#define RT2X00DEBUGFS_CREATE_ENTRY(__intf, __name) \
-({ \
- (__intf)->__name##_off_entry = \
- debugfs_create_u32(__stringify(__name) "_offset", \
- S_IRUGO | S_IWUSR, \
- (__intf)->driver_folder, \
- &(__intf)->offset_##__name); \
- if (IS_ERR((__intf)->__name##_off_entry)) \
- goto exit; \
- \
- (__intf)->__name##_val_entry = \
- debugfs_create_file(__stringify(__name) "_value", \
- S_IRUGO | S_IWUSR, \
- (__intf)->driver_folder, \
- (__intf), &rt2x00debug_fop_##__name);\
- if (IS_ERR((__intf)->__name##_val_entry)) \
- goto exit; \
-})
-
- RT2X00DEBUGFS_CREATE_ENTRY(intf, csr);
- RT2X00DEBUGFS_CREATE_ENTRY(intf, eeprom);
- RT2X00DEBUGFS_CREATE_ENTRY(intf, bbp);
- RT2X00DEBUGFS_CREATE_ENTRY(intf, rf);
-
-#undef RT2X00DEBUGFS_CREATE_ENTRY
-
- return;
-
-exit:
- rt2x00debug_deregister(rt2x00dev);
- ERROR(rt2x00dev, "Failed to register debug handler.\n");
-
- return;
-}
-
-void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev)
-{
- const struct rt2x00debug_intf *intf = rt2x00dev->debugfs_intf;
-
- if (unlikely(!intf))
- return;
-
- debugfs_remove(intf->rf_val_entry);
- debugfs_remove(intf->rf_off_entry);
- debugfs_remove(intf->bbp_val_entry);
- debugfs_remove(intf->bbp_off_entry);
- debugfs_remove(intf->eeprom_val_entry);
- debugfs_remove(intf->eeprom_off_entry);
- debugfs_remove(intf->csr_val_entry);
- debugfs_remove(intf->csr_off_entry);
- debugfs_remove(intf->dev_flags);
- debugfs_remove(intf->chipset_entry);
- debugfs_remove(intf->driver_entry);
- debugfs_remove(intf->driver_folder);
- kfree(intf->chipset_blob.data);
- kfree(intf->driver_blob.data);
- kfree(intf);
-
- rt2x00dev->debugfs_intf = NULL;
-}
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00debug
- Abstract: Data structures for the rt2x00debug.
- */
-
-#ifndef RT2X00DEBUG_H
-#define RT2X00DEBUG_H
-
-struct rt2x00_dev;
-
-#define RT2X00DEBUGFS_REGISTER_ENTRY(__name, __type) \
-struct reg##__name { \
- void (*read)(const struct rt2x00_dev *rt2x00dev, \
- const unsigned int word, __type *data); \
- void (*write)(const struct rt2x00_dev *rt2x00dev, \
- const unsigned int word, __type data); \
- \
- unsigned int word_size; \
- unsigned int word_count; \
-} __name
-
-struct rt2x00debug {
- /*
- * Reference to the modules structure.
- */
- struct module *owner;
-
- /*
- * Register access entries.
- */
- RT2X00DEBUGFS_REGISTER_ENTRY(csr, u32);
- RT2X00DEBUGFS_REGISTER_ENTRY(eeprom, u16);
- RT2X00DEBUGFS_REGISTER_ENTRY(bbp, u8);
- RT2X00DEBUGFS_REGISTER_ENTRY(rf, u32);
-};
-
-#endif /* RT2X00DEBUG_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00lib
- Abstract: rt2x00 generic device routines.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2x00lib"
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include "rt2x00.h"
-#include "rt2x00lib.h"
-
-/*
- * Ring handler.
- */
-struct data_ring *rt2x00lib_get_ring(struct rt2x00_dev *rt2x00dev,
- const unsigned int queue)
-{
- int beacon = test_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
-
- /*
- * Check if we are requesting a reqular TX ring,
- * or if we are requesting a Beacon or Atim ring.
- * For Atim rings, we should check if it is supported.
- */
- if (queue < rt2x00dev->hw->queues && rt2x00dev->tx)
- return &rt2x00dev->tx[queue];
-
- if (!rt2x00dev->bcn || !beacon)
- return NULL;
-
- if (queue == IEEE80211_TX_QUEUE_BEACON)
- return &rt2x00dev->bcn[0];
- else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
- return &rt2x00dev->bcn[1];
-
- return NULL;
-}
-EXPORT_SYMBOL_GPL(rt2x00lib_get_ring);
-
-/*
- * Link tuning handlers
- */
-static void rt2x00lib_start_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
- rt2x00_clear_link(&rt2x00dev->link);
-
- /*
- * Reset the link tuner.
- */
- rt2x00dev->ops->lib->reset_tuner(rt2x00dev);
-
- queue_delayed_work(rt2x00dev->hw->workqueue,
- &rt2x00dev->link.work, LINK_TUNE_INTERVAL);
-}
-
-static void rt2x00lib_stop_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
- cancel_delayed_work_sync(&rt2x00dev->link.work);
-}
-
-void rt2x00lib_reset_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
- if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
- return;
-
- rt2x00lib_stop_link_tuner(rt2x00dev);
- rt2x00lib_start_link_tuner(rt2x00dev);
-}
-
-/*
- * Radio control handlers.
- */
-int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
- int status;
-
- /*
- * Don't enable the radio twice.
- * And check if the hardware button has been disabled.
- */
- if (test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags) ||
- test_bit(DEVICE_DISABLED_RADIO_HW, &rt2x00dev->flags))
- return 0;
-
- /*
- * Enable radio.
- */
- status = rt2x00dev->ops->lib->set_device_state(rt2x00dev,
- STATE_RADIO_ON);
- if (status)
- return status;
-
- __set_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags);
-
- /*
- * Enable RX.
- */
- rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
-
- /*
- * Start the TX queues.
- */
- ieee80211_start_queues(rt2x00dev->hw);
-
- return 0;
-}
-
-void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
- if (!__test_and_clear_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
- return;
-
- /*
- * Stop all scheduled work.
- */
- if (work_pending(&rt2x00dev->beacon_work))
- cancel_work_sync(&rt2x00dev->beacon_work);
- if (work_pending(&rt2x00dev->filter_work))
- cancel_work_sync(&rt2x00dev->filter_work);
- if (work_pending(&rt2x00dev->config_work))
- cancel_work_sync(&rt2x00dev->config_work);
-
- /*
- * Stop the TX queues.
- */
- ieee80211_stop_queues(rt2x00dev->hw);
-
- /*
- * Disable RX.
- */
- rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
-
- /*
- * Disable radio.
- */
- rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_OFF);
-}
-
-void rt2x00lib_toggle_rx(struct rt2x00_dev *rt2x00dev, enum dev_state state)
-{
- /*
- * When we are disabling the RX, we should also stop the link tuner.
- */
- if (state == STATE_RADIO_RX_OFF)
- rt2x00lib_stop_link_tuner(rt2x00dev);
-
- rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
-
- /*
- * When we are enabling the RX, we should also start the link tuner.
- */
- if (state == STATE_RADIO_RX_ON &&
- is_interface_present(&rt2x00dev->interface))
- rt2x00lib_start_link_tuner(rt2x00dev);
-}
-
-static void rt2x00lib_precalculate_link_signal(struct link *link)
-{
- if (link->rx_failed || link->rx_success)
- link->rx_percentage =
- (link->rx_success * 100) /
- (link->rx_failed + link->rx_success);
- else
- link->rx_percentage = 50;
-
- if (link->tx_failed || link->tx_success)
- link->tx_percentage =
- (link->tx_success * 100) /
- (link->tx_failed + link->tx_success);
- else
- link->tx_percentage = 50;
-
- link->rx_success = 0;
- link->rx_failed = 0;
- link->tx_success = 0;
- link->tx_failed = 0;
-}
-
-static int rt2x00lib_calculate_link_signal(struct rt2x00_dev *rt2x00dev,
- int rssi)
-{
- int rssi_percentage = 0;
- int signal;
-
- /*
- * We need a positive value for the RSSI.
- */
- if (rssi < 0)
- rssi += rt2x00dev->rssi_offset;
-
- /*
- * Calculate the different percentages,
- * which will be used for the signal.
- */
- if (rt2x00dev->rssi_offset)
- rssi_percentage = (rssi * 100) / rt2x00dev->rssi_offset;
-
- /*
- * Add the individual percentages and use the WEIGHT
- * defines to calculate the current link signal.
- */
- signal = ((WEIGHT_RSSI * rssi_percentage) +
- (WEIGHT_TX * rt2x00dev->link.tx_percentage) +
- (WEIGHT_RX * rt2x00dev->link.rx_percentage)) / 100;
-
- return (signal > 100) ? 100 : signal;
-}
-
-static void rt2x00lib_link_tuner(struct work_struct *work)
-{
- struct rt2x00_dev *rt2x00dev =
- container_of(work, struct rt2x00_dev, link.work.work);
-
- /*
- * When the radio is shutting down we should
- * immediately cease all link tuning.
- */
- if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
- return;
-
- /*
- * Update statistics.
- */
- rt2x00dev->ops->lib->link_stats(rt2x00dev);
-
- rt2x00dev->low_level_stats.dot11FCSErrorCount +=
- rt2x00dev->link.rx_failed;
-
- /*
- * Only perform the link tuning when Link tuning
- * has been enabled (This could have been disabled from the EEPROM).
- */
- if (!test_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags))
- rt2x00dev->ops->lib->link_tuner(rt2x00dev);
-
- /*
- * Precalculate a portion of the link signal which is
- * in based on the tx/rx success/failure counters.
- */
- rt2x00lib_precalculate_link_signal(&rt2x00dev->link);
-
- /*
- * Increase tuner counter, and reschedule the next link tuner run.
- */
- rt2x00dev->link.count++;
- queue_delayed_work(rt2x00dev->hw->workqueue, &rt2x00dev->link.work,
- LINK_TUNE_INTERVAL);
-}
-
-static void rt2x00lib_packetfilter_scheduled(struct work_struct *work)
-{
- struct rt2x00_dev *rt2x00dev =
- container_of(work, struct rt2x00_dev, filter_work);
- unsigned int filter = rt2x00dev->interface.filter;
-
- /*
- * Since we had stored the filter inside interface.filter,
- * we should now clear that field. Otherwise the driver will
- * assume nothing has changed (*total_flags will be compared
- * to interface.filter to determine if any action is required).
- */
- rt2x00dev->interface.filter = 0;
-
- rt2x00dev->ops->hw->configure_filter(rt2x00dev->hw,
- filter, &filter, 0, NULL);
-}
-
-static void rt2x00lib_configuration_scheduled(struct work_struct *work)
-{
- struct rt2x00_dev *rt2x00dev =
- container_of(work, struct rt2x00_dev, config_work);
- int preamble = !test_bit(CONFIG_SHORT_PREAMBLE, &rt2x00dev->flags);
-
- rt2x00mac_erp_ie_changed(rt2x00dev->hw,
- IEEE80211_ERP_CHANGE_PREAMBLE, 0, preamble);
-}
-
-/*
- * Interrupt context handlers.
- */
-static void rt2x00lib_beacondone_scheduled(struct work_struct *work)
-{
- struct rt2x00_dev *rt2x00dev =
- container_of(work, struct rt2x00_dev, beacon_work);
- struct data_ring *ring =
- rt2x00lib_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
- struct data_entry *entry = rt2x00_get_data_entry(ring);
- struct sk_buff *skb;
-
- skb = ieee80211_beacon_get(rt2x00dev->hw,
- rt2x00dev->interface.id,
- &entry->tx_status.control);
- if (!skb)
- return;
-
- rt2x00dev->ops->hw->beacon_update(rt2x00dev->hw, skb,
- &entry->tx_status.control);
-
- dev_kfree_skb(skb);
-}
-
-void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev)
-{
- if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
- return;
-
- queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->beacon_work);
-}
-EXPORT_SYMBOL_GPL(rt2x00lib_beacondone);
-
-void rt2x00lib_txdone(struct data_entry *entry,
- const int status, const int retry)
-{
- struct rt2x00_dev *rt2x00dev = entry->ring->rt2x00dev;
- struct ieee80211_tx_status *tx_status = &entry->tx_status;
- struct ieee80211_low_level_stats *stats = &rt2x00dev->low_level_stats;
- int success = !!(status == TX_SUCCESS || status == TX_SUCCESS_RETRY);
- int fail = !!(status == TX_FAIL_RETRY || status == TX_FAIL_INVALID ||
- status == TX_FAIL_OTHER);
-
- /*
- * Update TX statistics.
- */
- tx_status->flags = 0;
- tx_status->ack_signal = 0;
- tx_status->excessive_retries = (status == TX_FAIL_RETRY);
- tx_status->retry_count = retry;
- rt2x00dev->link.tx_success += success;
- rt2x00dev->link.tx_failed += retry + fail;
-
- if (!(tx_status->control.flags & IEEE80211_TXCTL_NO_ACK)) {
- if (success)
- tx_status->flags |= IEEE80211_TX_STATUS_ACK;
- else
- stats->dot11ACKFailureCount++;
- }
-
- tx_status->queue_length = entry->ring->stats.limit;
- tx_status->queue_number = tx_status->control.queue;
-
- if (tx_status->control.flags & IEEE80211_TXCTL_USE_RTS_CTS) {
- if (success)
- stats->dot11RTSSuccessCount++;
- else
- stats->dot11RTSFailureCount++;
- }
-
- /*
- * Send the tx_status to mac80211,
- * that method also cleans up the skb structure.
- */
- ieee80211_tx_status_irqsafe(rt2x00dev->hw, entry->skb, tx_status);
- entry->skb = NULL;
-}
-EXPORT_SYMBOL_GPL(rt2x00lib_txdone);
-
-void rt2x00lib_rxdone(struct data_entry *entry, struct sk_buff *skb,
- struct rxdata_entry_desc *desc)
-{
- struct rt2x00_dev *rt2x00dev = entry->ring->rt2x00dev;
- struct ieee80211_rx_status *rx_status = &rt2x00dev->rx_status;
- struct ieee80211_hw_mode *mode;
- struct ieee80211_rate *rate;
- unsigned int i;
- int val = 0;
-
- /*
- * Update RX statistics.
- */
- mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
- for (i = 0; i < mode->num_rates; i++) {
- rate = &mode->rates[i];
-
- /*
- * When frame was received with an OFDM bitrate,
- * the signal is the PLCP value. If it was received with
- * a CCK bitrate the signal is the rate in 0.5kbit/s.
- */
- if (!desc->ofdm)
- val = DEVICE_GET_RATE_FIELD(rate->val, RATE);
- else
- val = DEVICE_GET_RATE_FIELD(rate->val, PLCP);
-
- if (val == desc->signal) {
- val = rate->val;
- break;
- }
- }
-
- rt2x00_update_link_rssi(&rt2x00dev->link, desc->rssi);
- rt2x00dev->link.rx_success++;
- rx_status->rate = val;
- rx_status->signal =
- rt2x00lib_calculate_link_signal(rt2x00dev, desc->rssi);
- rx_status->ssi = desc->rssi;
- rx_status->flag = desc->flags;
-
- /*
- * Send frame to mac80211
- */
- ieee80211_rx_irqsafe(rt2x00dev->hw, skb, rx_status);
-}
-EXPORT_SYMBOL_GPL(rt2x00lib_rxdone);
-
-/*
- * TX descriptor initializer
- */
-void rt2x00lib_write_tx_desc(struct rt2x00_dev *rt2x00dev,
- struct data_desc *txd,
- struct ieee80211_hdr *ieee80211hdr,
- unsigned int length,
- struct ieee80211_tx_control *control)
-{
- struct txdata_entry_desc desc;
- struct data_ring *ring;
- int tx_rate;
- int bitrate;
- int duration;
- int residual;
- u16 frame_control;
- u16 seq_ctrl;
-
- /*
- * Make sure the descriptor is properly cleared.
- */
- memset(&desc, 0x00, sizeof(desc));
-
- /*
- * Get ring pointer, if we fail to obtain the
- * correct ring, then use the first TX ring.
- */
- ring = rt2x00lib_get_ring(rt2x00dev, control->queue);
- if (!ring)
- ring = rt2x00lib_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
-
- desc.cw_min = ring->tx_params.cw_min;
- desc.cw_max = ring->tx_params.cw_max;
- desc.aifs = ring->tx_params.aifs;
-
- /*
- * Identify queue
- */
- if (control->queue < rt2x00dev->hw->queues)
- desc.queue = control->queue;
- else if (control->queue == IEEE80211_TX_QUEUE_BEACON ||
- control->queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
- desc.queue = QUEUE_MGMT;
- else
- desc.queue = QUEUE_OTHER;
-
- /*
- * Read required fields from ieee80211 header.
- */
- frame_control = le16_to_cpu(ieee80211hdr->frame_control);
- seq_ctrl = le16_to_cpu(ieee80211hdr->seq_ctrl);
-
- tx_rate = control->tx_rate;
-
- /*
- * Check if this is a RTS/CTS frame
- */
- if (is_rts_frame(frame_control) || is_cts_frame(frame_control)) {
- __set_bit(ENTRY_TXD_BURST, &desc.flags);
- if (is_rts_frame(frame_control))
- __set_bit(ENTRY_TXD_RTS_FRAME, &desc.flags);
- if (control->rts_cts_rate)
- tx_rate = control->rts_cts_rate;
- }
-
- /*
- * Check for OFDM
- */
- if (DEVICE_GET_RATE_FIELD(tx_rate, RATEMASK) & DEV_OFDM_RATEMASK)
- __set_bit(ENTRY_TXD_OFDM_RATE, &desc.flags);
-
- /*
- * Check if more fragments are pending
- */
- if (ieee80211_get_morefrag(ieee80211hdr)) {
- __set_bit(ENTRY_TXD_BURST, &desc.flags);
- __set_bit(ENTRY_TXD_MORE_FRAG, &desc.flags);
- }
-
- /*
- * Beacons and probe responses require the tsf timestamp
- * to be inserted into the frame.
- */
- if (control->queue == IEEE80211_TX_QUEUE_BEACON ||
- is_probe_resp(frame_control))
- __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc.flags);
-
- /*
- * Determine with what IFS priority this frame should be send.
- * Set ifs to IFS_SIFS when the this is not the first fragment,
- * or this fragment came after RTS/CTS.
- */
- if ((seq_ctrl & IEEE80211_SCTL_FRAG) > 0 ||
- test_bit(ENTRY_TXD_RTS_FRAME, &desc.flags))
- desc.ifs = IFS_SIFS;
- else
- desc.ifs = IFS_BACKOFF;
-
- /*
- * PLCP setup
- * Length calculation depends on OFDM/CCK rate.
- */
- desc.signal = DEVICE_GET_RATE_FIELD(tx_rate, PLCP);
- desc.service = 0x04;
-
- if (test_bit(ENTRY_TXD_OFDM_RATE, &desc.flags)) {
- desc.length_high = ((length + FCS_LEN) >> 6) & 0x3f;
- desc.length_low = ((length + FCS_LEN) & 0x3f);
- } else {
- bitrate = DEVICE_GET_RATE_FIELD(tx_rate, RATE);
-
- /*
- * Convert length to microseconds.
- */
- residual = get_duration_res(length + FCS_LEN, bitrate);
- duration = get_duration(length + FCS_LEN, bitrate);
-
- if (residual != 0) {
- duration++;
-
- /*
- * Check if we need to set the Length Extension
- */
- if (bitrate == 110 && residual <= 30)
- desc.service |= 0x80;
- }
-
- desc.length_high = (duration >> 8) & 0xff;
- desc.length_low = duration & 0xff;
-
- /*
- * When preamble is enabled we should set the
- * preamble bit for the signal.
- */
- if (DEVICE_GET_RATE_FIELD(tx_rate, PREAMBLE))
- desc.signal |= 0x08;
- }
-
- rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, txd, &desc,
- ieee80211hdr, length, control);
-}
-EXPORT_SYMBOL_GPL(rt2x00lib_write_tx_desc);
-
-/*
- * Driver initialization handlers.
- */
-static void rt2x00lib_channel(struct ieee80211_channel *entry,
- const int channel, const int tx_power,
- const int value)
-{
- entry->chan = channel;
- if (channel <= 14)
- entry->freq = 2407 + (5 * channel);
- else
- entry->freq = 5000 + (5 * channel);
- entry->val = value;
- entry->flag =
- IEEE80211_CHAN_W_IBSS |
- IEEE80211_CHAN_W_ACTIVE_SCAN |
- IEEE80211_CHAN_W_SCAN;
- entry->power_level = tx_power;
- entry->antenna_max = 0xff;
-}
-
-static void rt2x00lib_rate(struct ieee80211_rate *entry,
- const int rate, const int mask,
- const int plcp, const int flags)
-{
- entry->rate = rate;
- entry->val =
- DEVICE_SET_RATE_FIELD(rate, RATE) |
- DEVICE_SET_RATE_FIELD(mask, RATEMASK) |
- DEVICE_SET_RATE_FIELD(plcp, PLCP);
- entry->flags = flags;
- entry->val2 = entry->val;
- if (entry->flags & IEEE80211_RATE_PREAMBLE2)
- entry->val2 |= DEVICE_SET_RATE_FIELD(1, PREAMBLE);
- entry->min_rssi_ack = 0;
- entry->min_rssi_ack_delta = 0;
-}
-
-static int rt2x00lib_probe_hw_modes(struct rt2x00_dev *rt2x00dev,
- struct hw_mode_spec *spec)
-{
- struct ieee80211_hw *hw = rt2x00dev->hw;
- struct ieee80211_hw_mode *hwmodes;
- struct ieee80211_channel *channels;
- struct ieee80211_rate *rates;
- unsigned int i;
- unsigned char tx_power;
-
- hwmodes = kzalloc(sizeof(*hwmodes) * spec->num_modes, GFP_KERNEL);
- if (!hwmodes)
- goto exit;
-
- channels = kzalloc(sizeof(*channels) * spec->num_channels, GFP_KERNEL);
- if (!channels)
- goto exit_free_modes;
-
- rates = kzalloc(sizeof(*rates) * spec->num_rates, GFP_KERNEL);
- if (!rates)
- goto exit_free_channels;
-
- /*
- * Initialize Rate list.
- */
- rt2x00lib_rate(&rates[0], 10, DEV_RATEMASK_1MB,
- 0x00, IEEE80211_RATE_CCK);
- rt2x00lib_rate(&rates[1], 20, DEV_RATEMASK_2MB,
- 0x01, IEEE80211_RATE_CCK_2);
- rt2x00lib_rate(&rates[2], 55, DEV_RATEMASK_5_5MB,
- 0x02, IEEE80211_RATE_CCK_2);
- rt2x00lib_rate(&rates[3], 110, DEV_RATEMASK_11MB,
- 0x03, IEEE80211_RATE_CCK_2);
-
- if (spec->num_rates > 4) {
- rt2x00lib_rate(&rates[4], 60, DEV_RATEMASK_6MB,
- 0x0b, IEEE80211_RATE_OFDM);
- rt2x00lib_rate(&rates[5], 90, DEV_RATEMASK_9MB,
- 0x0f, IEEE80211_RATE_OFDM);
- rt2x00lib_rate(&rates[6], 120, DEV_RATEMASK_12MB,
- 0x0a, IEEE80211_RATE_OFDM);
- rt2x00lib_rate(&rates[7], 180, DEV_RATEMASK_18MB,
- 0x0e, IEEE80211_RATE_OFDM);
- rt2x00lib_rate(&rates[8], 240, DEV_RATEMASK_24MB,
- 0x09, IEEE80211_RATE_OFDM);
- rt2x00lib_rate(&rates[9], 360, DEV_RATEMASK_36MB,
- 0x0d, IEEE80211_RATE_OFDM);
- rt2x00lib_rate(&rates[10], 480, DEV_RATEMASK_48MB,
- 0x08, IEEE80211_RATE_OFDM);
- rt2x00lib_rate(&rates[11], 540, DEV_RATEMASK_54MB,
- 0x0c, IEEE80211_RATE_OFDM);
- }
-
- /*
- * Initialize Channel list.
- */
- for (i = 0; i < spec->num_channels; i++) {
- if (spec->channels[i].channel <= 14)
- tx_power = spec->tx_power_bg[i];
- else if (spec->tx_power_a)
- tx_power = spec->tx_power_a[i];
- else
- tx_power = spec->tx_power_default;
-
- rt2x00lib_channel(&channels[i],
- spec->channels[i].channel, tx_power, i);
- }
-
- /*
- * Intitialize 802.11b
- * Rates: CCK.
- * Channels: OFDM.
- */
- if (spec->num_modes > HWMODE_B) {
- hwmodes[HWMODE_B].mode = MODE_IEEE80211B;
- hwmodes[HWMODE_B].num_channels = 14;
- hwmodes[HWMODE_B].num_rates = 4;
- hwmodes[HWMODE_B].channels = channels;
- hwmodes[HWMODE_B].rates = rates;
- }
-
- /*
- * Intitialize 802.11g
- * Rates: CCK, OFDM.
- * Channels: OFDM.
- */
- if (spec->num_modes > HWMODE_G) {
- hwmodes[HWMODE_G].mode = MODE_IEEE80211G;
- hwmodes[HWMODE_G].num_channels = 14;
- hwmodes[HWMODE_G].num_rates = spec->num_rates;
- hwmodes[HWMODE_G].channels = channels;
- hwmodes[HWMODE_G].rates = rates;
- }
-
- /*
- * Intitialize 802.11a
- * Rates: OFDM.
- * Channels: OFDM, UNII, HiperLAN2.
- */
- if (spec->num_modes > HWMODE_A) {
- hwmodes[HWMODE_A].mode = MODE_IEEE80211A;
- hwmodes[HWMODE_A].num_channels = spec->num_channels - 14;
- hwmodes[HWMODE_A].num_rates = spec->num_rates - 4;
- hwmodes[HWMODE_A].channels = &channels[14];
- hwmodes[HWMODE_A].rates = &rates[4];
- }
-
- if (spec->num_modes > HWMODE_G &&
- ieee80211_register_hwmode(hw, &hwmodes[HWMODE_G]))
- goto exit_free_rates;
-
- if (spec->num_modes > HWMODE_B &&
- ieee80211_register_hwmode(hw, &hwmodes[HWMODE_B]))
- goto exit_free_rates;
-
- if (spec->num_modes > HWMODE_A &&
- ieee80211_register_hwmode(hw, &hwmodes[HWMODE_A]))
- goto exit_free_rates;
-
- rt2x00dev->hwmodes = hwmodes;
-
- return 0;
-
-exit_free_rates:
- kfree(rates);
-
-exit_free_channels:
- kfree(channels);
-
-exit_free_modes:
- kfree(hwmodes);
-
-exit:
- ERROR(rt2x00dev, "Allocation ieee80211 modes failed.\n");
- return -ENOMEM;
-}
-
-static void rt2x00lib_remove_hw(struct rt2x00_dev *rt2x00dev)
-{
- if (test_bit(DEVICE_REGISTERED_HW, &rt2x00dev->flags))
- ieee80211_unregister_hw(rt2x00dev->hw);
-
- if (likely(rt2x00dev->hwmodes)) {
- kfree(rt2x00dev->hwmodes->channels);
- kfree(rt2x00dev->hwmodes->rates);
- kfree(rt2x00dev->hwmodes);
- rt2x00dev->hwmodes = NULL;
- }
-}
-
-static int rt2x00lib_probe_hw(struct rt2x00_dev *rt2x00dev)
-{
- struct hw_mode_spec *spec = &rt2x00dev->spec;
- int status;
-
- /*
- * Initialize HW modes.
- */
- status = rt2x00lib_probe_hw_modes(rt2x00dev, spec);
- if (status)
- return status;
-
- /*
- * Register HW.
- */
- status = ieee80211_register_hw(rt2x00dev->hw);
- if (status) {
- rt2x00lib_remove_hw(rt2x00dev);
- return status;
- }
-
- __set_bit(DEVICE_REGISTERED_HW, &rt2x00dev->flags);
-
- return 0;
-}
-
-/*
- * Initialization/uninitialization handlers.
- */
-static int rt2x00lib_alloc_entries(struct data_ring *ring,
- const u16 max_entries, const u16 data_size,
- const u16 desc_size)
-{
- struct data_entry *entry;
- unsigned int i;
-
- ring->stats.limit = max_entries;
- ring->data_size = data_size;
- ring->desc_size = desc_size;
-
- /*
- * Allocate all ring entries.
- */
- entry = kzalloc(ring->stats.limit * sizeof(*entry), GFP_KERNEL);
- if (!entry)
- return -ENOMEM;
-
- for (i = 0; i < ring->stats.limit; i++) {
- entry[i].flags = 0;
- entry[i].ring = ring;
- entry[i].skb = NULL;
- }
-
- ring->entry = entry;
-
- return 0;
-}
-
-static int rt2x00lib_alloc_ring_entries(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring;
-
- /*
- * Allocate the RX ring.
- */
- if (rt2x00lib_alloc_entries(rt2x00dev->rx, RX_ENTRIES, DATA_FRAME_SIZE,
- rt2x00dev->ops->rxd_size))
- return -ENOMEM;
-
- /*
- * First allocate the TX rings.
- */
- txring_for_each(rt2x00dev, ring) {
- if (rt2x00lib_alloc_entries(ring, TX_ENTRIES, DATA_FRAME_SIZE,
- rt2x00dev->ops->txd_size))
- return -ENOMEM;
- }
-
- if (!test_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags))
- return 0;
-
- /*
- * Allocate the BEACON ring.
- */
- if (rt2x00lib_alloc_entries(&rt2x00dev->bcn[0], BEACON_ENTRIES,
- MGMT_FRAME_SIZE, rt2x00dev->ops->txd_size))
- return -ENOMEM;
-
- /*
- * Allocate the Atim ring.
- */
- if (rt2x00lib_alloc_entries(&rt2x00dev->bcn[1], ATIM_ENTRIES,
- DATA_FRAME_SIZE, rt2x00dev->ops->txd_size))
- return -ENOMEM;
-
- return 0;
-}
-
-static void rt2x00lib_free_ring_entries(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring;
-
- ring_for_each(rt2x00dev, ring) {
- kfree(ring->entry);
- ring->entry = NULL;
- }
-}
-
-void rt2x00lib_uninitialize(struct rt2x00_dev *rt2x00dev)
-{
- if (!__test_and_clear_bit(DEVICE_INITIALIZED, &rt2x00dev->flags))
- return;
-
- /*
- * Unregister rfkill.
- */
- rt2x00rfkill_unregister(rt2x00dev);
-
- /*
- * Allow the HW to uninitialize.
- */
- rt2x00dev->ops->lib->uninitialize(rt2x00dev);
-
- /*
- * Free allocated ring entries.
- */
- rt2x00lib_free_ring_entries(rt2x00dev);
-}
-
-int rt2x00lib_initialize(struct rt2x00_dev *rt2x00dev)
-{
- int status;
-
- if (test_bit(DEVICE_INITIALIZED, &rt2x00dev->flags))
- return 0;
-
- /*
- * Allocate all ring entries.
- */
- status = rt2x00lib_alloc_ring_entries(rt2x00dev);
- if (status) {
- ERROR(rt2x00dev, "Ring entries allocation failed.\n");
- return status;
- }
-
- /*
- * Initialize the device.
- */
- status = rt2x00dev->ops->lib->initialize(rt2x00dev);
- if (status)
- goto exit;
-
- __set_bit(DEVICE_INITIALIZED, &rt2x00dev->flags);
-
- /*
- * Register the rfkill handler.
- */
- status = rt2x00rfkill_register(rt2x00dev);
- if (status)
- goto exit_unitialize;
-
- return 0;
-
-exit_unitialize:
- rt2x00lib_uninitialize(rt2x00dev);
-
-exit:
- rt2x00lib_free_ring_entries(rt2x00dev);
-
- return status;
-}
-
-/*
- * driver allocation handlers.
- */
-static int rt2x00lib_alloc_rings(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring;
-
- /*
- * We need the following rings:
- * RX: 1
- * TX: hw->queues
- * Beacon: 1 (if required)
- * Atim: 1 (if required)
- */
- rt2x00dev->data_rings = 1 + rt2x00dev->hw->queues +
- (2 * test_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags));
-
- ring = kzalloc(rt2x00dev->data_rings * sizeof(*ring), GFP_KERNEL);
- if (!ring) {
- ERROR(rt2x00dev, "Ring allocation failed.\n");
- return -ENOMEM;
- }
-
- /*
- * Initialize pointers
- */
- rt2x00dev->rx = ring;
- rt2x00dev->tx = &rt2x00dev->rx[1];
- if (test_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags))
- rt2x00dev->bcn = &rt2x00dev->tx[rt2x00dev->hw->queues];
-
- /*
- * Initialize ring parameters.
- * cw_min: 2^5 = 32.
- * cw_max: 2^10 = 1024.
- */
- ring_for_each(rt2x00dev, ring) {
- ring->rt2x00dev = rt2x00dev;
- ring->tx_params.aifs = 2;
- ring->tx_params.cw_min = 5;
- ring->tx_params.cw_max = 10;
- }
-
- return 0;
-}
-
-static void rt2x00lib_free_rings(struct rt2x00_dev *rt2x00dev)
-{
- kfree(rt2x00dev->rx);
- rt2x00dev->rx = NULL;
- rt2x00dev->tx = NULL;
- rt2x00dev->bcn = NULL;
-}
-
-int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev)
-{
- int retval = -ENOMEM;
-
- /*
- * Let the driver probe the device to detect the capabilities.
- */
- retval = rt2x00dev->ops->lib->probe_hw(rt2x00dev);
- if (retval) {
- ERROR(rt2x00dev, "Failed to allocate device.\n");
- goto exit;
- }
-
- /*
- * Initialize configuration work.
- */
- INIT_WORK(&rt2x00dev->beacon_work, rt2x00lib_beacondone_scheduled);
- INIT_WORK(&rt2x00dev->filter_work, rt2x00lib_packetfilter_scheduled);
- INIT_WORK(&rt2x00dev->config_work, rt2x00lib_configuration_scheduled);
- INIT_DELAYED_WORK(&rt2x00dev->link.work, rt2x00lib_link_tuner);
-
- /*
- * Reset current working type.
- */
- rt2x00dev->interface.type = INVALID_INTERFACE;
-
- /*
- * Allocate ring array.
- */
- retval = rt2x00lib_alloc_rings(rt2x00dev);
- if (retval)
- goto exit;
-
- /*
- * Initialize ieee80211 structure.
- */
- retval = rt2x00lib_probe_hw(rt2x00dev);
- if (retval) {
- ERROR(rt2x00dev, "Failed to initialize hw.\n");
- goto exit;
- }
-
- /*
- * Allocatie rfkill.
- */
- retval = rt2x00rfkill_allocate(rt2x00dev);
- if (retval)
- goto exit;
-
- /*
- * Open the debugfs entry.
- */
- rt2x00debug_register(rt2x00dev);
-
- __set_bit(DEVICE_PRESENT, &rt2x00dev->flags);
-
- return 0;
-
-exit:
- rt2x00lib_remove_dev(rt2x00dev);
-
- return retval;
-}
-EXPORT_SYMBOL_GPL(rt2x00lib_probe_dev);
-
-void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev)
-{
- __clear_bit(DEVICE_PRESENT, &rt2x00dev->flags);
-
- /*
- * Disable radio.
- */
- rt2x00lib_disable_radio(rt2x00dev);
-
- /*
- * Uninitialize device.
- */
- rt2x00lib_uninitialize(rt2x00dev);
-
- /*
- * Close debugfs entry.
- */
- rt2x00debug_deregister(rt2x00dev);
-
- /*
- * Free rfkill
- */
- rt2x00rfkill_free(rt2x00dev);
-
- /*
- * Free ieee80211_hw memory.
- */
- rt2x00lib_remove_hw(rt2x00dev);
-
- /*
- * Free firmware image.
- */
- rt2x00lib_free_firmware(rt2x00dev);
-
- /*
- * Free ring structures.
- */
- rt2x00lib_free_rings(rt2x00dev);
-}
-EXPORT_SYMBOL_GPL(rt2x00lib_remove_dev);
-
-/*
- * Device state handlers
- */
-#ifdef CONFIG_PM
-int rt2x00lib_suspend(struct rt2x00_dev *rt2x00dev, pm_message_t state)
-{
- int retval;
-
- NOTICE(rt2x00dev, "Going to sleep.\n");
- __clear_bit(DEVICE_PRESENT, &rt2x00dev->flags);
-
- /*
- * Only continue if mac80211 has open interfaces.
- */
- if (!test_bit(DEVICE_STARTED, &rt2x00dev->flags))
- goto exit;
- __set_bit(DEVICE_STARTED_SUSPEND, &rt2x00dev->flags);
-
- /*
- * Disable radio and unitialize all items
- * that must be recreated on resume.
- */
- rt2x00mac_stop(rt2x00dev->hw);
- rt2x00lib_uninitialize(rt2x00dev);
- rt2x00debug_deregister(rt2x00dev);
-
-exit:
- /*
- * Set device mode to sleep for power management.
- */
- retval = rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_SLEEP);
- if (retval)
- return retval;
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00lib_suspend);
-
-int rt2x00lib_resume(struct rt2x00_dev *rt2x00dev)
-{
- struct interface *intf = &rt2x00dev->interface;
- int retval;
-
- NOTICE(rt2x00dev, "Waking up.\n");
- __set_bit(DEVICE_PRESENT, &rt2x00dev->flags);
-
- /*
- * Open the debugfs entry.
- */
- rt2x00debug_register(rt2x00dev);
-
- /*
- * Only continue if mac80211 had open interfaces.
- */
- if (!__test_and_clear_bit(DEVICE_STARTED_SUSPEND, &rt2x00dev->flags))
- return 0;
-
- /*
- * Reinitialize device and all active interfaces.
- */
- retval = rt2x00mac_start(rt2x00dev->hw);
- if (retval)
- goto exit;
-
- /*
- * Reconfigure device.
- */
- rt2x00lib_config(rt2x00dev, &rt2x00dev->hw->conf, 1);
- if (!rt2x00dev->hw->conf.radio_enabled)
- rt2x00lib_disable_radio(rt2x00dev);
-
- rt2x00lib_config_mac_addr(rt2x00dev, intf->mac);
- rt2x00lib_config_bssid(rt2x00dev, intf->bssid);
- rt2x00lib_config_type(rt2x00dev, intf->type);
-
- /*
- * It is possible that during that mac80211 has attempted
- * to send frames while we were suspending or resuming.
- * In that case we have disabled the TX queue and should
- * now enable it again
- */
- ieee80211_start_queues(rt2x00dev->hw);
-
- /*
- * When in Master or Ad-hoc mode,
- * restart Beacon transmitting by faking a beacondone event.
- */
- if (intf->type == IEEE80211_IF_TYPE_AP ||
- intf->type == IEEE80211_IF_TYPE_IBSS)
- rt2x00lib_beacondone(rt2x00dev);
-
- return 0;
-
-exit:
- rt2x00lib_disable_radio(rt2x00dev);
- rt2x00lib_uninitialize(rt2x00dev);
- rt2x00debug_deregister(rt2x00dev);
-
- return retval;
-}
-EXPORT_SYMBOL_GPL(rt2x00lib_resume);
-#endif /* CONFIG_PM */
-
-/*
- * rt2x00lib module information.
- */
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("rt2x00 library");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00lib
- Abstract: Data structures for the rt2x00lib module.
- Supported chipsets: RT2460, RT2560, RT2570,
- rt2561, rt2561s, rt2661, rt2571W & rt2671.
- */
-
-#ifndef RT2X00DEV_H
-#define RT2X00DEV_H
-
-#include "rt2x00debug.h"
-#include "rt2x00firmware.h"
-#include "rt2x00rfkill.h"
-
-/*
- * Radio control.
- */
-int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_toggle_rx(struct rt2x00_dev *rt2x00dev, int enable);
-
-/*
- * Initialization/uninitialization handlers.
- */
-int rt2x00lib_initialize(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_uninitialize(struct rt2x00_dev *rt2x00dev);
-
-/*
- * Config handlers.
- */
-void rt2x00lib_config_type(struct rt2x00_dev *rt2x00dev, const int type);
-void rt2x00lib_config_phymode(struct rt2x00_dev *rt2x00dev, const int phymode);
-void rt2x00lib_config_channel(struct rt2x00_dev *rt2x00dev, const int value,
- const int channel, const int freq, const int txpower);
-void rt2x00lib_config_promisc(struct rt2x00_dev *rt2x00dev, const int promisc);
-void rt2x00lib_config_txpower(struct rt2x00_dev *rt2x00dev, const int txpower);
-void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx, const int antenna_rx);
-
-#endif /* RT2X00DEV_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00lib
- Abstract: rt2x00 firmware loading routines.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2x00lib"
-
-#include <linux/crc-itu-t.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include "rt2x00.h"
-#include "rt2x00lib.h"
-
-static int rt2x00lib_request_firmware(struct rt2x00_dev *rt2x00dev)
-{
- struct device *device = wiphy_dev(rt2x00dev->hw->wiphy);
- const struct firmware *fw;
- char *fw_name;
- int retval;
- u16 crc;
- u16 tmp;
-
- /*
- * Read correct firmware from harddisk.
- */
- fw_name = rt2x00dev->ops->lib->get_firmware_name(rt2x00dev);
- if (!fw_name) {
- ERROR(rt2x00dev,
- "Invalid firmware filename.\n"
- "Please file bug report to %s.\n", DRV_PROJECT);
- return -EINVAL;
- }
-
- INFO(rt2x00dev, "Loading firmware file '%s'.\n", fw_name);
-
- retval = request_firmware(&fw, fw_name, device);
- if (retval) {
- ERROR(rt2x00dev, "Failed to request Firmware.\n");
- return retval;
- }
-
- if (!fw || !fw->size || !fw->data) {
- ERROR(rt2x00dev, "Failed to read Firmware.\n");
- return -ENOENT;
- }
-
- /*
- * Validate the firmware using 16 bit CRC.
- * The last 2 bytes of the firmware are the CRC
- * so substract those 2 bytes from the CRC checksum,
- * and set those 2 bytes to 0 when calculating CRC.
- */
- tmp = 0;
- crc = crc_itu_t(0, fw->data, fw->size - 2);
- crc = crc_itu_t(crc, (u8 *)&tmp, 2);
-
- if (crc != (fw->data[fw->size - 2] << 8 | fw->data[fw->size - 1])) {
- ERROR(rt2x00dev, "Firmware CRC error.\n");
- retval = -ENOENT;
- goto exit;
- }
-
- INFO(rt2x00dev, "Firmware detected - version: %d.%d.\n",
- fw->data[fw->size - 4], fw->data[fw->size - 3]);
-
- rt2x00dev->fw = fw;
-
- return 0;
-
-exit:
- release_firmware(fw);
-
- return retval;
-}
-
-int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev)
-{
- int retval;
-
- if (!rt2x00dev->fw) {
- retval = rt2x00lib_request_firmware(rt2x00dev);
- if (retval)
- return retval;
- }
-
- /*
- * Send firmware to the device.
- */
- retval = rt2x00dev->ops->lib->load_firmware(rt2x00dev,
- rt2x00dev->fw->data,
- rt2x00dev->fw->size);
- return retval;
-}
-
-void rt2x00lib_free_firmware(struct rt2x00_dev *rt2x00dev)
-{
- release_firmware(rt2x00dev->fw);
- rt2x00dev->fw = NULL;
-}
-
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00lib
- Abstract: Data structures for the firmware loader.
- Supported chipsets: rt2561, rt2561s, rt2661, rt2571W & rt2671.
- */
-
-#ifndef RT2X00FIRMWARE_H
-#define RT2X00FIRMWARE_H
-
-#ifdef CONFIG_RT2X00_LIB_FIRMWARE
-int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev);
-int rt2x00lib_load_firmware_wait(struct rt2x00_dev *rt2x00dev);
-#else /* CONFIG_RT2X00_LIB_FIRMWARE */
-static inline int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev)
-{
- /*
- * This shouldn't happen.
- */
- BUG();
- return 0;
-}
-
-static inline int rt2x00lib_load_firmware_wait(struct rt2x00_dev *rt2x00dev)
-{
- return 0;
-}
-#endif /* CONFIG_RT2X00_LIB_FIRMWARE */
-
-#endif /* RT2X00FIRMWARE_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00lib
- Abstract: Data structures and definitions for the rt2x00lib module.
- */
-
-#ifndef RT2X00LIB_H
-#define RT2X00LIB_H
-
-/*
- * Interval defines
- * Both the link tuner as the rfkill will be called once per second.
- */
-#define LINK_TUNE_INTERVAL ( round_jiffies_relative(HZ) )
-#define RFKILL_POLL_INTERVAL ( 1000 )
-
-/*
- * Radio control handlers.
- */
-int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_toggle_rx(struct rt2x00_dev *rt2x00dev, enum dev_state state);
-void rt2x00lib_reset_link_tuner(struct rt2x00_dev *rt2x00dev);
-
-/*
- * Initialization handlers.
- */
-int rt2x00lib_initialize(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_uninitialize(struct rt2x00_dev *rt2x00dev);
-
-/*
- * Configuration handlers.
- */
-void rt2x00lib_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *mac);
-void rt2x00lib_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid);
-void rt2x00lib_config_type(struct rt2x00_dev *rt2x00dev, const int type);
-void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
- struct ieee80211_conf *conf, const int force_config);
-
-/*
- * Firmware handlers.
- */
-#ifdef CONFIG_RT2X00_LIB_FIRMWARE
-int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_free_firmware(struct rt2x00_dev *rt2x00dev);
-#else
-static inline int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev)
-{
- return 0;
-}
-static inline void rt2x00lib_free_firmware(struct rt2x00_dev *rt2x00dev)
-{
-}
-#endif /* CONFIG_RT2X00_LIB_FIRMWARE */
-
-/*
- * Debugfs handlers.
- */
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-void rt2x00debug_register(struct rt2x00_dev *rt2x00dev);
-void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev);
-#else
-static inline void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
-{
-}
-
-static inline void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev)
-{
-}
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
-/*
- * RFkill handlers.
- */
-#ifdef CONFIG_RT2X00_LIB_RFKILL
-int rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev);
-void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev);
-int rt2x00rfkill_allocate(struct rt2x00_dev *rt2x00dev);
-void rt2x00rfkill_free(struct rt2x00_dev *rt2x00dev);
-#else
-static inline int rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev)
-{
- return 0;
-}
-
-static inline void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev)
-{
-}
-
-static inline int rt2x00rfkill_allocate(struct rt2x00_dev *rt2x00dev)
-{
- return 0;
-}
-
-static inline void rt2x00rfkill_free(struct rt2x00_dev *rt2x00dev)
-{
-}
-#endif /* CONFIG_RT2X00_LIB_RFKILL */
-
-#endif /* RT2X00LIB_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00mac
- Abstract: rt2x00 generic mac80211 routines.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2x00lib"
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include "rt2x00.h"
-#include "rt2x00lib.h"
-
-static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring,
- struct sk_buff *frag_skb,
- struct ieee80211_tx_control *control)
-{
- struct sk_buff *skb;
- int size;
-
- if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
- size = sizeof(struct ieee80211_cts);
- else
- size = sizeof(struct ieee80211_rts);
-
- skb = dev_alloc_skb(size + rt2x00dev->hw->extra_tx_headroom);
- if (!skb) {
- WARNING(rt2x00dev, "Failed to create RTS/CTS frame.\n");
- return NETDEV_TX_BUSY;
- }
-
- skb_reserve(skb, rt2x00dev->hw->extra_tx_headroom);
- skb_put(skb, size);
-
- if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
- ieee80211_ctstoself_get(rt2x00dev->hw, rt2x00dev->interface.id,
- frag_skb->data, frag_skb->len, control,
- (struct ieee80211_cts *)(skb->data));
- else
- ieee80211_rts_get(rt2x00dev->hw, rt2x00dev->interface.id,
- frag_skb->data, frag_skb->len, control,
- (struct ieee80211_rts *)(skb->data));
-
- if (rt2x00dev->ops->lib->write_tx_data(rt2x00dev, ring, skb, control)) {
- WARNING(rt2x00dev, "Failed to send RTS/CTS frame.\n");
- return NETDEV_TX_BUSY;
- }
-
- return NETDEV_TX_OK;
-}
-
-int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
- struct ieee80211_tx_control *control)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
- struct data_ring *ring;
- u16 frame_control;
-
- /*
- * Mac80211 might be calling this function while we are trying
- * to remove the device or perhaps suspending it.
- * Note that we can only stop the TX queues inside the TX path
- * due to possible race conditions in mac80211.
- */
- if (!test_bit(DEVICE_PRESENT, &rt2x00dev->flags)) {
- ieee80211_stop_queues(hw);
- return 0;
- }
-
- /*
- * Determine which ring to put packet on.
- */
- ring = rt2x00lib_get_ring(rt2x00dev, control->queue);
- if (unlikely(!ring)) {
- ERROR(rt2x00dev,
- "Attempt to send packet over invalid queue %d.\n"
- "Please file bug report to %s.\n",
- control->queue, DRV_PROJECT);
- dev_kfree_skb_any(skb);
- return NETDEV_TX_OK;
- }
-
- /*
- * If CTS/RTS is required. and this frame is not CTS or RTS,
- * create and queue that frame first. But make sure we have
- * at least enough entries available to send this CTS/RTS
- * frame as well as the data frame.
- */
- frame_control = le16_to_cpu(ieee80211hdr->frame_control);
- if (!is_rts_frame(frame_control) && !is_cts_frame(frame_control) &&
- (control->flags & (IEEE80211_TXCTL_USE_RTS_CTS |
- IEEE80211_TXCTL_USE_CTS_PROTECT))) {
- if (rt2x00_ring_free(ring) <= 1)
- return NETDEV_TX_BUSY;
-
- if (rt2x00mac_tx_rts_cts(rt2x00dev, ring, skb, control))
- return NETDEV_TX_BUSY;
- }
-
- if (rt2x00dev->ops->lib->write_tx_data(rt2x00dev, ring, skb, control))
- return NETDEV_TX_BUSY;
-
- if (rt2x00dev->ops->lib->kick_tx_queue)
- rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
-
- return NETDEV_TX_OK;
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_tx);
-
-int rt2x00mac_start(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- int status;
-
- if (!test_bit(DEVICE_PRESENT, &rt2x00dev->flags) ||
- test_bit(DEVICE_STARTED, &rt2x00dev->flags))
- return 0;
-
- /*
- * If this is the first interface which is added,
- * we should load the firmware now.
- */
- if (test_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags)) {
- status = rt2x00lib_load_firmware(rt2x00dev);
- if (status)
- return status;
- }
-
- /*
- * Initialize the device.
- */
- status = rt2x00lib_initialize(rt2x00dev);
- if (status)
- return status;
-
- /*
- * Enable radio.
- */
- status = rt2x00lib_enable_radio(rt2x00dev);
- if (status) {
- rt2x00lib_uninitialize(rt2x00dev);
- return status;
- }
-
- __set_bit(DEVICE_STARTED, &rt2x00dev->flags);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_start);
-
-void rt2x00mac_stop(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- if (!test_bit(DEVICE_PRESENT, &rt2x00dev->flags))
- return;
-
- /*
- * Perhaps we can add something smarter here,
- * but for now just disabling the radio should do.
- */
- rt2x00lib_disable_radio(rt2x00dev);
-
- __clear_bit(DEVICE_STARTED, &rt2x00dev->flags);
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_stop);
-
-int rt2x00mac_add_interface(struct ieee80211_hw *hw,
- struct ieee80211_if_init_conf *conf)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct interface *intf = &rt2x00dev->interface;
-
- /* FIXME: Beaconing is broken in rt2x00. */
- if (conf->type == IEEE80211_IF_TYPE_IBSS ||
- conf->type == IEEE80211_IF_TYPE_AP) {
- ERROR(rt2x00dev,
- "rt2x00 does not support Adhoc or Master mode");
- return -EOPNOTSUPP;
- }
-
- /*
- * Don't allow interfaces to be added while
- * either the device has disappeared or when
- * another interface is already present.
- */
- if (!test_bit(DEVICE_PRESENT, &rt2x00dev->flags) ||
- is_interface_present(intf))
- return -ENOBUFS;
-
- intf->id = conf->if_id;
- intf->type = conf->type;
- if (conf->type == IEEE80211_IF_TYPE_AP)
- memcpy(&intf->bssid, conf->mac_addr, ETH_ALEN);
- memcpy(&intf->mac, conf->mac_addr, ETH_ALEN);
-
- /*
- * The MAC adddress must be configured after the device
- * has been initialized. Otherwise the device can reset
- * the MAC registers.
- */
- rt2x00lib_config_mac_addr(rt2x00dev, intf->mac);
- rt2x00lib_config_type(rt2x00dev, conf->type);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_add_interface);
-
-void rt2x00mac_remove_interface(struct ieee80211_hw *hw,
- struct ieee80211_if_init_conf *conf)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct interface *intf = &rt2x00dev->interface;
-
- /*
- * Don't allow interfaces to be remove while
- * either the device has disappeared or when
- * no interface is present.
- */
- if (!test_bit(DEVICE_PRESENT, &rt2x00dev->flags) ||
- !is_interface_present(intf))
- return;
-
- intf->id = 0;
- intf->type = INVALID_INTERFACE;
- memset(&intf->bssid, 0x00, ETH_ALEN);
- memset(&intf->mac, 0x00, ETH_ALEN);
-
- /*
- * Make sure the bssid and mac address registers
- * are cleared to prevent false ACKing of frames.
- */
- rt2x00lib_config_mac_addr(rt2x00dev, intf->mac);
- rt2x00lib_config_bssid(rt2x00dev, intf->bssid);
- rt2x00lib_config_type(rt2x00dev, intf->type);
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_remove_interface);
-
-int rt2x00mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- /*
- * Mac80211 might be calling this function while we are trying
- * to remove the device or perhaps suspending it.
- */
- if (!test_bit(DEVICE_PRESENT, &rt2x00dev->flags))
- return 0;
-
- /*
- * Check if we need to disable the radio,
- * if this is not the case, at least the RX must be disabled.
- */
- if (test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) {
- if (!conf->radio_enabled)
- rt2x00lib_disable_radio(rt2x00dev);
- else
- rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
- }
-
- rt2x00lib_config(rt2x00dev, conf, 0);
-
- /*
- * Reenable RX only if the radio should be on.
- */
- if (test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
- rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
- else if (conf->radio_enabled)
- return rt2x00lib_enable_radio(rt2x00dev);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_config);
-
-int rt2x00mac_config_interface(struct ieee80211_hw *hw, int if_id,
- struct ieee80211_if_conf *conf)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct interface *intf = &rt2x00dev->interface;
- int status;
-
- /*
- * Mac80211 might be calling this function while we are trying
- * to remove the device or perhaps suspending it.
- */
- if (!test_bit(DEVICE_PRESENT, &rt2x00dev->flags))
- return 0;
-
- /*
- * If the given type does not match the configured type,
- * there has been a problem.
- */
- if (conf->type != intf->type)
- return -EINVAL;
-
- /*
- * If the interface does not work in master mode,
- * then the bssid value in the interface structure
- * should now be set.
- */
- if (conf->type != IEEE80211_IF_TYPE_AP)
- memcpy(&intf->bssid, conf->bssid, ETH_ALEN);
- rt2x00lib_config_bssid(rt2x00dev, intf->bssid);
-
- /*
- * We only need to initialize the beacon when master mode is enabled.
- */
- if (conf->type != IEEE80211_IF_TYPE_AP || !conf->beacon)
- return 0;
-
- status = rt2x00dev->ops->hw->beacon_update(rt2x00dev->hw,
- conf->beacon,
- conf->beacon_control);
- if (status)
- dev_kfree_skb(conf->beacon);
-
- return status;
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_config_interface);
-
-int rt2x00mac_get_stats(struct ieee80211_hw *hw,
- struct ieee80211_low_level_stats *stats)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- /*
- * The dot11ACKFailureCount, dot11RTSFailureCount and
- * dot11RTSSuccessCount are updated in interrupt time.
- * dot11FCSErrorCount is updated in the link tuner.
- */
- memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats));
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_get_stats);
-
-int rt2x00mac_get_tx_stats(struct ieee80211_hw *hw,
- struct ieee80211_tx_queue_stats *stats)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- unsigned int i;
-
- for (i = 0; i < hw->queues; i++)
- memcpy(&stats->data[i], &rt2x00dev->tx[i].stats,
- sizeof(rt2x00dev->tx[i].stats));
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_get_tx_stats);
-
-void rt2x00mac_erp_ie_changed(struct ieee80211_hw *hw, u8 changes,
- int cts_protection, int preamble)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- int short_preamble;
- int ack_timeout;
- int ack_consume_time;
- int difs;
-
- /*
- * We only support changing preamble mode.
- */
- if (!(changes & IEEE80211_ERP_CHANGE_PREAMBLE))
- return;
-
- short_preamble = !preamble;
- preamble = !!(preamble) ? PREAMBLE : SHORT_PREAMBLE;
-
- difs = (hw->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
- SHORT_DIFS : DIFS;
- ack_timeout = difs + PLCP + preamble + get_duration(ACK_SIZE, 10);
-
- ack_consume_time = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
-
- if (short_preamble)
- __set_bit(CONFIG_SHORT_PREAMBLE, &rt2x00dev->flags);
- else
- __clear_bit(CONFIG_SHORT_PREAMBLE, &rt2x00dev->flags);
-
- rt2x00dev->ops->lib->config_preamble(rt2x00dev, short_preamble,
- ack_timeout, ack_consume_time);
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_erp_ie_changed);
-
-int rt2x00mac_conf_tx(struct ieee80211_hw *hw, int queue,
- const struct ieee80211_tx_queue_params *params)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct data_ring *ring;
-
- ring = rt2x00lib_get_ring(rt2x00dev, queue);
- if (unlikely(!ring))
- return -EINVAL;
-
- /*
- * The passed variables are stored as real value ((2^n)-1).
- * Ralink registers require to know the bit number 'n'.
- */
- if (params->cw_min)
- ring->tx_params.cw_min = fls(params->cw_min);
- else
- ring->tx_params.cw_min = 5; /* cw_min: 2^5 = 32. */
-
- if (params->cw_max)
- ring->tx_params.cw_max = fls(params->cw_max);
- else
- ring->tx_params.cw_max = 10; /* cw_min: 2^10 = 1024. */
-
- if (params->aifs)
- ring->tx_params.aifs = params->aifs;
- else
- ring->tx_params.aifs = 2;
-
- INFO(rt2x00dev,
- "Configured TX ring %d - CWmin: %d, CWmax: %d, Aifs: %d.\n",
- queue, ring->tx_params.cw_min, ring->tx_params.cw_max,
- ring->tx_params.aifs);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00mac_conf_tx);
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00pci
- Abstract: rt2x00 generic pci device routines.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2x00pci"
-
-#include <linux/dma-mapping.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-
-#include "rt2x00.h"
-#include "rt2x00pci.h"
-
-/*
- * Beacon handlers.
- */
-int rt2x00pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
- struct ieee80211_tx_control *control)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct data_ring *ring =
- rt2x00lib_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
- struct data_entry *entry = rt2x00_get_data_entry(ring);
-
- /*
- * Just in case mac80211 doesn't set this correctly,
- * but we need this queue set for the descriptor
- * initialization.
- */
- control->queue = IEEE80211_TX_QUEUE_BEACON;
-
- /*
- * Update the beacon entry.
- */
- memcpy(entry->data_addr, skb->data, skb->len);
- rt2x00lib_write_tx_desc(rt2x00dev, entry->priv,
- (struct ieee80211_hdr *)skb->data,
- skb->len, control);
-
- /*
- * Enable beacon generation.
- */
- rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_beacon_update);
-
-/*
- * TX data handlers.
- */
-int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring, struct sk_buff *skb,
- struct ieee80211_tx_control *control)
-{
- struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
- struct data_entry *entry = rt2x00_get_data_entry(ring);
- struct data_desc *txd = entry->priv;
- u32 word;
-
- if (rt2x00_ring_full(ring)) {
- ieee80211_stop_queue(rt2x00dev->hw, control->queue);
- return -EINVAL;
- }
-
- rt2x00_desc_read(txd, 0, &word);
-
- if (rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
- rt2x00_get_field32(word, TXD_ENTRY_VALID)) {
- ERROR(rt2x00dev,
- "Arrived at non-free entry in the non-full queue %d.\n"
- "Please file bug report to %s.\n",
- control->queue, DRV_PROJECT);
- ieee80211_stop_queue(rt2x00dev->hw, control->queue);
- return -EINVAL;
- }
-
- entry->skb = skb;
- memcpy(&entry->tx_status.control, control, sizeof(*control));
- memcpy(entry->data_addr, skb->data, skb->len);
- rt2x00lib_write_tx_desc(rt2x00dev, txd, ieee80211hdr,
- skb->len, control);
-
- rt2x00_ring_index_inc(ring);
-
- if (rt2x00_ring_full(ring))
- ieee80211_stop_queue(rt2x00dev->hw, control->queue);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);
-
-/*
- * RX data handlers.
- */
-void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring = rt2x00dev->rx;
- struct data_entry *entry;
- struct data_desc *rxd;
- struct sk_buff *skb;
- struct ieee80211_hdr *hdr;
- struct rxdata_entry_desc desc;
- int header_size;
- int align;
- u32 word;
-
- while (1) {
- entry = rt2x00_get_data_entry(ring);
- rxd = entry->priv;
- rt2x00_desc_read(rxd, 0, &word);
-
- if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
- break;
-
- memset(&desc, 0x00, sizeof(desc));
- rt2x00dev->ops->lib->fill_rxdone(entry, &desc);
-
- hdr = (struct ieee80211_hdr *)entry->data_addr;
- header_size =
- ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
-
- /*
- * The data behind the ieee80211 header must be
- * aligned on a 4 byte boundary.
- */
- align = header_size % 4;
-
- /*
- * Allocate the sk_buffer, initialize it and copy
- * all data into it.
- */
- skb = dev_alloc_skb(desc.size + align);
- if (!skb)
- return;
-
- skb_reserve(skb, align);
- memcpy(skb_put(skb, desc.size), entry->data_addr, desc.size);
-
- /*
- * Send the frame to rt2x00lib for further processing.
- */
- rt2x00lib_rxdone(entry, skb, &desc);
-
- if (test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags)) {
- rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
- rt2x00_desc_write(rxd, 0, word);
- }
-
- rt2x00_ring_index_inc(ring);
- }
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
-
-/*
- * Device initialization handlers.
- */
-#define priv_offset(__ring, __i) \
-({ \
- ring->data_addr + (i * ring->desc_size); \
-})
-
-#define data_addr_offset(__ring, __i) \
-({ \
- (__ring)->data_addr + \
- ((__ring)->stats.limit * (__ring)->desc_size) + \
- ((__i) * (__ring)->data_size); \
-})
-
-#define data_dma_offset(__ring, __i) \
-({ \
- (__ring)->data_dma + \
- ((__ring)->stats.limit * (__ring)->desc_size) + \
- ((__i) * (__ring)->data_size); \
-})
-
-static int rt2x00pci_alloc_dma(struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring)
-{
- unsigned int i;
-
- /*
- * Allocate DMA memory for descriptor and buffer.
- */
- ring->data_addr = pci_alloc_consistent(rt2x00dev_pci(rt2x00dev),
- rt2x00_get_ring_size(ring),
- &ring->data_dma);
- if (!ring->data_addr)
- return -ENOMEM;
-
- /*
- * Initialize all ring entries to contain valid
- * addresses.
- */
- for (i = 0; i < ring->stats.limit; i++) {
- ring->entry[i].priv = priv_offset(ring, i);
- ring->entry[i].data_addr = data_addr_offset(ring, i);
- ring->entry[i].data_dma = data_dma_offset(ring, i);
- }
-
- return 0;
-}
-
-static void rt2x00pci_free_dma(struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring)
-{
- if (ring->data_addr)
- pci_free_consistent(rt2x00dev_pci(rt2x00dev),
- rt2x00_get_ring_size(ring),
- ring->data_addr, ring->data_dma);
- ring->data_addr = NULL;
-}
-
-int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
-{
- struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
- struct data_ring *ring;
- int status;
-
- /*
- * Allocate DMA
- */
- ring_for_each(rt2x00dev, ring) {
- status = rt2x00pci_alloc_dma(rt2x00dev, ring);
- if (status)
- goto exit;
- }
-
- /*
- * Register interrupt handler.
- */
- status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
- IRQF_SHARED, pci_name(pci_dev), rt2x00dev);
- if (status) {
- ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
- pci_dev->irq, status);
- return status;
- }
-
- return 0;
-
-exit:
- rt2x00pci_uninitialize(rt2x00dev);
-
- return status;
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
-
-void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring;
-
- /*
- * Free irq line.
- */
- free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev);
-
- /*
- * Free DMA
- */
- ring_for_each(rt2x00dev, ring)
- rt2x00pci_free_dma(rt2x00dev, ring);
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
-
-/*
- * PCI driver handlers.
- */
-static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
-{
- kfree(rt2x00dev->rf);
- rt2x00dev->rf = NULL;
-
- kfree(rt2x00dev->eeprom);
- rt2x00dev->eeprom = NULL;
-
- if (rt2x00dev->csr_addr) {
- iounmap(rt2x00dev->csr_addr);
- rt2x00dev->csr_addr = NULL;
- }
-}
-
-static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
-{
- struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
-
- rt2x00dev->csr_addr = ioremap(pci_resource_start(pci_dev, 0),
- pci_resource_len(pci_dev, 0));
- if (!rt2x00dev->csr_addr)
- goto exit;
-
- rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
- if (!rt2x00dev->eeprom)
- goto exit;
-
- rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
- if (!rt2x00dev->rf)
- goto exit;
-
- return 0;
-
-exit:
- ERROR_PROBE("Failed to allocate registers.\n");
-
- rt2x00pci_free_reg(rt2x00dev);
-
- return -ENOMEM;
-}
-
-int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
-{
- struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
- struct ieee80211_hw *hw;
- struct rt2x00_dev *rt2x00dev;
- int retval;
-
- retval = pci_request_regions(pci_dev, pci_name(pci_dev));
- if (retval) {
- ERROR_PROBE("PCI request regions failed.\n");
- return retval;
- }
-
- retval = pci_enable_device(pci_dev);
- if (retval) {
- ERROR_PROBE("Enable device failed.\n");
- goto exit_release_regions;
- }
-
- pci_set_master(pci_dev);
-
- if (pci_set_mwi(pci_dev))
- ERROR_PROBE("MWI not available.\n");
-
- if (pci_set_dma_mask(pci_dev, DMA_64BIT_MASK) &&
- pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
- ERROR_PROBE("PCI DMA not supported.\n");
- retval = -EIO;
- goto exit_disable_device;
- }
-
- hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
- if (!hw) {
- ERROR_PROBE("Failed to allocate hardware.\n");
- retval = -ENOMEM;
- goto exit_disable_device;
- }
-
- pci_set_drvdata(pci_dev, hw);
-
- rt2x00dev = hw->priv;
- rt2x00dev->dev = pci_dev;
- rt2x00dev->ops = ops;
- rt2x00dev->hw = hw;
-
- retval = rt2x00pci_alloc_reg(rt2x00dev);
- if (retval)
- goto exit_free_device;
-
- retval = rt2x00lib_probe_dev(rt2x00dev);
- if (retval)
- goto exit_free_reg;
-
- return 0;
-
-exit_free_reg:
- rt2x00pci_free_reg(rt2x00dev);
-
-exit_free_device:
- ieee80211_free_hw(hw);
-
-exit_disable_device:
- if (retval != -EBUSY)
- pci_disable_device(pci_dev);
-
-exit_release_regions:
- pci_release_regions(pci_dev);
-
- pci_set_drvdata(pci_dev, NULL);
-
- return retval;
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_probe);
-
-void rt2x00pci_remove(struct pci_dev *pci_dev)
-{
- struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- /*
- * Free all allocated data.
- */
- rt2x00lib_remove_dev(rt2x00dev);
- rt2x00pci_free_reg(rt2x00dev);
- ieee80211_free_hw(hw);
-
- /*
- * Free the PCI device data.
- */
- pci_set_drvdata(pci_dev, NULL);
- pci_disable_device(pci_dev);
- pci_release_regions(pci_dev);
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_remove);
-
-#ifdef CONFIG_PM
-int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
-{
- struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
- struct rt2x00_dev *rt2x00dev = hw->priv;
- int retval;
-
- retval = rt2x00lib_suspend(rt2x00dev, state);
- if (retval)
- return retval;
-
- rt2x00pci_free_reg(rt2x00dev);
-
- pci_save_state(pci_dev);
- pci_disable_device(pci_dev);
- return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
-
-int rt2x00pci_resume(struct pci_dev *pci_dev)
-{
- struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
- struct rt2x00_dev *rt2x00dev = hw->priv;
- int retval;
-
- if (pci_set_power_state(pci_dev, PCI_D0) ||
- pci_enable_device(pci_dev) ||
- pci_restore_state(pci_dev)) {
- ERROR(rt2x00dev, "Failed to resume device.\n");
- return -EIO;
- }
-
- retval = rt2x00pci_alloc_reg(rt2x00dev);
- if (retval)
- return retval;
-
- retval = rt2x00lib_resume(rt2x00dev);
- if (retval)
- goto exit_free_reg;
-
- return 0;
-
-exit_free_reg:
- rt2x00pci_free_reg(rt2x00dev);
-
- return retval;
-}
-EXPORT_SYMBOL_GPL(rt2x00pci_resume);
-#endif /* CONFIG_PM */
-
-/*
- * rt2x00pci module information.
- */
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("rt2x00 library");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00pci
- Abstract: Data structures for the rt2x00pci module.
- */
-
-#ifndef RT2X00PCI_H
-#define RT2X00PCI_H
-
-#include <linux/io.h>
-
-/*
- * This variable should be used with the
- * pci_driver structure initialization.
- */
-#define PCI_DEVICE_DATA(__ops) .driver_data = (kernel_ulong_t)(__ops)
-
-/*
- * Register defines.
- * Some registers require multiple attempts before success,
- * in those cases REGISTER_BUSY_COUNT attempts should be
- * taken with a REGISTER_BUSY_DELAY interval.
- */
-#define REGISTER_BUSY_COUNT 5
-#define REGISTER_BUSY_DELAY 100
-
-/*
- * Descriptor availability flags.
- * All PCI device descriptors have these 2 flags
- * with the exact same definition.
- * By storing them here we can use them inside rt2x00pci
- * for some simple entry availability checking.
- */
-#define TXD_ENTRY_OWNER_NIC FIELD32(0x00000001)
-#define TXD_ENTRY_VALID FIELD32(0x00000002)
-#define RXD_ENTRY_OWNER_NIC FIELD32(0x00000001)
-
-/*
- * Register access.
- */
-static inline void rt2x00pci_register_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned long offset,
- u32 *value)
-{
- *value = readl(rt2x00dev->csr_addr + offset);
-}
-
-static inline void
-rt2x00pci_register_multiread(const struct rt2x00_dev *rt2x00dev,
- const unsigned long offset,
- void *value, const u16 length)
-{
- memcpy_fromio(value, rt2x00dev->csr_addr + offset, length);
-}
-
-static inline void rt2x00pci_register_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned long offset,
- u32 value)
-{
- writel(value, rt2x00dev->csr_addr + offset);
-}
-
-static inline void
-rt2x00pci_register_multiwrite(const struct rt2x00_dev *rt2x00dev,
- const unsigned long offset,
- void *value, const u16 length)
-{
- memcpy_toio(rt2x00dev->csr_addr + offset, value, length);
-}
-
-/*
- * Beacon handlers.
- */
-int rt2x00pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
- struct ieee80211_tx_control *control);
-
-/*
- * TX data handlers.
- */
-int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring, struct sk_buff *skb,
- struct ieee80211_tx_control *control);
-
-/*
- * RX data handlers.
- */
-void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev);
-
-/*
- * Device initialization handlers.
- */
-int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev);
-void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev);
-
-/*
- * PCI driver handlers.
- */
-int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id);
-void rt2x00pci_remove(struct pci_dev *pci_dev);
-#ifdef CONFIG_PM
-int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state);
-int rt2x00pci_resume(struct pci_dev *pci_dev);
-#else
-#define rt2x00pci_suspend NULL
-#define rt2x00pci_resume NULL
-#endif /* CONFIG_PM */
-
-#endif /* RT2X00PCI_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00
- Abstract: rt2x00 generic register information.
- */
-
-#ifndef RT2X00REG_H
-#define RT2X00REG_H
-
-/*
- * TX result flags.
- */
-enum TX_STATUS {
- TX_SUCCESS = 0,
- TX_SUCCESS_RETRY = 1,
- TX_FAIL_RETRY = 2,
- TX_FAIL_INVALID = 3,
- TX_FAIL_OTHER = 4,
-};
-
-/*
- * Antenna values
- */
-enum antenna {
- ANTENNA_SW_DIVERSITY = 0,
- ANTENNA_A = 1,
- ANTENNA_B = 2,
- ANTENNA_HW_DIVERSITY = 3,
-};
-
-/*
- * Led mode values.
- */
-enum led_mode {
- LED_MODE_DEFAULT = 0,
- LED_MODE_TXRX_ACTIVITY = 1,
- LED_MODE_SIGNAL_STRENGTH = 2,
- LED_MODE_ASUS = 3,
- LED_MODE_ALPHA = 4,
-};
-
-/*
- * TSF sync values
- */
-enum tsf_sync {
- TSF_SYNC_NONE = 0,
- TSF_SYNC_INFRA = 1,
- TSF_SYNC_BEACON = 2,
-};
-
-/*
- * Device states
- */
-enum dev_state {
- STATE_DEEP_SLEEP = 0,
- STATE_SLEEP = 1,
- STATE_STANDBY = 2,
- STATE_AWAKE = 3,
-
-/*
- * Additional device states, these values are
- * not strict since they are not directly passed
- * into the device.
- */
- STATE_RADIO_ON,
- STATE_RADIO_OFF,
- STATE_RADIO_RX_ON,
- STATE_RADIO_RX_OFF,
- STATE_RADIO_IRQ_ON,
- STATE_RADIO_IRQ_OFF,
-};
-
-/*
- * IFS backoff values
- */
-enum ifs {
- IFS_BACKOFF = 0,
- IFS_SIFS = 1,
- IFS_NEW_BACKOFF = 2,
- IFS_NONE = 3,
-};
-
-/*
- * Cipher types for hardware encryption
- */
-enum cipher {
- CIPHER_NONE = 0,
- CIPHER_WEP64 = 1,
- CIPHER_WEP128 = 2,
- CIPHER_TKIP = 3,
- CIPHER_AES = 4,
-/*
- * The following fields were added by rt61pci and rt73usb.
- */
- CIPHER_CKIP64 = 5,
- CIPHER_CKIP128 = 6,
- CIPHER_TKIP_NO_MIC = 7,
-};
-
-/*
- * Register handlers.
- * We store the position of a register field inside a field structure,
- * This will simplify the process of setting and reading a certain field
- * inside the register while making sure the process remains byte order safe.
- */
-struct rt2x00_field8 {
- u8 bit_offset;
- u8 bit_mask;
-};
-
-struct rt2x00_field16 {
- u16 bit_offset;
- u16 bit_mask;
-};
-
-struct rt2x00_field32 {
- u32 bit_offset;
- u32 bit_mask;
-};
-
-/*
- * Power of two check, this will check
- * if the mask that has been given contains
- * and contiguous set of bits.
- */
-#define is_power_of_two(x) ( !((x) & ((x)-1)) )
-#define low_bit_mask(x) ( ((x)-1) & ~(x) )
-#define is_valid_mask(x) is_power_of_two(1 + (x) + low_bit_mask(x))
-
-#define FIELD8(__mask) \
-({ \
- BUILD_BUG_ON(!(__mask) || \
- !is_valid_mask(__mask) || \
- (__mask) != (u8)(__mask)); \
- (struct rt2x00_field8) { \
- __ffs(__mask), (__mask) \
- }; \
-})
-
-#define FIELD16(__mask) \
-({ \
- BUILD_BUG_ON(!(__mask) || \
- !is_valid_mask(__mask) || \
- (__mask) != (u16)(__mask));\
- (struct rt2x00_field16) { \
- __ffs(__mask), (__mask) \
- }; \
-})
-
-#define FIELD32(__mask) \
-({ \
- BUILD_BUG_ON(!(__mask) || \
- !is_valid_mask(__mask) || \
- (__mask) != (u32)(__mask));\
- (struct rt2x00_field32) { \
- __ffs(__mask), (__mask) \
- }; \
-})
-
-static inline void rt2x00_set_field32(u32 *reg,
- const struct rt2x00_field32 field,
- const u32 value)
-{
- *reg &= ~(field.bit_mask);
- *reg |= (value << field.bit_offset) & field.bit_mask;
-}
-
-static inline u32 rt2x00_get_field32(const u32 reg,
- const struct rt2x00_field32 field)
-{
- return (reg & field.bit_mask) >> field.bit_offset;
-}
-
-static inline void rt2x00_set_field16(u16 *reg,
- const struct rt2x00_field16 field,
- const u16 value)
-{
- *reg &= ~(field.bit_mask);
- *reg |= (value << field.bit_offset) & field.bit_mask;
-}
-
-static inline u16 rt2x00_get_field16(const u16 reg,
- const struct rt2x00_field16 field)
-{
- return (reg & field.bit_mask) >> field.bit_offset;
-}
-
-static inline void rt2x00_set_field8(u8 *reg,
- const struct rt2x00_field8 field,
- const u8 value)
-{
- *reg &= ~(field.bit_mask);
- *reg |= (value << field.bit_offset) & field.bit_mask;
-}
-
-static inline u8 rt2x00_get_field8(const u8 reg,
- const struct rt2x00_field8 field)
-{
- return (reg & field.bit_mask) >> field.bit_offset;
-}
-
-/*
- * Device specific rate value.
- * We will have to create the device specific rate value
- * passed to the ieee80211 kernel. We need to make it a consist of
- * multiple fields because we want to store more then 1 device specific
- * values inside the value.
- * 1 - rate, stored as 100 kbit/s.
- * 2 - preamble, short_preamble enabled flag.
- * 3 - MASK_RATE, which rates are enabled in this mode, this mask
- * corresponds with the TX register format for the current device.
- * 4 - plcp, 802.11b rates are device specific,
- * 802.11g rates are set according to the ieee802.11a-1999 p.14.
- * The bit to enable preamble is set in a seperate define.
- */
-#define DEV_RATE FIELD32(0x000007ff)
-#define DEV_PREAMBLE FIELD32(0x00000800)
-#define DEV_RATEMASK FIELD32(0x00fff000)
-#define DEV_PLCP FIELD32(0xff000000)
-
-/*
- * Bitfields
- */
-#define DEV_RATEBIT_1MB ( 1 << 0 )
-#define DEV_RATEBIT_2MB ( 1 << 1 )
-#define DEV_RATEBIT_5_5MB ( 1 << 2 )
-#define DEV_RATEBIT_11MB ( 1 << 3 )
-#define DEV_RATEBIT_6MB ( 1 << 4 )
-#define DEV_RATEBIT_9MB ( 1 << 5 )
-#define DEV_RATEBIT_12MB ( 1 << 6 )
-#define DEV_RATEBIT_18MB ( 1 << 7 )
-#define DEV_RATEBIT_24MB ( 1 << 8 )
-#define DEV_RATEBIT_36MB ( 1 << 9 )
-#define DEV_RATEBIT_48MB ( 1 << 10 )
-#define DEV_RATEBIT_54MB ( 1 << 11 )
-
-/*
- * Bitmasks for DEV_RATEMASK
- */
-#define DEV_RATEMASK_1MB ( (DEV_RATEBIT_1MB << 1) -1 )
-#define DEV_RATEMASK_2MB ( (DEV_RATEBIT_2MB << 1) -1 )
-#define DEV_RATEMASK_5_5MB ( (DEV_RATEBIT_5_5MB << 1) -1 )
-#define DEV_RATEMASK_11MB ( (DEV_RATEBIT_11MB << 1) -1 )
-#define DEV_RATEMASK_6MB ( (DEV_RATEBIT_6MB << 1) -1 )
-#define DEV_RATEMASK_9MB ( (DEV_RATEBIT_9MB << 1) -1 )
-#define DEV_RATEMASK_12MB ( (DEV_RATEBIT_12MB << 1) -1 )
-#define DEV_RATEMASK_18MB ( (DEV_RATEBIT_18MB << 1) -1 )
-#define DEV_RATEMASK_24MB ( (DEV_RATEBIT_24MB << 1) -1 )
-#define DEV_RATEMASK_36MB ( (DEV_RATEBIT_36MB << 1) -1 )
-#define DEV_RATEMASK_48MB ( (DEV_RATEBIT_48MB << 1) -1 )
-#define DEV_RATEMASK_54MB ( (DEV_RATEBIT_54MB << 1) -1 )
-
-/*
- * Bitmask groups of bitrates
- */
-#define DEV_BASIC_RATEMASK \
- ( DEV_RATEMASK_11MB | \
- DEV_RATEBIT_6MB | DEV_RATEBIT_12MB | DEV_RATEBIT_24MB )
-
-#define DEV_CCK_RATEMASK ( DEV_RATEMASK_11MB )
-#define DEV_OFDM_RATEMASK ( DEV_RATEMASK_54MB & ~DEV_CCK_RATEMASK )
-
-/*
- * Macro's to set and get specific fields from the device specific val and val2
- * fields inside the ieee80211_rate entry.
- */
-#define DEVICE_SET_RATE_FIELD(__value, __mask) \
- (int)( ((__value) << DEV_##__mask.bit_offset) & DEV_##__mask.bit_mask )
-
-#define DEVICE_GET_RATE_FIELD(__value, __mask) \
- (int)( ((__value) & DEV_##__mask.bit_mask) >> DEV_##__mask.bit_offset )
-
-#endif /* RT2X00REG_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00rfkill
- Abstract: rt2x00 rfkill routines.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2x00lib"
-
-#include <linux/input-polldev.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/rfkill.h>
-
-#include "rt2x00.h"
-#include "rt2x00lib.h"
-
-static int rt2x00rfkill_toggle_radio(void *data, enum rfkill_state state)
-{
- struct rt2x00_dev *rt2x00dev = data;
- int retval = 0;
-
- if (unlikely(!rt2x00dev))
- return 0;
-
- /*
- * Only continue if there are enabled interfaces.
- */
- if (!test_bit(DEVICE_STARTED, &rt2x00dev->flags))
- return 0;
-
- if (state == RFKILL_STATE_ON) {
- INFO(rt2x00dev, "Hardware button pressed, enabling radio.\n");
- __clear_bit(DEVICE_DISABLED_RADIO_HW, &rt2x00dev->flags);
- retval = rt2x00lib_enable_radio(rt2x00dev);
- } else if (state == RFKILL_STATE_OFF) {
- INFO(rt2x00dev, "Hardware button pressed, disabling radio.\n");
- __set_bit(DEVICE_DISABLED_RADIO_HW, &rt2x00dev->flags);
- rt2x00lib_disable_radio(rt2x00dev);
- }
-
- return retval;
-}
-
-static void rt2x00rfkill_poll(struct input_polled_dev *poll_dev)
-{
- struct rt2x00_dev *rt2x00dev = poll_dev->private;
- int state = rt2x00dev->ops->lib->rfkill_poll(rt2x00dev);
-
- if (rt2x00dev->rfkill->state != state)
- input_report_key(poll_dev->input, KEY_WLAN, 1);
-}
-
-int rt2x00rfkill_register(struct rt2x00_dev *rt2x00dev)
-{
- int retval;
-
- if (!test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags))
- return 0;
-
- retval = rfkill_register(rt2x00dev->rfkill);
- if (retval) {
- ERROR(rt2x00dev, "Failed to register rfkill handler.\n");
- return retval;
- }
-
- retval = input_register_polled_device(rt2x00dev->poll_dev);
- if (retval) {
- ERROR(rt2x00dev, "Failed to register polled device.\n");
- rfkill_unregister(rt2x00dev->rfkill);
- return retval;
- }
-
- return 0;
-}
-
-void rt2x00rfkill_unregister(struct rt2x00_dev *rt2x00dev)
-{
- if (!test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags))
- return;
-
- input_unregister_polled_device(rt2x00dev->poll_dev);
- rfkill_unregister(rt2x00dev->rfkill);
-}
-
-int rt2x00rfkill_allocate(struct rt2x00_dev *rt2x00dev)
-{
- struct device *device = wiphy_dev(rt2x00dev->hw->wiphy);
-
- if (!test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags))
- return 0;
-
- rt2x00dev->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
- if (!rt2x00dev->rfkill) {
- ERROR(rt2x00dev, "Failed to allocate rfkill handler.\n");
- return -ENOMEM;
- }
-
- rt2x00dev->rfkill->name = rt2x00dev->ops->name;
- rt2x00dev->rfkill->data = rt2x00dev;
- rt2x00dev->rfkill->state = rt2x00dev->ops->lib->rfkill_poll(rt2x00dev);
- rt2x00dev->rfkill->toggle_radio = rt2x00rfkill_toggle_radio;
-
- rt2x00dev->poll_dev = input_allocate_polled_device();
- if (!rt2x00dev->poll_dev) {
- ERROR(rt2x00dev, "Failed to allocate polled device.\n");
- rfkill_free(rt2x00dev->rfkill);
- return -ENOMEM;
- }
-
- rt2x00dev->poll_dev->private = rt2x00dev;
- rt2x00dev->poll_dev->poll = rt2x00rfkill_poll;
- rt2x00dev->poll_dev->poll_interval = RFKILL_POLL_INTERVAL;
-
- return 0;
-}
-
-void rt2x00rfkill_free(struct rt2x00_dev *rt2x00dev)
-{
- if (!test_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags))
- return;
-
- input_free_polled_device(rt2x00dev->poll_dev);
- rfkill_free(rt2x00dev->rfkill);
-}
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00lib
- Abstract: Data structures for the rfkill.
- Supported chipsets: RT2460, RT2560, rt2561, rt2561s, rt2661.
- */
-
-#ifndef RT2X00RFKILL_H
-#define RT2X00RFKILL_H
-
-#ifdef CONFIG_RT2X00_LIB_RFKILL
-int rt2x00lib_register_rfkill(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_unregister_rfkill(struct rt2x00_dev *rt2x00dev);
-int rt2x00lib_allocate_rfkill(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_free_rfkill(struct rt2x00_dev *rt2x00dev);
-#else /* CONFIG_RT2X00_LIB_RFKILL */
-static inline int rt2x00lib_register_rfkill(struct rt2x00_dev *rt2x00dev)
-{
- return 0;
-}
-
-static inline void rt2x00lib_unregister_rfkill(struct rt2x00_dev *rt2x00dev){}
-
-static inline int rt2x00lib_allocate_rfkill(struct rt2x00_dev *rt2x00dev)
-{
- return 0;
-}
-
-static inline void rt2x00lib_free_rfkill(struct rt2x00_dev *rt2x00dev){}
-#endif /* CONFIG_RT2X00_LIB_RFKILL */
-
-#endif /* RT2X00RFKILL_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00
- Abstract: rt2x00 ring datastructures and routines
- */
-
-#ifndef RT2X00RING_H
-#define RT2X00RING_H
-
-/*
- * data_desc
- * Each data entry also contains a descriptor which is used by the
- * device to determine what should be done with the packet and
- * what the current status is.
- * This structure is greatly simplified, but the descriptors
- * are basically a list of little endian 32 bit values.
- * Make the array by default 1 word big, this will allow us
- * to use sizeof() correctly.
- */
-struct data_desc {
- __le32 word[1];
-};
-
-/*
- * rxdata_entry_desc
- * Summary of information that has been read from the
- * RX frame descriptor.
- */
-struct rxdata_entry_desc {
- int signal;
- int rssi;
- int ofdm;
- int size;
- int flags;
-};
-
-/*
- * txdata_entry_desc
- * Summary of information that should be written into the
- * descriptor for sending a TX frame.
- */
-struct txdata_entry_desc {
- unsigned long flags;
-#define ENTRY_TXDONE 1
-#define ENTRY_TXD_RTS_FRAME 2
-#define ENTRY_TXD_OFDM_RATE 3
-#define ENTRY_TXD_MORE_FRAG 4
-#define ENTRY_TXD_REQ_TIMESTAMP 5
-#define ENTRY_TXD_BURST 6
-
-/*
- * Queue ID. ID's 0-4 are data TX rings
- */
- int queue;
-#define QUEUE_MGMT 13
-#define QUEUE_RX 14
-#define QUEUE_OTHER 15
-
- /*
- * PLCP values.
- */
- u16 length_high;
- u16 length_low;
- u16 signal;
- u16 service;
-
- /*
- * Timing information
- */
- int aifs;
- int ifs;
- int cw_min;
- int cw_max;
-};
-
-/*
- * data_entry
- * The data ring is a list of data entries.
- * Each entry holds a reference to the descriptor
- * and the data buffer. For TX rings the reference to the
- * sk_buff of the packet being transmitted is also stored here.
- */
-struct data_entry {
- /*
- * Status flags
- */
- unsigned long flags;
-#define ENTRY_OWNER_NIC 1
-
- /*
- * Ring we belong to.
- */
- struct data_ring *ring;
-
- /*
- * sk_buff for the packet which is being transmitted
- * in this entry (Only used with TX related rings).
- */
- struct sk_buff *skb;
-
- /*
- * Store a ieee80211_tx_status structure in each
- * ring entry, this will optimize the txdone
- * handler.
- */
- struct ieee80211_tx_status tx_status;
-
- /*
- * private pointer specific to driver.
- */
- void *priv;
-
- /*
- * Data address for this entry.
- */
- void *data_addr;
- dma_addr_t data_dma;
-};
-
-/*
- * data_ring
- * Data rings are used by the device to send and receive packets.
- * The data_addr is the base address of the data memory.
- * To determine at which point in the ring we are,
- * have to use the rt2x00_ring_index_*() functions.
- */
-struct data_ring {
- /*
- * Pointer to main rt2x00dev structure where this
- * ring belongs to.
- */
- struct rt2x00_dev *rt2x00dev;
-
- /*
- * Base address for the device specific data entries.
- */
- struct data_entry *entry;
-
- /*
- * TX queue statistic info.
- */
- struct ieee80211_tx_queue_stats_data stats;
-
- /*
- * TX Queue parameters.
- */
- struct ieee80211_tx_queue_params tx_params;
-
- /*
- * Base address for data ring.
- */
- dma_addr_t data_dma;
- void *data_addr;
-
- /*
- * Index variables.
- */
- u16 index;
- u16 index_done;
-
- /*
- * Size of packet and descriptor in bytes.
- */
- u16 data_size;
- u16 desc_size;
-};
-
-/*
- * Handlers to determine the address of the current device specific
- * data entry, where either index or index_done points to.
- */
-static inline struct data_entry *rt2x00_get_data_entry(struct data_ring *ring)
-{
- return &ring->entry[ring->index];
-}
-
-static inline struct data_entry *rt2x00_get_data_entry_done(struct data_ring
- *ring)
-{
- return &ring->entry[ring->index_done];
-}
-
-/*
- * Total ring memory
- */
-static inline int rt2x00_get_ring_size(struct data_ring *ring)
-{
- return ring->stats.limit * (ring->desc_size + ring->data_size);
-}
-
-/*
- * Ring index manipulation functions.
- */
-static inline void rt2x00_ring_index_inc(struct data_ring *ring)
-{
- ring->index++;
- if (ring->index >= ring->stats.limit)
- ring->index = 0;
- ring->stats.len++;
-}
-
-static inline void rt2x00_ring_index_done_inc(struct data_ring *ring)
-{
- ring->index_done++;
- if (ring->index_done >= ring->stats.limit)
- ring->index_done = 0;
- ring->stats.len--;
- ring->stats.count++;
-}
-
-static inline void rt2x00_ring_index_clear(struct data_ring *ring)
-{
- ring->index = 0;
- ring->index_done = 0;
- ring->stats.len = 0;
- ring->stats.count = 0;
-}
-
-static inline int rt2x00_ring_empty(struct data_ring *ring)
-{
- return ring->stats.len == 0;
-}
-
-static inline int rt2x00_ring_full(struct data_ring *ring)
-{
- return ring->stats.len == ring->stats.limit;
-}
-
-static inline int rt2x00_ring_free(struct data_ring *ring)
-{
- return ring->stats.limit - ring->stats.len;
-}
-
-/*
- * TX/RX Descriptor access functions.
- */
-static inline void rt2x00_desc_read(struct data_desc *desc,
- const u8 word, u32 *value)
-{
- *value = le32_to_cpu(desc->word[word]);
-}
-
-static inline void rt2x00_desc_write(struct data_desc *desc,
- const u8 word, const u32 value)
-{
- desc->word[word] = cpu_to_le32(value);
-}
-
-#endif /* RT2X00RING_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00usb
- Abstract: rt2x00 generic usb device routines.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2x00usb"
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/usb.h>
-
-#include "rt2x00.h"
-#include "rt2x00usb.h"
-
-/*
- * Interfacing with the HW.
- */
-int rt2x00usb_vendor_request(const struct rt2x00_dev *rt2x00dev,
- const u8 request, const u8 requesttype,
- const u16 offset, const u16 value,
- void *buffer, const u16 buffer_length,
- const int timeout)
-{
- struct usb_device *usb_dev =
- interface_to_usbdev(rt2x00dev_usb(rt2x00dev));
- int status;
- unsigned int i;
- unsigned int pipe =
- (requesttype == USB_VENDOR_REQUEST_IN) ?
- usb_rcvctrlpipe(usb_dev, 0) : usb_sndctrlpipe(usb_dev, 0);
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- status = usb_control_msg(usb_dev, pipe, request, requesttype,
- value, offset, buffer, buffer_length,
- timeout);
- if (status >= 0)
- return 0;
-
- /*
- * Check for errors
- * -ENODEV: Device has disappeared, no point continuing.
- * All other errors: Try again.
- */
- else if (status == -ENODEV)
- break;
- }
-
- ERROR(rt2x00dev,
- "Vendor Request 0x%02x failed for offset 0x%04x with error %d.\n",
- request, offset, status);
-
- return status;
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_vendor_request);
-
-int rt2x00usb_vendor_request_buff(const struct rt2x00_dev *rt2x00dev,
- const u8 request, const u8 requesttype,
- const u16 offset, void *buffer,
- const u16 buffer_length, const int timeout)
-{
- int status;
-
- /*
- * Check for Cache availability.
- */
- if (unlikely(!rt2x00dev->csr_cache || buffer_length > CSR_CACHE_SIZE)) {
- ERROR(rt2x00dev, "CSR cache not available.\n");
- return -ENOMEM;
- }
-
- if (requesttype == USB_VENDOR_REQUEST_OUT)
- memcpy(rt2x00dev->csr_cache, buffer, buffer_length);
-
- status = rt2x00usb_vendor_request(rt2x00dev, request, requesttype,
- offset, 0, rt2x00dev->csr_cache,
- buffer_length, timeout);
-
- if (!status && requesttype == USB_VENDOR_REQUEST_IN)
- memcpy(buffer, rt2x00dev->csr_cache, buffer_length);
-
- return status;
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_vendor_request_buff);
-
-/*
- * TX data handlers.
- */
-static void rt2x00usb_interrupt_txdone(struct urb *urb)
-{
- struct data_entry *entry = (struct data_entry *)urb->context;
- struct data_ring *ring = entry->ring;
- struct rt2x00_dev *rt2x00dev = ring->rt2x00dev;
- struct data_desc *txd = (struct data_desc *)entry->skb->data;
- u32 word;
- int tx_status;
-
- if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags) ||
- !__test_and_clear_bit(ENTRY_OWNER_NIC, &entry->flags))
- return;
-
- rt2x00_desc_read(txd, 0, &word);
-
- /*
- * Remove the descriptor data from the buffer.
- */
- skb_pull(entry->skb, ring->desc_size);
-
- /*
- * Obtain the status about this packet.
- */
- tx_status = !urb->status ? TX_SUCCESS : TX_FAIL_RETRY;
-
- rt2x00lib_txdone(entry, tx_status, 0);
-
- /*
- * Make this entry available for reuse.
- */
- entry->flags = 0;
- rt2x00_ring_index_done_inc(entry->ring);
-
- /*
- * If the data ring was full before the txdone handler
- * we must make sure the packet queue in the mac80211 stack
- * is reenabled when the txdone handler has finished.
- */
- if (!rt2x00_ring_full(ring))
- ieee80211_wake_queue(rt2x00dev->hw,
- entry->tx_status.control.queue);
-}
-
-int rt2x00usb_write_tx_data(struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring, struct sk_buff *skb,
- struct ieee80211_tx_control *control)
-{
- struct usb_device *usb_dev =
- interface_to_usbdev(rt2x00dev_usb(rt2x00dev));
- struct data_entry *entry = rt2x00_get_data_entry(ring);
- int pipe = usb_sndbulkpipe(usb_dev, 1);
- u32 length;
-
- if (rt2x00_ring_full(ring)) {
- ieee80211_stop_queue(rt2x00dev->hw, control->queue);
- return -EINVAL;
- }
-
- if (test_bit(ENTRY_OWNER_NIC, &entry->flags)) {
- ERROR(rt2x00dev,
- "Arrived at non-free entry in the non-full queue %d.\n"
- "Please file bug report to %s.\n",
- control->queue, DRV_PROJECT);
- ieee80211_stop_queue(rt2x00dev->hw, control->queue);
- return -EINVAL;
- }
-
- /*
- * Add the descriptor in front of the skb.
- */
- skb_push(skb, ring->desc_size);
- memset(skb->data, 0, ring->desc_size);
-
- rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
- (struct ieee80211_hdr *)(skb->data +
- ring->desc_size),
- skb->len - ring->desc_size, control);
- memcpy(&entry->tx_status.control, control, sizeof(*control));
- entry->skb = skb;
-
- /*
- * USB devices cannot blindly pass the skb->len as the
- * length of the data to usb_fill_bulk_urb. Pass the skb
- * to the driver to determine what the length should be.
- */
- length = rt2x00dev->ops->lib->get_tx_data_len(rt2x00dev, skb);
-
- /*
- * Initialize URB and send the frame to the device.
- */
- __set_bit(ENTRY_OWNER_NIC, &entry->flags);
- usb_fill_bulk_urb(entry->priv, usb_dev, pipe,
- skb->data, length, rt2x00usb_interrupt_txdone, entry);
- usb_submit_urb(entry->priv, GFP_ATOMIC);
-
- rt2x00_ring_index_inc(ring);
-
- if (rt2x00_ring_full(ring))
- ieee80211_stop_queue(rt2x00dev->hw, control->queue);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_write_tx_data);
-
-/*
- * RX data handlers.
- */
-static void rt2x00usb_interrupt_rxdone(struct urb *urb)
-{
- struct data_entry *entry = (struct data_entry *)urb->context;
- struct data_ring *ring = entry->ring;
- struct rt2x00_dev *rt2x00dev = ring->rt2x00dev;
- struct sk_buff *skb;
- struct ieee80211_hdr *hdr;
- struct rxdata_entry_desc desc;
- int header_size;
- int frame_size;
-
- if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags) ||
- !test_and_clear_bit(ENTRY_OWNER_NIC, &entry->flags))
- return;
-
- /*
- * Check if the received data is simply too small
- * to be actually valid, or if the urb is signaling
- * a problem.
- */
- if (urb->actual_length < entry->ring->desc_size || urb->status)
- goto skip_entry;
-
- memset(&desc, 0x00, sizeof(desc));
- rt2x00dev->ops->lib->fill_rxdone(entry, &desc);
-
- /*
- * Allocate a new sk buffer to replace the current one.
- * If allocation fails, we should drop the current frame
- * so we can recycle the existing sk buffer for the new frame.
- * As alignment we use 2 and not NET_IP_ALIGN because we need
- * to be sure we have 2 bytes room in the head. (NET_IP_ALIGN
- * can be 0 on some hardware). We use these 2 bytes for frame
- * alignment later, we assume that the chance that
- * header_size % 4 == 2 is bigger then header_size % 2 == 0
- * and thus optimize alignment by reserving the 2 bytes in
- * advance.
- */
- frame_size = entry->ring->data_size + entry->ring->desc_size;
- skb = dev_alloc_skb(frame_size + 2);
- if (!skb)
- goto skip_entry;
-
- skb_reserve(skb, 2);
- skb_put(skb, frame_size);
-
- /*
- * The data behind the ieee80211 header must be
- * aligned on a 4 byte boundary.
- * After that trim the entire buffer down to only
- * contain the valid frame data excluding the device
- * descriptor.
- */
- hdr = (struct ieee80211_hdr *)entry->skb->data;
- header_size =
- ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
-
- if (header_size % 4 == 0) {
- skb_push(entry->skb, 2);
- memmove(entry->skb->data, entry->skb->data + 2, skb->len - 2);
- }
- skb_trim(entry->skb, desc.size);
-
- /*
- * Send the frame to rt2x00lib for further processing.
- */
- rt2x00lib_rxdone(entry, entry->skb, &desc);
-
- /*
- * Replace current entry's skb with the newly allocated one,
- * and reinitialize the urb.
- */
- entry->skb = skb;
- urb->transfer_buffer = entry->skb->data;
- urb->transfer_buffer_length = entry->skb->len;
-
-skip_entry:
- if (test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags)) {
- __set_bit(ENTRY_OWNER_NIC, &entry->flags);
- usb_submit_urb(urb, GFP_ATOMIC);
- }
-
- rt2x00_ring_index_inc(ring);
-}
-
-/*
- * Radio handlers
- */
-void rt2x00usb_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
- struct usb_device *usb_dev =
- interface_to_usbdev(rt2x00dev_usb(rt2x00dev));
- struct data_ring *ring;
- struct data_entry *entry;
- unsigned int i;
-
- /*
- * Initialize the TX rings
- */
- txringall_for_each(rt2x00dev, ring) {
- for (i = 0; i < ring->stats.limit; i++)
- ring->entry[i].flags = 0;
-
- rt2x00_ring_index_clear(ring);
- }
-
- /*
- * Initialize and start the RX ring.
- */
- rt2x00_ring_index_clear(rt2x00dev->rx);
-
- for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
- entry = &rt2x00dev->rx->entry[i];
-
- usb_fill_bulk_urb(entry->priv, usb_dev,
- usb_rcvbulkpipe(usb_dev, 1),
- entry->skb->data, entry->skb->len,
- rt2x00usb_interrupt_rxdone, entry);
-
- __set_bit(ENTRY_OWNER_NIC, &entry->flags);
- usb_submit_urb(entry->priv, GFP_ATOMIC);
- }
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_enable_radio);
-
-void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring;
- unsigned int i;
-
- rt2x00usb_vendor_request_sw(rt2x00dev, USB_RX_CONTROL, 0x0000, 0x0000,
- REGISTER_TIMEOUT);
-
- /*
- * Cancel all rings.
- */
- ring_for_each(rt2x00dev, ring) {
- for (i = 0; i < ring->stats.limit; i++)
- usb_kill_urb(ring->entry[i].priv);
- }
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio);
-
-/*
- * Device initialization handlers.
- */
-static int rt2x00usb_alloc_urb(struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring)
-{
- unsigned int i;
-
- /*
- * Allocate the URB's
- */
- for (i = 0; i < ring->stats.limit; i++) {
- ring->entry[i].priv = usb_alloc_urb(0, GFP_KERNEL);
- if (!ring->entry[i].priv)
- return -ENOMEM;
- }
-
- return 0;
-}
-
-static void rt2x00usb_free_urb(struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring)
-{
- unsigned int i;
-
- if (!ring->entry)
- return;
-
- for (i = 0; i < ring->stats.limit; i++) {
- usb_kill_urb(ring->entry[i].priv);
- usb_free_urb(ring->entry[i].priv);
- if (ring->entry[i].skb)
- kfree_skb(ring->entry[i].skb);
- }
-}
-
-int rt2x00usb_initialize(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring;
- struct sk_buff *skb;
- unsigned int entry_size;
- unsigned int i;
- int status;
-
- /*
- * Allocate DMA
- */
- ring_for_each(rt2x00dev, ring) {
- status = rt2x00usb_alloc_urb(rt2x00dev, ring);
- if (status)
- goto exit;
- }
-
- /*
- * For the RX ring, skb's should be allocated.
- */
- entry_size = rt2x00dev->rx->data_size + rt2x00dev->rx->desc_size;
- for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
- skb = dev_alloc_skb(NET_IP_ALIGN + entry_size);
- if (!skb)
- goto exit;
-
- skb_reserve(skb, NET_IP_ALIGN);
- skb_put(skb, entry_size);
-
- rt2x00dev->rx->entry[i].skb = skb;
- }
-
- return 0;
-
-exit:
- rt2x00usb_uninitialize(rt2x00dev);
-
- return status;
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_initialize);
-
-void rt2x00usb_uninitialize(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring;
-
- ring_for_each(rt2x00dev, ring)
- rt2x00usb_free_urb(rt2x00dev, ring);
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_uninitialize);
-
-/*
- * USB driver handlers.
- */
-static void rt2x00usb_free_reg(struct rt2x00_dev *rt2x00dev)
-{
- kfree(rt2x00dev->rf);
- rt2x00dev->rf = NULL;
-
- kfree(rt2x00dev->eeprom);
- rt2x00dev->eeprom = NULL;
-
- kfree(rt2x00dev->csr_cache);
- rt2x00dev->csr_cache = NULL;
-}
-
-static int rt2x00usb_alloc_reg(struct rt2x00_dev *rt2x00dev)
-{
- rt2x00dev->csr_cache = kzalloc(CSR_CACHE_SIZE, GFP_KERNEL);
- if (!rt2x00dev->csr_cache)
- goto exit;
-
- rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
- if (!rt2x00dev->eeprom)
- goto exit;
-
- rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
- if (!rt2x00dev->rf)
- goto exit;
-
- return 0;
-
-exit:
- ERROR_PROBE("Failed to allocate registers.\n");
-
- rt2x00usb_free_reg(rt2x00dev);
-
- return -ENOMEM;
-}
-
-int rt2x00usb_probe(struct usb_interface *usb_intf,
- const struct usb_device_id *id)
-{
- struct usb_device *usb_dev = interface_to_usbdev(usb_intf);
- struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_info;
- struct ieee80211_hw *hw;
- struct rt2x00_dev *rt2x00dev;
- int retval;
-
- usb_dev = usb_get_dev(usb_dev);
-
- hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
- if (!hw) {
- ERROR_PROBE("Failed to allocate hardware.\n");
- retval = -ENOMEM;
- goto exit_put_device;
- }
-
- usb_set_intfdata(usb_intf, hw);
-
- rt2x00dev = hw->priv;
- rt2x00dev->dev = usb_intf;
- rt2x00dev->ops = ops;
- rt2x00dev->hw = hw;
-
- rt2x00dev->usb_maxpacket =
- usb_maxpacket(usb_dev, usb_sndbulkpipe(usb_dev, 1), 1);
- if (!rt2x00dev->usb_maxpacket)
- rt2x00dev->usb_maxpacket = 1;
-
- retval = rt2x00usb_alloc_reg(rt2x00dev);
- if (retval)
- goto exit_free_device;
-
- retval = rt2x00lib_probe_dev(rt2x00dev);
- if (retval)
- goto exit_free_reg;
-
- return 0;
-
-exit_free_reg:
- rt2x00usb_free_reg(rt2x00dev);
-
-exit_free_device:
- ieee80211_free_hw(hw);
-
-exit_put_device:
- usb_put_dev(usb_dev);
-
- usb_set_intfdata(usb_intf, NULL);
-
- return retval;
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_probe);
-
-void rt2x00usb_disconnect(struct usb_interface *usb_intf)
-{
- struct ieee80211_hw *hw = usb_get_intfdata(usb_intf);
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- /*
- * Free all allocated data.
- */
- rt2x00lib_remove_dev(rt2x00dev);
- rt2x00usb_free_reg(rt2x00dev);
- ieee80211_free_hw(hw);
-
- /*
- * Free the USB device data.
- */
- usb_set_intfdata(usb_intf, NULL);
- usb_put_dev(interface_to_usbdev(usb_intf));
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_disconnect);
-
-#ifdef CONFIG_PM
-int rt2x00usb_suspend(struct usb_interface *usb_intf, pm_message_t state)
-{
- struct ieee80211_hw *hw = usb_get_intfdata(usb_intf);
- struct rt2x00_dev *rt2x00dev = hw->priv;
- int retval;
-
- retval = rt2x00lib_suspend(rt2x00dev, state);
- if (retval)
- return retval;
-
- rt2x00usb_free_reg(rt2x00dev);
-
- /*
- * Decrease usbdev refcount.
- */
- usb_put_dev(interface_to_usbdev(usb_intf));
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_suspend);
-
-int rt2x00usb_resume(struct usb_interface *usb_intf)
-{
- struct ieee80211_hw *hw = usb_get_intfdata(usb_intf);
- struct rt2x00_dev *rt2x00dev = hw->priv;
- int retval;
-
- usb_get_dev(interface_to_usbdev(usb_intf));
-
- retval = rt2x00usb_alloc_reg(rt2x00dev);
- if (retval)
- return retval;
-
- retval = rt2x00lib_resume(rt2x00dev);
- if (retval)
- goto exit_free_reg;
-
- return 0;
-
-exit_free_reg:
- rt2x00usb_free_reg(rt2x00dev);
-
- return retval;
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_resume);
-#endif /* CONFIG_PM */
-
-/*
- * rt2x00pci module information.
- */
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("rt2x00 library");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt2x00usb
- Abstract: Data structures for the rt2x00usb module.
- */
-
-#ifndef RT2X00USB_H
-#define RT2X00USB_H
-
-/*
- * This variable should be used with the
- * usb_driver structure initialization.
- */
-#define USB_DEVICE_DATA(__ops) .driver_info = (kernel_ulong_t)(__ops)
-
-/*
- * Register defines.
- * Some registers require multiple attempts before success,
- * in those cases REGISTER_BUSY_COUNT attempts should be
- * taken with a REGISTER_BUSY_DELAY interval.
- * For USB vendor requests we need to pass a timeout
- * time in ms, for this we use the REGISTER_TIMEOUT,
- * however when loading firmware a higher value is
- * required. In that case we use the REGISTER_TIMEOUT_FIRMWARE.
- */
-#define REGISTER_BUSY_COUNT 5
-#define REGISTER_BUSY_DELAY 100
-#define REGISTER_TIMEOUT 500
-#define REGISTER_TIMEOUT_FIRMWARE 1000
-
-/*
- * Cache size
- */
-#define CSR_CACHE_SIZE 8
-#define CSR_CACHE_SIZE_FIRMWARE 64
-
-/*
- * USB request types.
- */
-#define USB_VENDOR_REQUEST ( USB_TYPE_VENDOR | USB_RECIP_DEVICE )
-#define USB_VENDOR_REQUEST_IN ( USB_DIR_IN | USB_VENDOR_REQUEST )
-#define USB_VENDOR_REQUEST_OUT ( USB_DIR_OUT | USB_VENDOR_REQUEST )
-
-/*
- * USB vendor commands.
- */
-#define USB_DEVICE_MODE 0x01
-#define USB_SINGLE_WRITE 0x02
-#define USB_SINGLE_READ 0x03
-#define USB_MULTI_WRITE 0x06
-#define USB_MULTI_READ 0x07
-#define USB_EEPROM_WRITE 0x08
-#define USB_EEPROM_READ 0x09
-#define USB_LED_CONTROL 0x0a /* RT73USB */
-#define USB_RX_CONTROL 0x0c
-
-/*
- * Device modes offset
- */
-#define USB_MODE_RESET 0x01
-#define USB_MODE_UNPLUG 0x02
-#define USB_MODE_FUNCTION 0x03
-#define USB_MODE_TEST 0x04
-#define USB_MODE_SLEEP 0x07 /* RT73USB */
-#define USB_MODE_FIRMWARE 0x08 /* RT73USB */
-#define USB_MODE_WAKEUP 0x09 /* RT73USB */
-
-/*
- * Used to read/write from/to the device.
- * This is the main function to communicate with the device,
- * the buffer argument _must_ either be NULL or point to
- * a buffer allocated by kmalloc. Failure to do so can lead
- * to unexpected behavior depending on the architecture.
- */
-int rt2x00usb_vendor_request(const struct rt2x00_dev *rt2x00dev,
- const u8 request, const u8 requesttype,
- const u16 offset, const u16 value,
- void *buffer, const u16 buffer_length,
- const int timeout);
-
-/*
- * Used to read/write from/to the device.
- * This function will use a previously with kmalloc allocated cache
- * to communicate with the device. The contents of the buffer pointer
- * will be copied to this cache when writing, or read from the cache
- * when reading.
- * Buffers send to rt2x00usb_vendor_request _must_ be allocated with
- * kmalloc. Hence the reason for using a previously allocated cache
- * which has been allocated properly.
- */
-int rt2x00usb_vendor_request_buff(const struct rt2x00_dev *rt2x00dev,
- const u8 request, const u8 requesttype,
- const u16 offset, void *buffer,
- const u16 buffer_length, const int timeout);
-
-/*
- * Simple wrapper around rt2x00usb_vendor_request to write a single
- * command to the device. Since we don't use the buffer argument we
- * don't have to worry about kmalloc here.
- */
-static inline int rt2x00usb_vendor_request_sw(const struct rt2x00_dev
- *rt2x00dev,
- const u8 request,
- const u16 offset,
- const u16 value,
- const int timeout)
-{
- return rt2x00usb_vendor_request(rt2x00dev, request,
- USB_VENDOR_REQUEST_OUT, offset,
- value, NULL, 0, timeout);
-}
-
-/*
- * Simple wrapper around rt2x00usb_vendor_request to read the eeprom
- * from the device. Note that the eeprom argument _must_ be allocated using
- * kmalloc for correct handling inside the kernel USB layer.
- */
-static inline int rt2x00usb_eeprom_read(const struct rt2x00_dev *rt2x00dev,
- __le16 *eeprom, const u16 lenght)
-{
- int timeout = REGISTER_TIMEOUT * (lenght / sizeof(u16));
-
- return rt2x00usb_vendor_request(rt2x00dev, USB_EEPROM_READ,
- USB_VENDOR_REQUEST_IN, 0x0000,
- 0x0000, eeprom, lenght, timeout);
-}
-
-/*
- * Radio handlers
- */
-void rt2x00usb_enable_radio(struct rt2x00_dev *rt2x00dev);
-void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev);
-
-/*
- * TX data handlers.
- */
-int rt2x00usb_write_tx_data(struct rt2x00_dev *rt2x00dev,
- struct data_ring *ring, struct sk_buff *skb,
- struct ieee80211_tx_control *control);
-
-/*
- * Device initialization handlers.
- */
-int rt2x00usb_initialize(struct rt2x00_dev *rt2x00dev);
-void rt2x00usb_uninitialize(struct rt2x00_dev *rt2x00dev);
-
-/*
- * USB driver handlers.
- */
-int rt2x00usb_probe(struct usb_interface *usb_intf,
- const struct usb_device_id *id);
-void rt2x00usb_disconnect(struct usb_interface *usb_intf);
-#ifdef CONFIG_PM
-int rt2x00usb_suspend(struct usb_interface *usb_intf, pm_message_t state);
-int rt2x00usb_resume(struct usb_interface *usb_intf);
-#else
-#define rt2x00usb_suspend NULL
-#define rt2x00usb_resume NULL
-#endif /* CONFIG_PM */
-
-#endif /* RT2X00USB_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt61pci
- Abstract: rt61pci device specific routines.
- Supported chipsets: RT2561, RT2561s, RT2661.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt61pci"
-
-#include <linux/delay.h>
-#include <linux/etherdevice.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/eeprom_93cx6.h>
-
-#include "rt2x00.h"
-#include "rt2x00pci.h"
-#include "rt61pci.h"
-
-/*
- * Register access.
- * BBP and RF register require indirect register access,
- * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
- * These indirect registers work with busy bits,
- * and we will try maximal REGISTER_BUSY_COUNT times to access
- * the register while taking a REGISTER_BUSY_DELAY us delay
- * between each attampt. When the busy bit is still set at that time,
- * the access attempt is considered to have failed,
- * and we will print an error.
- */
-static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- unsigned int i;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®);
- if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
- break;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- return reg;
-}
-
-static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u8 value)
-{
- u32 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt61pci_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
- ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
- return;
- }
-
- /*
- * Write the data into the BBP.
- */
- reg = 0;
- rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
- rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
- rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
- rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
-
- rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
-}
-
-static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u8 *value)
-{
- u32 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt61pci_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
- ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
- return;
- }
-
- /*
- * Write the request into the BBP.
- */
- reg = 0;
- rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
- rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
- rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
-
- rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt61pci_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
- ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
- *value = 0xff;
- return;
- }
-
- *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
-}
-
-static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u32 value)
-{
- u32 reg;
- unsigned int i;
-
- if (!word)
- return;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
- if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
- goto rf_write;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
- return;
-
-rf_write:
- reg = 0;
- rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
- rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
- rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
- rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
-
- rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
- rt2x00_rf_write(rt2x00dev, word, value);
-}
-
-static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
- const u8 command, const u8 token,
- const u8 arg0, const u8 arg1)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
-
- if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
- ERROR(rt2x00dev, "mcu request error. "
- "Request 0x%02x failed for token 0x%02x.\n",
- command, token);
- return;
- }
-
- rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
- rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
- rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
- rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
- rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
- rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
- rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
- rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
-}
-
-static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
-{
- struct rt2x00_dev *rt2x00dev = eeprom->data;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
-
- eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
- eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
- eeprom->reg_data_clock =
- !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
- eeprom->reg_chip_select =
- !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
-}
-
-static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
-{
- struct rt2x00_dev *rt2x00dev = eeprom->data;
- u32 reg = 0;
-
- rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
- rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
- rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
- !!eeprom->reg_data_clock);
- rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
- !!eeprom->reg_chip_select);
-
- rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
-}
-
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
-
-static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 *data)
-{
- rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 data)
-{
- rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static const struct rt2x00debug rt61pci_rt2x00debug = {
- .owner = THIS_MODULE,
- .csr = {
- .read = rt61pci_read_csr,
- .write = rt61pci_write_csr,
- .word_size = sizeof(u32),
- .word_count = CSR_REG_SIZE / sizeof(u32),
- },
- .eeprom = {
- .read = rt2x00_eeprom_read,
- .write = rt2x00_eeprom_write,
- .word_size = sizeof(u16),
- .word_count = EEPROM_SIZE / sizeof(u16),
- },
- .bbp = {
- .read = rt61pci_bbp_read,
- .write = rt61pci_bbp_write,
- .word_size = sizeof(u8),
- .word_count = BBP_SIZE / sizeof(u8),
- },
- .rf = {
- .read = rt2x00_rf_read,
- .write = rt61pci_rf_write,
- .word_size = sizeof(u32),
- .word_count = RF_SIZE / sizeof(u32),
- },
-};
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
-#ifdef CONFIG_RT61PCI_RFKILL
-static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
- return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
-}
-#else
-#define rt61pci_rfkill_poll NULL
-#endif /* CONFIG_RT61PCI_RFKILL */
-
-/*
- * Configuration handlers.
- */
-static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
-{
- u32 tmp;
-
- tmp = le32_to_cpu(mac[1]);
- rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
- mac[1] = cpu_to_le32(tmp);
-
- rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
- (2 * sizeof(__le32)));
-}
-
-static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
-{
- u32 tmp;
-
- tmp = le32_to_cpu(bssid[1]);
- rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
- bssid[1] = cpu_to_le32(tmp);
-
- rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
- (2 * sizeof(__le32)));
-}
-
-static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
- const int tsf_sync)
-{
- u32 reg;
-
- /*
- * Clear current synchronisation setup.
- * For the Beacon base registers we only need to clear
- * the first byte since that byte contains the VALID and OWNER
- * bits which (when set to 0) will invalidate the entire beacon.
- */
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
- rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
- rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
- rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
- rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
-
- /*
- * Enable synchronisation.
- */
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
- rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
- rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
- rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
- rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, tsf_sync);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
-}
-
-static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
- const int short_preamble,
- const int ack_timeout,
- const int ack_consume_time)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
- rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
- !!short_preamble);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
-}
-
-static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
- const int basic_rate_mask)
-{
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
-}
-
-static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
- struct rf_channel *rf, const int txpower)
-{
- u8 r3;
- u8 r94;
- u8 smart;
-
- rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
- rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
-
- smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
- rt2x00_rf(&rt2x00dev->chip, RF2527));
-
- rt61pci_bbp_read(rt2x00dev, 3, &r3);
- rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
- rt61pci_bbp_write(rt2x00dev, 3, r3);
-
- r94 = 6;
- if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
- r94 += txpower - MAX_TXPOWER;
- else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
- r94 += txpower;
- rt61pci_bbp_write(rt2x00dev, 94, r94);
-
- rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
- rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
- rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
- rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
-
- udelay(200);
-
- rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
- rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
- rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
- rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
-
- udelay(200);
-
- rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
- rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
- rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
- rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
-
- msleep(1);
-}
-
-static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
- const int txpower)
-{
- struct rf_channel rf;
-
- rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
- rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
- rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
- rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
-
- rt61pci_config_channel(rt2x00dev, &rf, txpower);
-}
-
-static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx,
- const int antenna_rx)
-{
- u8 r3;
- u8 r4;
- u8 r77;
-
- rt61pci_bbp_read(rt2x00dev, 3, &r3);
- rt61pci_bbp_read(rt2x00dev, 4, &r4);
- rt61pci_bbp_read(rt2x00dev, 77, &r77);
-
- rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
- !rt2x00_rf(&rt2x00dev->chip, RF5225));
-
- switch (antenna_rx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
- !!(rt2x00dev->curr_hwmode != HWMODE_A));
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
-
- if (rt2x00dev->curr_hwmode == HWMODE_A)
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
- else
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
-
- if (rt2x00dev->curr_hwmode == HWMODE_A)
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
- else
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
- break;
- }
-
- rt61pci_bbp_write(rt2x00dev, 77, r77);
- rt61pci_bbp_write(rt2x00dev, 3, r3);
- rt61pci_bbp_write(rt2x00dev, 4, r4);
-}
-
-static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx,
- const int antenna_rx)
-{
- u8 r3;
- u8 r4;
- u8 r77;
-
- rt61pci_bbp_read(rt2x00dev, 3, &r3);
- rt61pci_bbp_read(rt2x00dev, 4, &r4);
- rt61pci_bbp_read(rt2x00dev, 77, &r77);
-
- rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
- !rt2x00_rf(&rt2x00dev->chip, RF2527));
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
- !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
-
- switch (antenna_rx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
- break;
- }
-
- rt61pci_bbp_write(rt2x00dev, 77, r77);
- rt61pci_bbp_write(rt2x00dev, 3, r3);
- rt61pci_bbp_write(rt2x00dev, 4, r4);
-}
-
-static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
- const int p1, const int p2)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
-
- if (p1 != 0xff) {
- rt2x00_set_field32(®, MAC_CSR13_BIT4, !!p1);
- rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
- }
- if (p2 != 0xff) {
- rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
- rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
- }
-}
-
-static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx,
- const int antenna_rx)
-{
- u16 eeprom;
- u8 r3;
- u8 r4;
- u8 r77;
-
- rt61pci_bbp_read(rt2x00dev, 3, &r3);
- rt61pci_bbp_read(rt2x00dev, 4, &r4);
- rt61pci_bbp_read(rt2x00dev, 77, &r77);
- rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
-
- rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
-
- if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
- rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 1);
- rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
- } else if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) {
- if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) >= 2) {
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
- rt61pci_bbp_write(rt2x00dev, 77, r77);
- }
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
- } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
- rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
-
- switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
- case 0:
- rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
- break;
- case 1:
- rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
- break;
- case 2:
- rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
- break;
- case 3:
- rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
- break;
- }
- } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
- !rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
-
- switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
- case 0:
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
- rt61pci_bbp_write(rt2x00dev, 77, r77);
- rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
- break;
- case 1:
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
- rt61pci_bbp_write(rt2x00dev, 77, r77);
- rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
- break;
- case 2:
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
- rt61pci_bbp_write(rt2x00dev, 77, r77);
- rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
- break;
- case 3:
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
- rt61pci_bbp_write(rt2x00dev, 77, r77);
- rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
- break;
- }
- }
-
- rt61pci_bbp_write(rt2x00dev, 3, r3);
- rt61pci_bbp_write(rt2x00dev, 4, r4);
-}
-
-struct antenna_sel {
- u8 word;
- /*
- * value[0] -> non-LNA
- * value[1] -> LNA
- */
- u8 value[2];
-};
-
-static const struct antenna_sel antenna_sel_a[] = {
- { 96, { 0x58, 0x78 } },
- { 104, { 0x38, 0x48 } },
- { 75, { 0xfe, 0x80 } },
- { 86, { 0xfe, 0x80 } },
- { 88, { 0xfe, 0x80 } },
- { 35, { 0x60, 0x60 } },
- { 97, { 0x58, 0x58 } },
- { 98, { 0x58, 0x58 } },
-};
-
-static const struct antenna_sel antenna_sel_bg[] = {
- { 96, { 0x48, 0x68 } },
- { 104, { 0x2c, 0x3c } },
- { 75, { 0xfe, 0x80 } },
- { 86, { 0xfe, 0x80 } },
- { 88, { 0xfe, 0x80 } },
- { 35, { 0x50, 0x50 } },
- { 97, { 0x48, 0x48 } },
- { 98, { 0x48, 0x48 } },
-};
-
-static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx, const int antenna_rx)
-{
- const struct antenna_sel *sel;
- unsigned int lna;
- unsigned int i;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
-
- if (rt2x00dev->curr_hwmode == HWMODE_A) {
- sel = antenna_sel_a;
- lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
-
- rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 0);
- rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 1);
- } else {
- sel = antenna_sel_bg;
- lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
-
- rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 1);
- rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 0);
- }
-
- for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
- rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
-
- rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
-
- if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
- rt2x00_rf(&rt2x00dev->chip, RF5325))
- rt61pci_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
- else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
- rt61pci_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
- else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
- if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
- rt61pci_config_antenna_2x(rt2x00dev, antenna_tx,
- antenna_rx);
- else
- rt61pci_config_antenna_2529(rt2x00dev, antenna_tx,
- antenna_rx);
- }
-}
-
-static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
- struct rt2x00lib_conf *libconf)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
- rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
- rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
- rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
- rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
- rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
- rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
- libconf->conf->beacon_int * 16);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
-}
-
-static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
- const unsigned int flags,
- struct rt2x00lib_conf *libconf)
-{
- if (flags & CONFIG_UPDATE_PHYMODE)
- rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
- if (flags & CONFIG_UPDATE_CHANNEL)
- rt61pci_config_channel(rt2x00dev, &libconf->rf,
- libconf->conf->power_level);
- if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
- rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
- if (flags & CONFIG_UPDATE_ANTENNA)
- rt61pci_config_antenna(rt2x00dev, libconf->conf->antenna_sel_tx,
- libconf->conf->antenna_sel_rx);
- if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
- rt61pci_config_duration(rt2x00dev, libconf);
-}
-
-/*
- * LED functions.
- */
-static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- u16 led_reg;
- u8 arg0;
- u8 arg1;
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR14, ®);
- rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
- rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
-
- led_reg = rt2x00dev->led_reg;
- rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
- if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
- rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
- else
- rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
-
- arg0 = led_reg & 0xff;
- arg1 = (led_reg >> 8) & 0xff;
-
- rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
-}
-
-static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
-{
- u16 led_reg;
- u8 arg0;
- u8 arg1;
-
- led_reg = rt2x00dev->led_reg;
- rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
- rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
- rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
-
- arg0 = led_reg & 0xff;
- arg1 = (led_reg >> 8) & 0xff;
-
- rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
-}
-
-static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
-{
- u8 led;
-
- if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
- return;
-
- /*
- * Led handling requires a positive value for the rssi,
- * to do that correctly we need to add the correction.
- */
- rssi += rt2x00dev->rssi_offset;
-
- if (rssi <= 30)
- led = 0;
- else if (rssi <= 39)
- led = 1;
- else if (rssi <= 49)
- led = 2;
- else if (rssi <= 53)
- led = 3;
- else if (rssi <= 63)
- led = 4;
- else
- led = 5;
-
- rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
-}
-
-/*
- * Link tuning
- */
-static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Update FCS error count from register.
- */
- rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
- rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
-
- /*
- * Update False CCA count from register.
- */
- rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
- rt2x00dev->link.false_cca =
- rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
-}
-
-static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
-{
- rt61pci_bbp_write(rt2x00dev, 17, 0x20);
- rt2x00dev->link.vgc_level = 0x20;
-}
-
-static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
- int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
- u8 r17;
- u8 up_bound;
- u8 low_bound;
-
- /*
- * Update Led strength
- */
- rt61pci_activity_led(rt2x00dev, rssi);
-
- rt61pci_bbp_read(rt2x00dev, 17, &r17);
-
- /*
- * Determine r17 bounds.
- */
- if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
- low_bound = 0x28;
- up_bound = 0x48;
- if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
- low_bound += 0x10;
- up_bound += 0x10;
- }
- } else {
- low_bound = 0x20;
- up_bound = 0x40;
- if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
- low_bound += 0x10;
- up_bound += 0x10;
- }
- }
-
- /*
- * Special big-R17 for very short distance
- */
- if (rssi >= -35) {
- if (r17 != 0x60)
- rt61pci_bbp_write(rt2x00dev, 17, 0x60);
- return;
- }
-
- /*
- * Special big-R17 for short distance
- */
- if (rssi >= -58) {
- if (r17 != up_bound)
- rt61pci_bbp_write(rt2x00dev, 17, up_bound);
- return;
- }
-
- /*
- * Special big-R17 for middle-short distance
- */
- if (rssi >= -66) {
- low_bound += 0x10;
- if (r17 != low_bound)
- rt61pci_bbp_write(rt2x00dev, 17, low_bound);
- return;
- }
-
- /*
- * Special mid-R17 for middle distance
- */
- if (rssi >= -74) {
- low_bound += 0x08;
- if (r17 != low_bound)
- rt61pci_bbp_write(rt2x00dev, 17, low_bound);
- return;
- }
-
- /*
- * Special case: Change up_bound based on the rssi.
- * Lower up_bound when rssi is weaker then -74 dBm.
- */
- up_bound -= 2 * (-74 - rssi);
- if (low_bound > up_bound)
- up_bound = low_bound;
-
- if (r17 > up_bound) {
- rt61pci_bbp_write(rt2x00dev, 17, up_bound);
- return;
- }
-
- /*
- * r17 does not yet exceed upper limit, continue and base
- * the r17 tuning on the false CCA count.
- */
- if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
- if (++r17 > up_bound)
- r17 = up_bound;
- rt61pci_bbp_write(rt2x00dev, 17, r17);
- } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
- if (--r17 < low_bound)
- r17 = low_bound;
- rt61pci_bbp_write(rt2x00dev, 17, r17);
- }
-}
-
-/*
- * Firmware name function.
- */
-static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
-{
- char *fw_name;
-
- switch (rt2x00dev->chip.rt) {
- case RT2561:
- fw_name = FIRMWARE_RT2561;
- break;
- case RT2561s:
- fw_name = FIRMWARE_RT2561s;
- break;
- case RT2661:
- fw_name = FIRMWARE_RT2661;
- break;
- default:
- fw_name = NULL;
- break;
- }
-
- return fw_name;
-}
-
-/*
- * Initialization functions.
- */
-static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
- const size_t len)
-{
- int i;
- u32 reg;
-
- /*
- * Wait for stable hardware.
- */
- for (i = 0; i < 100; i++) {
- rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
- if (reg)
- break;
- msleep(1);
- }
-
- if (!reg) {
- ERROR(rt2x00dev, "Unstable hardware.\n");
- return -EBUSY;
- }
-
- /*
- * Prepare MCU and mailbox for firmware loading.
- */
- reg = 0;
- rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
- rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
- rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
- rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
- rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
-
- /*
- * Write firmware to device.
- */
- reg = 0;
- rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
- rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
- rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
-
- rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
- data, len);
-
- rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
- rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
-
- rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
- rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
-
- for (i = 0; i < 100; i++) {
- rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
- if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
- break;
- msleep(1);
- }
-
- if (i == 100) {
- ERROR(rt2x00dev, "MCU Control register not ready.\n");
- return -EBUSY;
- }
-
- /*
- * Reset MAC and BBP registers.
- */
- reg = 0;
- rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
- rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
- rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
-
- return 0;
-}
-
-static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring = rt2x00dev->rx;
- struct data_desc *rxd;
- unsigned int i;
- u32 word;
-
- memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
- for (i = 0; i < ring->stats.limit; i++) {
- rxd = ring->entry[i].priv;
-
- rt2x00_desc_read(rxd, 5, &word);
- rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
- ring->entry[i].data_dma);
- rt2x00_desc_write(rxd, 5, word);
-
- rt2x00_desc_read(rxd, 0, &word);
- rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
- rt2x00_desc_write(rxd, 0, word);
- }
-
- rt2x00_ring_index_clear(rt2x00dev->rx);
-}
-
-static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
-{
- struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
- struct data_desc *txd;
- unsigned int i;
- u32 word;
-
- memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
- for (i = 0; i < ring->stats.limit; i++) {
- txd = ring->entry[i].priv;
-
- rt2x00_desc_read(txd, 1, &word);
- rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
- rt2x00_desc_write(txd, 1, word);
-
- rt2x00_desc_read(txd, 5, &word);
- rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
- rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
- rt2x00_desc_write(txd, 5, word);
-
- rt2x00_desc_read(txd, 6, &word);
- rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
- ring->entry[i].data_dma);
- rt2x00_desc_write(txd, 6, word);
-
- rt2x00_desc_read(txd, 0, &word);
- rt2x00_set_field32(&word, TXD_W0_VALID, 0);
- rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
- rt2x00_desc_write(txd, 0, word);
- }
-
- rt2x00_ring_index_clear(ring);
-}
-
-static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Initialize rings.
- */
- rt61pci_init_rxring(rt2x00dev);
- rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
- rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
- rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
- rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
- rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
-
- /*
- * Initialize registers.
- */
- rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
- rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
- rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
- rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
- rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
- rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
-
- rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
- rt2x00_set_field32(®, TX_RING_CSR1_MGMT_RING_SIZE,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
- rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
- 4);
- rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
- rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
- rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
- rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
- rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
- rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
- rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
- rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
- rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, ®);
- rt2x00_set_field32(®, MGMT_BASE_CSR_RING_REGISTER,
- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
- rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
- rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE,
- rt2x00dev->rx->stats.limit);
- rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
- rt2x00dev->rx->desc_size / 4);
- rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
- rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
- rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
- rt2x00dev->rx->data_dma);
- rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
- rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
- rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
- rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
- rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
- rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_MGMT, 0);
- rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
- rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
- rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
- rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
- rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
- rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
- rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
- rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
- rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
-
- return 0;
-}
-
-static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
- rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
- rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
-
- /*
- * CCK TXD BBP registers
- */
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
-
- /*
- * OFDM TXD BBP registers
- */
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
- rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
- rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
- rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
- rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
- rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
- rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
- rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
- rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
-
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
-
- rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
- rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
-
- rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
-
- if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
- return -EBUSY;
-
- rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
-
- /*
- * Invalidate all Shared Keys (SEC_CSR0),
- * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
- */
- rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
- rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
- rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
-
- rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
- rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
- rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
- rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
-
- rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
-
- rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
-
- rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
-
- rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
- rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
- rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
- rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
-
- rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
- rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
- rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
- rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
-
- /*
- * We must clear the error counters.
- * These registers are cleared on read,
- * so we may pass a useless variable to store the value.
- */
- rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
- rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
- rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
-
- /*
- * Reset MAC and BBP registers.
- */
- rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
- rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
- rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
-
- return 0;
-}
-
-static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
-{
- unsigned int i;
- u16 eeprom;
- u8 reg_id;
- u8 value;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt61pci_bbp_read(rt2x00dev, 0, &value);
- if ((value != 0xff) && (value != 0x00))
- goto continue_csr_init;
- NOTICE(rt2x00dev, "Waiting for BBP register.\n");
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
- return -EACCES;
-
-continue_csr_init:
- rt61pci_bbp_write(rt2x00dev, 3, 0x00);
- rt61pci_bbp_write(rt2x00dev, 15, 0x30);
- rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
- rt61pci_bbp_write(rt2x00dev, 22, 0x38);
- rt61pci_bbp_write(rt2x00dev, 23, 0x06);
- rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
- rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
- rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
- rt61pci_bbp_write(rt2x00dev, 34, 0x12);
- rt61pci_bbp_write(rt2x00dev, 37, 0x07);
- rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
- rt61pci_bbp_write(rt2x00dev, 41, 0x60);
- rt61pci_bbp_write(rt2x00dev, 53, 0x10);
- rt61pci_bbp_write(rt2x00dev, 54, 0x18);
- rt61pci_bbp_write(rt2x00dev, 60, 0x10);
- rt61pci_bbp_write(rt2x00dev, 61, 0x04);
- rt61pci_bbp_write(rt2x00dev, 62, 0x04);
- rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
- rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
- rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
- rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
- rt61pci_bbp_write(rt2x00dev, 99, 0x00);
- rt61pci_bbp_write(rt2x00dev, 102, 0x16);
- rt61pci_bbp_write(rt2x00dev, 107, 0x04);
-
- DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
- for (i = 0; i < EEPROM_BBP_SIZE; i++) {
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
-
- if (eeprom != 0xffff && eeprom != 0x0000) {
- reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
- value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
- DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
- reg_id, value);
- rt61pci_bbp_write(rt2x00dev, reg_id, value);
- }
- }
- DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
-
- return 0;
-}
-
-/*
- * Device state switch handlers.
- */
-static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
- state == STATE_RADIO_RX_OFF);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
-}
-
-static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- int mask = (state == STATE_RADIO_IRQ_OFF);
- u32 reg;
-
- /*
- * When interrupts are being enabled, the interrupt registers
- * should clear the register to assure a clean state.
- */
- if (state == STATE_RADIO_IRQ_ON) {
- rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
- rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
- rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
- }
-
- /*
- * Only toggle the interrupts bits we are going to use.
- * Non-checked interrupt bits are disabled by default.
- */
- rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
- rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
- rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
- rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
- rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
- rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
-
- rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
- rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
- rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
- rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
- rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
- rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
- rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
- rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
- rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
- rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
-}
-
-static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Initialize all registers.
- */
- if (rt61pci_init_rings(rt2x00dev) ||
- rt61pci_init_registers(rt2x00dev) ||
- rt61pci_init_bbp(rt2x00dev)) {
- ERROR(rt2x00dev, "Register initialization failed.\n");
- return -EIO;
- }
-
- /*
- * Enable interrupts.
- */
- rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
-
- /*
- * Enable RX.
- */
- rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
- rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
- rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
-
- /*
- * Enable LED
- */
- rt61pci_enable_led(rt2x00dev);
-
- return 0;
-}
-
-static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Disable LED
- */
- rt61pci_disable_led(rt2x00dev);
-
- rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
-
- /*
- * Disable synchronisation.
- */
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
-
- /*
- * Cancel RX and TX.
- */
- rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
- rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
-
- /*
- * Disable interrupts.
- */
- rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
-}
-
-static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
-{
- u32 reg;
- unsigned int i;
- char put_to_sleep;
- char current_state;
-
- put_to_sleep = (state != STATE_AWAKE);
-
- rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
- rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
- rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
-
- /*
- * Device is not guaranteed to be in the requested state yet.
- * We must wait until the register indicates that the
- * device has entered the correct state.
- */
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
- current_state =
- rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
- if (current_state == !put_to_sleep)
- return 0;
- msleep(10);
- }
-
- NOTICE(rt2x00dev, "Device failed to enter state %d, "
- "current device state %d.\n", !put_to_sleep, current_state);
-
- return -EBUSY;
-}
-
-static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- int retval = 0;
-
- switch (state) {
- case STATE_RADIO_ON:
- retval = rt61pci_enable_radio(rt2x00dev);
- break;
- case STATE_RADIO_OFF:
- rt61pci_disable_radio(rt2x00dev);
- break;
- case STATE_RADIO_RX_ON:
- case STATE_RADIO_RX_OFF:
- rt61pci_toggle_rx(rt2x00dev, state);
- break;
- case STATE_DEEP_SLEEP:
- case STATE_SLEEP:
- case STATE_STANDBY:
- case STATE_AWAKE:
- retval = rt61pci_set_state(rt2x00dev, state);
- break;
- default:
- retval = -ENOTSUPP;
- break;
- }
-
- return retval;
-}
-
-/*
- * TX descriptor initialization
- */
-static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
- struct data_desc *txd,
- struct txdata_entry_desc *desc,
- struct ieee80211_hdr *ieee80211hdr,
- unsigned int length,
- struct ieee80211_tx_control *control)
-{
- u32 word;
-
- /*
- * Start writing the descriptor words.
- */
- rt2x00_desc_read(txd, 1, &word);
- rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
- rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
- rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
- rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
- rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
- rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
- rt2x00_desc_write(txd, 1, word);
-
- rt2x00_desc_read(txd, 2, &word);
- rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
- rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
- rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
- rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
- rt2x00_desc_write(txd, 2, word);
-
- rt2x00_desc_read(txd, 5, &word);
- rt2x00_set_field32(&word, TXD_W5_TX_POWER,
- TXPOWER_TO_DEV(control->power_level));
- rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
- rt2x00_desc_write(txd, 5, word);
-
- rt2x00_desc_read(txd, 11, &word);
- rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
- rt2x00_desc_write(txd, 11, word);
-
- rt2x00_desc_read(txd, 0, &word);
- rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
- rt2x00_set_field32(&word, TXD_W0_VALID, 1);
- rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
- test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_ACK,
- !(control->flags & IEEE80211_TXCTL_NO_ACK));
- rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
- test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_OFDM,
- test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
- rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
- !!(control->flags &
- IEEE80211_TXCTL_LONG_RETRY_LIMIT));
- rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
- rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
- rt2x00_set_field32(&word, TXD_W0_BURST,
- test_bit(ENTRY_TXD_BURST, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
- rt2x00_desc_write(txd, 0, word);
-}
-
-/*
- * TX data initialization
- */
-static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
- unsigned int queue)
-{
- u32 reg;
-
- if (queue == IEEE80211_TX_QUEUE_BEACON) {
- /*
- * For Wi-Fi faily generated beacons between participating
- * stations. Set TBTT phase adaptive adjustment step to 8us.
- */
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
- if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
- rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
- }
- return;
- }
-
- rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
- if (queue == IEEE80211_TX_QUEUE_DATA0)
- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1);
- else if (queue == IEEE80211_TX_QUEUE_DATA1)
- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1);
- else if (queue == IEEE80211_TX_QUEUE_DATA2)
- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1);
- else if (queue == IEEE80211_TX_QUEUE_DATA3)
- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1);
- else if (queue == IEEE80211_TX_QUEUE_DATA4)
- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_MGMT, 1);
- rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
-}
-
-/*
- * RX control handlers
- */
-static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
-{
- u16 eeprom;
- u8 offset;
- u8 lna;
-
- lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
- switch (lna) {
- case 3:
- offset = 90;
- break;
- case 2:
- offset = 74;
- break;
- case 1:
- offset = 64;
- break;
- default:
- return 0;
- }
-
- if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
- if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
- offset += 14;
-
- if (lna == 3 || lna == 2)
- offset += 10;
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
- offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
- } else {
- if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
- offset += 14;
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
- offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
- }
-
- return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
-}
-
-static void rt61pci_fill_rxdone(struct data_entry *entry,
- struct rxdata_entry_desc *desc)
-{
- struct data_desc *rxd = entry->priv;
- u32 word0;
- u32 word1;
-
- rt2x00_desc_read(rxd, 0, &word0);
- rt2x00_desc_read(rxd, 1, &word1);
-
- desc->flags = 0;
- if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
- desc->flags |= RX_FLAG_FAILED_FCS_CRC;
-
- /*
- * Obtain the status about this packet.
- */
- desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
- desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
- desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
- desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
-
- return;
-}
-
-/*
- * Interrupt functions.
- */
-static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
-{
- struct data_ring *ring;
- struct data_entry *entry;
- struct data_entry *entry_done;
- struct data_desc *txd;
- u32 word;
- u32 reg;
- u32 old_reg;
- int type;
- int index;
- int tx_status;
- int retry;
-
- /*
- * During each loop we will compare the freshly read
- * STA_CSR4 register value with the value read from
- * the previous loop. If the 2 values are equal then
- * we should stop processing because the chance it
- * quite big that the device has been unplugged and
- * we risk going into an endless loop.
- */
- old_reg = 0;
-
- while (1) {
- rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
- if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
- break;
-
- if (old_reg == reg)
- break;
- old_reg = reg;
-
- /*
- * Skip this entry when it contains an invalid
- * ring identication number.
- */
- type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
- ring = rt2x00lib_get_ring(rt2x00dev, type);
- if (unlikely(!ring))
- continue;
-
- /*
- * Skip this entry when it contains an invalid
- * index number.
- */
- index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
- if (unlikely(index >= ring->stats.limit))
- continue;
-
- entry = &ring->entry[index];
- txd = entry->priv;
- rt2x00_desc_read(txd, 0, &word);
-
- if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
- !rt2x00_get_field32(word, TXD_W0_VALID))
- return;
-
- entry_done = rt2x00_get_data_entry_done(ring);
- while (entry != entry_done) {
- /* Catch up. Just report any entries we missed as
- * failed. */
- WARNING(rt2x00dev,
- "TX status report missed for entry %p\n",
- entry_done);
- rt2x00lib_txdone(entry_done, TX_FAIL_OTHER, 0);
- entry_done = rt2x00_get_data_entry_done(ring);
- }
-
- /*
- * Obtain the status about this packet.
- */
- tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
- retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
-
- rt2x00lib_txdone(entry, tx_status, retry);
-
- /*
- * Make this entry available for reuse.
- */
- entry->flags = 0;
- rt2x00_set_field32(&word, TXD_W0_VALID, 0);
- rt2x00_desc_write(txd, 0, word);
- rt2x00_ring_index_done_inc(entry->ring);
-
- /*
- * If the data ring was full before the txdone handler
- * we must make sure the packet queue in the mac80211 stack
- * is reenabled when the txdone handler has finished.
- */
- if (!rt2x00_ring_full(ring))
- ieee80211_wake_queue(rt2x00dev->hw,
- entry->tx_status.control.queue);
- }
-}
-
-static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
-{
- struct rt2x00_dev *rt2x00dev = dev_instance;
- u32 reg_mcu;
- u32 reg;
-
- /*
- * Get the interrupt sources & saved to local variable.
- * Write register value back to clear pending interrupts.
- */
- rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
- rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
-
- rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
- rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
-
- if (!reg && !reg_mcu)
- return IRQ_NONE;
-
- if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
- return IRQ_HANDLED;
-
- /*
- * Handle interrupts, walk through all bits
- * and run the tasks, the bits are checked in order of
- * priority.
- */
-
- /*
- * 1 - Rx ring done interrupt.
- */
- if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
- rt2x00pci_rxdone(rt2x00dev);
-
- /*
- * 2 - Tx ring done interrupt.
- */
- if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
- rt61pci_txdone(rt2x00dev);
-
- /*
- * 3 - Handle MCU command done.
- */
- if (reg_mcu)
- rt2x00pci_register_write(rt2x00dev,
- M2H_CMD_DONE_CSR, 0xffffffff);
-
- return IRQ_HANDLED;
-}
-
-/*
- * Device probe functions.
- */
-static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- struct eeprom_93cx6 eeprom;
- u32 reg;
- u16 word;
- u8 *mac;
- s8 value;
-
- rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
-
- eeprom.data = rt2x00dev;
- eeprom.register_read = rt61pci_eepromregister_read;
- eeprom.register_write = rt61pci_eepromregister_write;
- eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
- PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
- eeprom.reg_data_in = 0;
- eeprom.reg_data_out = 0;
- eeprom.reg_data_clock = 0;
- eeprom.reg_chip_select = 0;
-
- eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
- EEPROM_SIZE / sizeof(u16));
-
- /*
- * Start validation of the data that has been read.
- */
- mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
- if (!is_valid_ether_addr(mac)) {
- DECLARE_MAC_BUF(macbuf);
-
- random_ether_addr(mac);
- EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
- EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
- rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
- rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
- rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
- rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
- rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
- EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
- LED_MODE_DEFAULT);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
- EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
- rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
- EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
- EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
- } else {
- value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
- if (value < -10 || value > 10)
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
- value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
- if (value < -10 || value > 10)
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
- EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
- } else {
- value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
- if (value < -10 || value > 10)
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
- value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
- if (value < -10 || value > 10)
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
- }
-
- return 0;
-}
-
-static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- u16 value;
- u16 eeprom;
- u16 device;
-
- /*
- * Read EEPROM word for configuration.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-
- /*
- * Identify RF chipset.
- * To determine the RT chip we have to read the
- * PCI header of the device.
- */
- pci_read_config_word(rt2x00dev_pci(rt2x00dev),
- PCI_CONFIG_HEADER_DEVICE, &device);
- value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
- rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
- rt2x00_set_chip(rt2x00dev, device, value, reg);
-
- if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
- !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
- ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
- return -ENODEV;
- }
-
- /*
- * Identify default antenna configuration.
- */
- rt2x00dev->hw->conf.antenna_sel_tx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
- rt2x00dev->hw->conf.antenna_sel_rx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
-
- /*
- * Read the Frame type.
- */
- if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
- __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
-
- /*
- * Determine number of antenna's.
- */
- if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
- __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
-
- /*
- * Detect if this device has an hardware controlled radio.
- */
-#ifdef CONFIG_RT61PCI_RFKILL
- if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
- __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
-#endif /* CONFIG_RT61PCI_RFKILL */
-
- /*
- * Read frequency offset and RF programming sequence.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
- if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
- __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
-
- rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
-
- /*
- * Read external LNA informations.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
-
- if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
- __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
- if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
- __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
-
- /*
- * Store led settings, for correct led behaviour.
- * If the eeprom value is invalid,
- * switch to default led mode.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
-
- rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
-
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
- rt2x00dev->led_mode);
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_0));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_1));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_2));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_3));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_4));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
- rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_RDY_G));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_RDY_A));
-
- return 0;
-}
-
-/*
- * RF value list for RF5225 & RF5325
- * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
- */
-static const struct rf_channel rf_vals_noseq[] = {
- { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
- { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
- { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
- { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
- { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
- { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
- { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
- { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
- { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
- { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
- { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
- { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
- { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
- { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
-
- /* 802.11 UNI / HyperLan 2 */
- { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
- { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
- { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
- { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
- { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
- { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
- { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
- { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
-
- /* 802.11 HyperLan 2 */
- { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
- { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
- { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
- { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
- { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
- { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
- { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
- { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
- { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
- { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
-
- /* 802.11 UNII */
- { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
- { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
- { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
- { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
- { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
- { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
-
- /* MMAC(Japan)J52 ch 34,38,42,46 */
- { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
- { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
- { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
- { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
-};
-
-/*
- * RF value list for RF5225 & RF5325
- * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
- */
-static const struct rf_channel rf_vals_seq[] = {
- { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
- { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
- { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
- { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
- { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
- { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
- { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
- { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
- { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
- { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
- { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
- { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
- { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
- { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
-
- /* 802.11 UNI / HyperLan 2 */
- { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
- { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
- { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
- { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
- { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
- { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
- { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
- { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
-
- /* 802.11 HyperLan 2 */
- { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
- { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
- { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
- { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
- { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
- { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
- { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
- { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
- { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
- { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
-
- /* 802.11 UNII */
- { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
- { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
- { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
- { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
- { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
- { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
-
- /* MMAC(Japan)J52 ch 34,38,42,46 */
- { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
- { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
- { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
- { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
-};
-
-static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
-{
- struct hw_mode_spec *spec = &rt2x00dev->spec;
- u8 *txpower;
- unsigned int i;
-
- /*
- * Initialize all hw fields.
- */
- rt2x00dev->hw->flags =
- IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
- IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
- rt2x00dev->hw->extra_tx_headroom = 0;
- rt2x00dev->hw->max_signal = MAX_SIGNAL;
- rt2x00dev->hw->max_rssi = MAX_RX_SSI;
- rt2x00dev->hw->queues = 5;
-
- SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
- SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
- rt2x00_eeprom_addr(rt2x00dev,
- EEPROM_MAC_ADDR_0));
-
- /*
- * Convert tx_power array in eeprom.
- */
- txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
- for (i = 0; i < 14; i++)
- txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
- /*
- * Initialize hw_mode information.
- */
- spec->num_modes = 2;
- spec->num_rates = 12;
- spec->tx_power_a = NULL;
- spec->tx_power_bg = txpower;
- spec->tx_power_default = DEFAULT_TXPOWER;
-
- if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
- spec->num_channels = 14;
- spec->channels = rf_vals_noseq;
- } else {
- spec->num_channels = 14;
- spec->channels = rf_vals_seq;
- }
-
- if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
- rt2x00_rf(&rt2x00dev->chip, RF5325)) {
- spec->num_modes = 3;
- spec->num_channels = ARRAY_SIZE(rf_vals_seq);
-
- txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
- for (i = 0; i < 14; i++)
- txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
- spec->tx_power_a = txpower;
- }
-}
-
-static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
-{
- int retval;
-
- /*
- * Allocate eeprom data.
- */
- retval = rt61pci_validate_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- retval = rt61pci_init_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- /*
- * Initialize hw specifications.
- */
- rt61pci_probe_hw_mode(rt2x00dev);
-
- /*
- * This device requires firmware
- */
- __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
-
- /*
- * Set the rssi offset.
- */
- rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
-
- return 0;
-}
-
-/*
- * IEEE80211 stack callback functions.
- */
-static void rt61pci_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed_flags,
- unsigned int *total_flags,
- int mc_count,
- struct dev_addr_list *mc_list)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct interface *intf = &rt2x00dev->interface;
- u32 reg;
-
- /*
- * Mask off any flags we are going to ignore from
- * the total_flags field.
- */
- *total_flags &=
- FIF_ALLMULTI |
- FIF_FCSFAIL |
- FIF_PLCPFAIL |
- FIF_CONTROL |
- FIF_OTHER_BSS |
- FIF_PROMISC_IN_BSS;
-
- /*
- * Apply some rules to the filters:
- * - Some filters imply different filters to be set.
- * - Some things we can't filter out at all.
- * - Some filters are set based on interface type.
- */
- if (mc_count)
- *total_flags |= FIF_ALLMULTI;
- if (*total_flags & FIF_OTHER_BSS ||
- *total_flags & FIF_PROMISC_IN_BSS)
- *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
- if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
- *total_flags |= FIF_PROMISC_IN_BSS;
-
- /*
- * Check if there is any work left for us.
- */
- if (intf->filter == *total_flags)
- return;
- intf->filter = *total_flags;
-
- /*
- * Start configuration steps.
- * Note that the version error will always be dropped
- * and broadcast frames will always be accepted since
- * there is no filter for it at this time.
- */
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
- !(*total_flags & FIF_FCSFAIL));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
- !(*total_flags & FIF_PLCPFAIL));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
- !(*total_flags & FIF_CONTROL));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
- rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
- !(*total_flags & FIF_ALLMULTI));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_BORADCAST, 0);
- rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
-}
-
-static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
- u32 short_retry, u32 long_retry)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
- rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
- rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
-
- return 0;
-}
-
-static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u64 tsf;
- u32 reg;
-
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
- tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
- rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
- tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
-
- return tsf;
-}
-
-static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
- rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
-}
-
-static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
- struct ieee80211_tx_control *control)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- /*
- * Just in case the ieee80211 doesn't set this,
- * but we need this queue set for the descriptor
- * initialization.
- */
- control->queue = IEEE80211_TX_QUEUE_BEACON;
-
- /*
- * We need to append the descriptor in front of the
- * beacon frame.
- */
- if (skb_headroom(skb) < TXD_DESC_SIZE) {
- if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
- dev_kfree_skb(skb);
- return -ENOMEM;
- }
- }
-
- /*
- * First we create the beacon.
- */
- skb_push(skb, TXD_DESC_SIZE);
- memset(skb->data, 0, TXD_DESC_SIZE);
-
- rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
- (struct ieee80211_hdr *)(skb->data +
- TXD_DESC_SIZE),
- skb->len - TXD_DESC_SIZE, control);
-
- /*
- * Write entire beacon with descriptor to register,
- * and kick the beacon generator.
- */
- rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
- skb->data, skb->len);
- rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
-
- return 0;
-}
-
-static const struct ieee80211_ops rt61pci_mac80211_ops = {
- .tx = rt2x00mac_tx,
- .start = rt2x00mac_start,
- .stop = rt2x00mac_stop,
- .add_interface = rt2x00mac_add_interface,
- .remove_interface = rt2x00mac_remove_interface,
- .config = rt2x00mac_config,
- .config_interface = rt2x00mac_config_interface,
- .configure_filter = rt61pci_configure_filter,
- .get_stats = rt2x00mac_get_stats,
- .set_retry_limit = rt61pci_set_retry_limit,
- .erp_ie_changed = rt2x00mac_erp_ie_changed,
- .conf_tx = rt2x00mac_conf_tx,
- .get_tx_stats = rt2x00mac_get_tx_stats,
- .get_tsf = rt61pci_get_tsf,
- .reset_tsf = rt61pci_reset_tsf,
- .beacon_update = rt61pci_beacon_update,
-};
-
-static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
- .irq_handler = rt61pci_interrupt,
- .probe_hw = rt61pci_probe_hw,
- .get_firmware_name = rt61pci_get_firmware_name,
- .load_firmware = rt61pci_load_firmware,
- .initialize = rt2x00pci_initialize,
- .uninitialize = rt2x00pci_uninitialize,
- .set_device_state = rt61pci_set_device_state,
- .rfkill_poll = rt61pci_rfkill_poll,
- .link_stats = rt61pci_link_stats,
- .reset_tuner = rt61pci_reset_tuner,
- .link_tuner = rt61pci_link_tuner,
- .write_tx_desc = rt61pci_write_tx_desc,
- .write_tx_data = rt2x00pci_write_tx_data,
- .kick_tx_queue = rt61pci_kick_tx_queue,
- .fill_rxdone = rt61pci_fill_rxdone,
- .config_mac_addr = rt61pci_config_mac_addr,
- .config_bssid = rt61pci_config_bssid,
- .config_type = rt61pci_config_type,
- .config_preamble = rt61pci_config_preamble,
- .config = rt61pci_config,
-};
-
-static const struct rt2x00_ops rt61pci_ops = {
- .name = DRV_NAME,
- .rxd_size = RXD_DESC_SIZE,
- .txd_size = TXD_DESC_SIZE,
- .eeprom_size = EEPROM_SIZE,
- .rf_size = RF_SIZE,
- .lib = &rt61pci_rt2x00_ops,
- .hw = &rt61pci_mac80211_ops,
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
- .debugfs = &rt61pci_rt2x00debug,
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-};
-
-/*
- * RT61pci module information.
- */
-static struct pci_device_id rt61pci_device_table[] = {
- /* RT2561s */
- { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
- /* RT2561 v2 */
- { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
- /* RT2661 */
- { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
- { 0, }
-};
-
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
-MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
- "PCI & PCMCIA chipset based cards");
-MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
-MODULE_FIRMWARE(FIRMWARE_RT2561);
-MODULE_FIRMWARE(FIRMWARE_RT2561s);
-MODULE_FIRMWARE(FIRMWARE_RT2661);
-MODULE_LICENSE("GPL");
-
-static struct pci_driver rt61pci_driver = {
- .name = DRV_NAME,
- .id_table = rt61pci_device_table,
- .probe = rt2x00pci_probe,
- .remove = __devexit_p(rt2x00pci_remove),
- .suspend = rt2x00pci_suspend,
- .resume = rt2x00pci_resume,
-};
-
-static int __init rt61pci_init(void)
-{
- return pci_register_driver(&rt61pci_driver);
-}
-
-static void __exit rt61pci_exit(void)
-{
- pci_unregister_driver(&rt61pci_driver);
-}
-
-module_init(rt61pci_init);
-module_exit(rt61pci_exit);
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt61pci
- Abstract: Data structures and registers for the rt61pci module.
- Supported chipsets: RT2561, RT2561s, RT2661.
- */
-
-#ifndef RT61PCI_H
-#define RT61PCI_H
-
-/*
- * RF chip defines.
- */
-#define RF5225 0x0001
-#define RF5325 0x0002
-#define RF2527 0x0003
-#define RF2529 0x0004
-
-/*
- * Signal information.
- * Defaul offset is required for RSSI <-> dBm conversion.
- */
-#define MAX_SIGNAL 100
-#define MAX_RX_SSI -1
-#define DEFAULT_RSSI_OFFSET 120
-
-/*
- * Register layout information.
- */
-#define CSR_REG_BASE 0x3000
-#define CSR_REG_SIZE 0x04b0
-#define EEPROM_BASE 0x0000
-#define EEPROM_SIZE 0x0100
-#define BBP_SIZE 0x0080
-#define RF_SIZE 0x0014
-
-/*
- * PCI registers.
- */
-
-/*
- * PCI Configuration Header
- */
-#define PCI_CONFIG_HEADER_VENDOR 0x0000
-#define PCI_CONFIG_HEADER_DEVICE 0x0002
-
-/*
- * HOST_CMD_CSR: For HOST to interrupt embedded processor
- */
-#define HOST_CMD_CSR 0x0008
-#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
-#define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
-
-/*
- * MCU_CNTL_CSR
- * SELECT_BANK: Select 8051 program bank.
- * RESET: Enable 8051 reset state.
- * READY: Ready state for 8051.
- */
-#define MCU_CNTL_CSR 0x000c
-#define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
-#define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
-#define MCU_CNTL_CSR_READY FIELD32(0x00000004)
-
-/*
- * SOFT_RESET_CSR
- */
-#define SOFT_RESET_CSR 0x0010
-
-/*
- * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
- */
-#define MCU_INT_SOURCE_CSR 0x0014
-#define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
-#define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
-#define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
-#define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
-#define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
-#define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
-#define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
-#define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
-#define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
-#define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
-
-/*
- * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
- */
-#define MCU_INT_MASK_CSR 0x0018
-#define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
-#define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
-#define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
-#define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
-#define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
-#define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
-#define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
-#define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
-#define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
-#define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
-
-/*
- * PCI_USEC_CSR
- */
-#define PCI_USEC_CSR 0x001c
-
-/*
- * Security key table memory.
- * 16 entries 32-byte for shared key table
- * 64 entries 32-byte for pairwise key table
- * 64 entries 8-byte for pairwise ta key table
- */
-#define SHARED_KEY_TABLE_BASE 0x1000
-#define PAIRWISE_KEY_TABLE_BASE 0x1200
-#define PAIRWISE_TA_TABLE_BASE 0x1a00
-
-struct hw_key_entry {
- u8 key[16];
- u8 tx_mic[8];
- u8 rx_mic[8];
-} __attribute__ ((packed));
-
-struct hw_pairwise_ta_entry {
- u8 address[6];
- u8 reserved[2];
-} __attribute__ ((packed));
-
-/*
- * Other on-chip shared memory space.
- */
-#define HW_CIS_BASE 0x2000
-#define HW_NULL_BASE 0x2b00
-
-/*
- * Since NULL frame won't be that long (256 byte),
- * We steal 16 tail bytes to save debugging settings.
- */
-#define HW_DEBUG_SETTING_BASE 0x2bf0
-
-/*
- * On-chip BEACON frame space.
- */
-#define HW_BEACON_BASE0 0x2c00
-#define HW_BEACON_BASE1 0x2d00
-#define HW_BEACON_BASE2 0x2e00
-#define HW_BEACON_BASE3 0x2f00
-#define HW_BEACON_OFFSET 0x0100
-
-/*
- * HOST-MCU shared memory.
- */
-
-/*
- * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
- */
-#define H2M_MAILBOX_CSR 0x2100
-#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
-#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
-#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
-#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
-
-/*
- * MCU_LEDCS: LED control for MCU Mailbox.
- */
-#define MCU_LEDCS_LED_MODE FIELD16(0x001f)
-#define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
-#define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
-#define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
-#define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
-#define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
-#define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
-#define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
-#define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
-#define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
-#define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
-#define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
-
-/*
- * M2H_CMD_DONE_CSR.
- */
-#define M2H_CMD_DONE_CSR 0x2104
-
-/*
- * MCU_TXOP_ARRAY_BASE.
- */
-#define MCU_TXOP_ARRAY_BASE 0x2110
-
-/*
- * MAC Control/Status Registers(CSR).
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * MAC_CSR0: ASIC revision number.
- */
-#define MAC_CSR0 0x3000
-
-/*
- * MAC_CSR1: System control register.
- * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
- * BBP_RESET: Hardware reset BBP.
- * HOST_READY: Host is ready after initialization, 1: ready.
- */
-#define MAC_CSR1 0x3004
-#define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
-#define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
-#define MAC_CSR1_HOST_READY FIELD32(0x00000004)
-
-/*
- * MAC_CSR2: STA MAC register 0.
- */
-#define MAC_CSR2 0x3008
-#define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
-#define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
-#define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
-#define MAC_CSR2_BYTE3 FIELD32(0xff000000)
-
-/*
- * MAC_CSR3: STA MAC register 1.
- */
-#define MAC_CSR3 0x300c
-#define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
-#define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
-#define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
-
-/*
- * MAC_CSR4: BSSID register 0.
- */
-#define MAC_CSR4 0x3010
-#define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
-#define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
-#define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
-#define MAC_CSR4_BYTE3 FIELD32(0xff000000)
-
-/*
- * MAC_CSR5: BSSID register 1.
- * BSS_ID_MASK: 3: one BSSID, 0: 4 BSSID, 2 or 1: 2 BSSID.
- */
-#define MAC_CSR5 0x3014
-#define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
-#define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
-#define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
-
-/*
- * MAC_CSR6: Maximum frame length register.
- */
-#define MAC_CSR6 0x3018
-#define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
-
-/*
- * MAC_CSR7: Reserved
- */
-#define MAC_CSR7 0x301c
-
-/*
- * MAC_CSR8: SIFS/EIFS register.
- * All units are in US.
- */
-#define MAC_CSR8 0x3020
-#define MAC_CSR8_SIFS FIELD32(0x000000ff)
-#define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
-#define MAC_CSR8_EIFS FIELD32(0xffff0000)
-
-/*
- * MAC_CSR9: Back-Off control register.
- * SLOT_TIME: Slot time, default is 20us for 802.11BG.
- * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
- * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
- * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
- */
-#define MAC_CSR9 0x3024
-#define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
-#define MAC_CSR9_CWMIN FIELD32(0x00000f00)
-#define MAC_CSR9_CWMAX FIELD32(0x0000f000)
-#define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
-
-/*
- * MAC_CSR10: Power state configuration.
- */
-#define MAC_CSR10 0x3028
-
-/*
- * MAC_CSR11: Power saving transition time register.
- * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
- * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
- * WAKEUP_LATENCY: In unit of TU.
- */
-#define MAC_CSR11 0x302c
-#define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
-#define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
-#define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
-#define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
-
-/*
- * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
- * CURRENT_STATE: 0:sleep, 1:awake.
- * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
- * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
- */
-#define MAC_CSR12 0x3030
-#define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
-#define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
-#define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
-#define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
-
-/*
- * MAC_CSR13: GPIO.
- */
-#define MAC_CSR13 0x3034
-#define MAC_CSR13_BIT0 FIELD32(0x00000001)
-#define MAC_CSR13_BIT1 FIELD32(0x00000002)
-#define MAC_CSR13_BIT2 FIELD32(0x00000004)
-#define MAC_CSR13_BIT3 FIELD32(0x00000008)
-#define MAC_CSR13_BIT4 FIELD32(0x00000010)
-#define MAC_CSR13_BIT5 FIELD32(0x00000020)
-#define MAC_CSR13_BIT6 FIELD32(0x00000040)
-#define MAC_CSR13_BIT7 FIELD32(0x00000080)
-#define MAC_CSR13_BIT8 FIELD32(0x00000100)
-#define MAC_CSR13_BIT9 FIELD32(0x00000200)
-#define MAC_CSR13_BIT10 FIELD32(0x00000400)
-#define MAC_CSR13_BIT11 FIELD32(0x00000800)
-#define MAC_CSR13_BIT12 FIELD32(0x00001000)
-
-/*
- * MAC_CSR14: LED control register.
- * ON_PERIOD: On period, default 70ms.
- * OFF_PERIOD: Off period, default 30ms.
- * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
- * SW_LED: s/w LED, 1: ON, 0: OFF.
- * HW_LED_POLARITY: 0: active low, 1: active high.
- */
-#define MAC_CSR14 0x3038
-#define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
-#define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
-#define MAC_CSR14_HW_LED FIELD32(0x00010000)
-#define MAC_CSR14_SW_LED FIELD32(0x00020000)
-#define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
-#define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
-
-/*
- * MAC_CSR15: NAV control.
- */
-#define MAC_CSR15 0x303c
-
-/*
- * TXRX control registers.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * TXRX_CSR0: TX/RX configuration register.
- * TSF_OFFSET: Default is 24.
- * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
- * DISABLE_RX: Disable Rx engine.
- * DROP_CRC: Drop CRC error.
- * DROP_PHYSICAL: Drop physical error.
- * DROP_CONTROL: Drop control frame.
- * DROP_NOT_TO_ME: Drop not to me unicast frame.
- * DROP_TO_DS: Drop fram ToDs bit is true.
- * DROP_VERSION_ERROR: Drop version error frame.
- * DROP_MULTICAST: Drop multicast frames.
- * DROP_BORADCAST: Drop broadcast frames.
- * ROP_ACK_CTS: Drop received ACK and CTS.
- */
-#define TXRX_CSR0 0x3040
-#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
-#define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
-#define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
-#define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
-#define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
-#define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
-#define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
-#define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
-#define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
-#define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
-#define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
-#define TXRX_CSR0_DROP_BORADCAST FIELD32(0x01000000)
-#define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
-#define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
-
-/*
- * TXRX_CSR1
- */
-#define TXRX_CSR1 0x3044
-#define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
-#define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
-#define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
-#define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
-#define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
-#define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
-#define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
-#define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
-
-/*
- * TXRX_CSR2
- */
-#define TXRX_CSR2 0x3048
-#define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
-#define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
-#define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
-#define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
-#define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
-#define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
-#define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
-#define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
-
-/*
- * TXRX_CSR3
- */
-#define TXRX_CSR3 0x304c
-#define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
-#define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
-#define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
-#define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
-#define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
-#define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
-#define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
-#define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
-
-/*
- * TXRX_CSR4: Auto-Responder/Tx-retry register.
- * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
- * OFDM_TX_RATE_DOWN: 1:enable.
- * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
- * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
- */
-#define TXRX_CSR4 0x3050
-#define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
-#define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
-#define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
-#define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
-#define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
-#define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
-#define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
-#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
-#define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
-#define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
-
-/*
- * TXRX_CSR5
- */
-#define TXRX_CSR5 0x3054
-
-/*
- * TXRX_CSR6: ACK/CTS payload consumed time
- */
-#define TXRX_CSR6 0x3058
-
-/*
- * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
- */
-#define TXRX_CSR7 0x305c
-#define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
-#define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
-#define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
-#define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
-
-/*
- * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
- */
-#define TXRX_CSR8 0x3060
-#define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
-#define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
-#define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
-#define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
-
-/*
- * TXRX_CSR9: Synchronization control register.
- * BEACON_INTERVAL: In unit of 1/16 TU.
- * TSF_TICKING: Enable TSF auto counting.
- * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
- * BEACON_GEN: Enable beacon generator.
- */
-#define TXRX_CSR9 0x3064
-#define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
-#define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
-#define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
-#define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
-#define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
-#define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
-
-/*
- * TXRX_CSR10: BEACON alignment.
- */
-#define TXRX_CSR10 0x3068
-
-/*
- * TXRX_CSR11: AES mask.
- */
-#define TXRX_CSR11 0x306c
-
-/*
- * TXRX_CSR12: TSF low 32.
- */
-#define TXRX_CSR12 0x3070
-#define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
-
-/*
- * TXRX_CSR13: TSF high 32.
- */
-#define TXRX_CSR13 0x3074
-#define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
-
-/*
- * TXRX_CSR14: TBTT timer.
- */
-#define TXRX_CSR14 0x3078
-
-/*
- * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
- */
-#define TXRX_CSR15 0x307c
-
-/*
- * PHY control registers.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * PHY_CSR0: RF/PS control.
- */
-#define PHY_CSR0 0x3080
-#define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
-#define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
-
-/*
- * PHY_CSR1
- */
-#define PHY_CSR1 0x3084
-
-/*
- * PHY_CSR2: Pre-TX BBP control.
- */
-#define PHY_CSR2 0x3088
-
-/*
- * PHY_CSR3: BBP serial control register.
- * VALUE: Register value to program into BBP.
- * REG_NUM: Selected BBP register.
- * READ_CONTROL: 0: Write BBP, 1: Read BBP.
- * BUSY: 1: ASIC is busy execute BBP programming.
- */
-#define PHY_CSR3 0x308c
-#define PHY_CSR3_VALUE FIELD32(0x000000ff)
-#define PHY_CSR3_REGNUM FIELD32(0x00007f00)
-#define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
-#define PHY_CSR3_BUSY FIELD32(0x00010000)
-
-/*
- * PHY_CSR4: RF serial control register
- * VALUE: Register value (include register id) serial out to RF/IF chip.
- * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
- * IF_SELECT: 1: select IF to program, 0: select RF to program.
- * PLL_LD: RF PLL_LD status.
- * BUSY: 1: ASIC is busy execute RF programming.
- */
-#define PHY_CSR4 0x3090
-#define PHY_CSR4_VALUE FIELD32(0x00ffffff)
-#define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
-#define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
-#define PHY_CSR4_PLL_LD FIELD32(0x40000000)
-#define PHY_CSR4_BUSY FIELD32(0x80000000)
-
-/*
- * PHY_CSR5: RX to TX signal switch timing control.
- */
-#define PHY_CSR5 0x3094
-#define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
-
-/*
- * PHY_CSR6: TX to RX signal timing control.
- */
-#define PHY_CSR6 0x3098
-#define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
-
-/*
- * PHY_CSR7: TX DAC switching timing control.
- */
-#define PHY_CSR7 0x309c
-
-/*
- * Security control register.
- */
-
-/*
- * SEC_CSR0: Shared key table control.
- */
-#define SEC_CSR0 0x30a0
-#define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
-#define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
-#define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
-#define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
-#define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
-#define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
-#define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
-#define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
-#define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
-#define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
-#define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
-#define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
-#define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
-#define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
-#define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
-#define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
-
-/*
- * SEC_CSR1: Shared key table security mode register.
- */
-#define SEC_CSR1 0x30a4
-#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
-#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
-#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
-#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
-#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
-#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
-#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
-#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
-
-/*
- * Pairwise key table valid bitmap registers.
- * SEC_CSR2: pairwise key table valid bitmap 0.
- * SEC_CSR3: pairwise key table valid bitmap 1.
- */
-#define SEC_CSR2 0x30a8
-#define SEC_CSR3 0x30ac
-
-/*
- * SEC_CSR4: Pairwise key table lookup control.
- */
-#define SEC_CSR4 0x30b0
-
-/*
- * SEC_CSR5: shared key table security mode register.
- */
-#define SEC_CSR5 0x30b4
-#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
-#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
-#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
-#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
-#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
-#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
-#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
-#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
-
-/*
- * STA control registers.
- */
-
-/*
- * STA_CSR0: RX PLCP error count & RX FCS error count.
- */
-#define STA_CSR0 0x30c0
-#define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
-#define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
-
-/*
- * STA_CSR1: RX False CCA count & RX LONG frame count.
- */
-#define STA_CSR1 0x30c4
-#define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
-#define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
-
-/*
- * STA_CSR2: TX Beacon count and RX FIFO overflow count.
- */
-#define STA_CSR2 0x30c8
-#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
-#define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
-
-/*
- * STA_CSR3: TX Beacon count.
- */
-#define STA_CSR3 0x30cc
-#define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
-
-/*
- * STA_CSR4: TX Result status register.
- * VALID: 1:This register contains a valid TX result.
- */
-#define STA_CSR4 0x30d0
-#define STA_CSR4_VALID FIELD32(0x00000001)
-#define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
-#define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
-#define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
-#define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
-#define STA_CSR4_TXRATE FIELD32(0x000f0000)
-
-/*
- * QOS control registers.
- */
-
-/*
- * QOS_CSR0: TXOP holder MAC address register.
- */
-#define QOS_CSR0 0x30e0
-#define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
-#define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
-#define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
-#define QOS_CSR0_BYTE3 FIELD32(0xff000000)
-
-/*
- * QOS_CSR1: TXOP holder MAC address register.
- */
-#define QOS_CSR1 0x30e4
-#define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
-#define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
-
-/*
- * QOS_CSR2: TXOP holder timeout register.
- */
-#define QOS_CSR2 0x30e8
-
-/*
- * RX QOS-CFPOLL MAC address register.
- * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
- * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
- */
-#define QOS_CSR3 0x30ec
-#define QOS_CSR4 0x30f0
-
-/*
- * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
- */
-#define QOS_CSR5 0x30f4
-
-/*
- * Host DMA registers.
- */
-
-/*
- * AC0_BASE_CSR: AC_BK base address.
- */
-#define AC0_BASE_CSR 0x3400
-#define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * AC1_BASE_CSR: AC_BE base address.
- */
-#define AC1_BASE_CSR 0x3404
-#define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * AC2_BASE_CSR: AC_VI base address.
- */
-#define AC2_BASE_CSR 0x3408
-#define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * AC3_BASE_CSR: AC_VO base address.
- */
-#define AC3_BASE_CSR 0x340c
-#define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * MGMT_BASE_CSR: MGMT ring base address.
- */
-#define MGMT_BASE_CSR 0x3410
-#define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
- */
-#define TX_RING_CSR0 0x3418
-#define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
-#define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
-#define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
-#define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
-
-/*
- * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
- * TXD_SIZE: In unit of 32-bit.
- */
-#define TX_RING_CSR1 0x341c
-#define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
-#define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
-#define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
-
-/*
- * AIFSN_CSR: AIFSN for each EDCA AC.
- * AIFSN0: For AC_BK.
- * AIFSN1: For AC_BE.
- * AIFSN2: For AC_VI.
- * AIFSN3: For AC_VO.
- */
-#define AIFSN_CSR 0x3420
-#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
-#define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
-#define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
-#define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
-
-/*
- * CWMIN_CSR: CWmin for each EDCA AC.
- * CWMIN0: For AC_BK.
- * CWMIN1: For AC_BE.
- * CWMIN2: For AC_VI.
- * CWMIN3: For AC_VO.
- */
-#define CWMIN_CSR 0x3424
-#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
-#define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
-#define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
-#define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
-
-/*
- * CWMAX_CSR: CWmax for each EDCA AC.
- * CWMAX0: For AC_BK.
- * CWMAX1: For AC_BE.
- * CWMAX2: For AC_VI.
- * CWMAX3: For AC_VO.
- */
-#define CWMAX_CSR 0x3428
-#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
-#define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
-#define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
-#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
-
-/*
- * TX_DMA_DST_CSR: TX DMA destination
- * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
- */
-#define TX_DMA_DST_CSR 0x342c
-#define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
-#define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
-#define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
-#define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
-#define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
-
-/*
- * TX_CNTL_CSR: KICK/Abort TX.
- * KICK_TX_AC0: For AC_BK.
- * KICK_TX_AC1: For AC_BE.
- * KICK_TX_AC2: For AC_VI.
- * KICK_TX_AC3: For AC_VO.
- * ABORT_TX_AC0: For AC_BK.
- * ABORT_TX_AC1: For AC_BE.
- * ABORT_TX_AC2: For AC_VI.
- * ABORT_TX_AC3: For AC_VO.
- */
-#define TX_CNTL_CSR 0x3430
-#define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
-#define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
-#define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
-#define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
-#define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
-#define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
-#define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
-#define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
-#define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
-#define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
-
-/*
- * LOAD_TX_RING_CSR: Load RX de
- */
-#define LOAD_TX_RING_CSR 0x3434
-#define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
-#define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
-#define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
-#define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
-#define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
-
-/*
- * Several read-only registers, for debugging.
- */
-#define AC0_TXPTR_CSR 0x3438
-#define AC1_TXPTR_CSR 0x343c
-#define AC2_TXPTR_CSR 0x3440
-#define AC3_TXPTR_CSR 0x3444
-#define MGMT_TXPTR_CSR 0x3448
-
-/*
- * RX_BASE_CSR
- */
-#define RX_BASE_CSR 0x3450
-#define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
-
-/*
- * RX_RING_CSR.
- * RXD_SIZE: In unit of 32-bit.
- */
-#define RX_RING_CSR 0x3454
-#define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
-#define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
-#define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
-
-/*
- * RX_CNTL_CSR
- */
-#define RX_CNTL_CSR 0x3458
-#define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
-#define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
-
-/*
- * RXPTR_CSR: Read-only, for debugging.
- */
-#define RXPTR_CSR 0x345c
-
-/*
- * PCI_CFG_CSR
- */
-#define PCI_CFG_CSR 0x3460
-
-/*
- * BUF_FORMAT_CSR
- */
-#define BUF_FORMAT_CSR 0x3464
-
-/*
- * INT_SOURCE_CSR: Interrupt source register.
- * Write one to clear corresponding bit.
- */
-#define INT_SOURCE_CSR 0x3468
-#define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
-#define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
-#define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
-#define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
-#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
-#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
-#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
-#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
-#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
-#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
-
-/*
- * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
- * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
- */
-#define INT_MASK_CSR 0x346c
-#define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
-#define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
-#define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
-#define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
-#define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
-#define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
-#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
-#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
-#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
-#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
-#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
-#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
-
-/*
- * E2PROM_CSR: EEPROM control register.
- * RELOAD: Write 1 to reload eeprom content.
- * TYPE_93C46: 1: 93c46, 0:93c66.
- * LOAD_STATUS: 1:loading, 0:done.
- */
-#define E2PROM_CSR 0x3470
-#define E2PROM_CSR_RELOAD FIELD32(0x00000001)
-#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
-#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
-#define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
-#define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
-#define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
-#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
-
-/*
- * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
- * AC0_TX_OP: For AC_BK, in unit of 32us.
- * AC1_TX_OP: For AC_BE, in unit of 32us.
- */
-#define AC_TXOP_CSR0 0x3474
-#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
-#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
-
-/*
- * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
- * AC2_TX_OP: For AC_VI, in unit of 32us.
- * AC3_TX_OP: For AC_VO, in unit of 32us.
- */
-#define AC_TXOP_CSR1 0x3478
-#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
-#define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
-
-/*
- * DMA_STATUS_CSR
- */
-#define DMA_STATUS_CSR 0x3480
-
-/*
- * TEST_MODE_CSR
- */
-#define TEST_MODE_CSR 0x3484
-
-/*
- * UART0_TX_CSR
- */
-#define UART0_TX_CSR 0x3488
-
-/*
- * UART0_RX_CSR
- */
-#define UART0_RX_CSR 0x348c
-
-/*
- * UART0_FRAME_CSR
- */
-#define UART0_FRAME_CSR 0x3490
-
-/*
- * UART0_BUFFER_CSR
- */
-#define UART0_BUFFER_CSR 0x3494
-
-/*
- * IO_CNTL_CSR
- */
-#define IO_CNTL_CSR 0x3498
-
-/*
- * UART_INT_SOURCE_CSR
- */
-#define UART_INT_SOURCE_CSR 0x34a8
-
-/*
- * UART_INT_MASK_CSR
- */
-#define UART_INT_MASK_CSR 0x34ac
-
-/*
- * PBF_QUEUE_CSR
- */
-#define PBF_QUEUE_CSR 0x34b0
-
-/*
- * Firmware DMA registers.
- * Firmware DMA registers are dedicated for MCU usage
- * and should not be touched by host driver.
- * Therefore we skip the definition of these registers.
- */
-#define FW_TX_BASE_CSR 0x34c0
-#define FW_TX_START_CSR 0x34c4
-#define FW_TX_LAST_CSR 0x34c8
-#define FW_MODE_CNTL_CSR 0x34cc
-#define FW_TXPTR_CSR 0x34d0
-
-/*
- * 8051 firmware image.
- */
-#define FIRMWARE_RT2561 "rt2561.bin"
-#define FIRMWARE_RT2561s "rt2561s.bin"
-#define FIRMWARE_RT2661 "rt2661.bin"
-#define FIRMWARE_IMAGE_BASE 0x4000
-
-/*
- * BBP registers.
- * The wordsize of the BBP is 8 bits.
- */
-
-/*
- * R2
- */
-#define BBP_R2_BG_MODE FIELD8(0x20)
-
-/*
- * R3
- */
-#define BBP_R3_SMART_MODE FIELD8(0x01)
-
-/*
- * R4: RX antenna control
- * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
- */
-#define BBP_R4_RX_ANTENNA FIELD8(0x03)
-#define BBP_R4_RX_FRAME_END FIELD8(0x20)
-
-/*
- * R77
- */
-#define BBP_R77_PAIR FIELD8(0x03)
-
-/*
- * RF registers
- */
-
-/*
- * RF 3
- */
-#define RF3_TXPOWER FIELD32(0x00003e00)
-
-/*
- * RF 4
- */
-#define RF4_FREQ_OFFSET FIELD32(0x0003f000)
-
-/*
- * EEPROM content.
- * The wordsize of the EEPROM is 16 bits.
- */
-
-/*
- * HW MAC address.
- */
-#define EEPROM_MAC_ADDR_0 0x0002
-#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR1 0x0004
-#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR_2 0x0006
-#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
-
-/*
- * EEPROM antenna.
- * ANTENNA_NUM: Number of antenna's.
- * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
- * DYN_TXAGC: Dynamic TX AGC control.
- * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
- * RF_TYPE: Rf_type of this adapter.
- */
-#define EEPROM_ANTENNA 0x0010
-#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
-#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
-#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
-#define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
-#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
-#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
-#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
-
-/*
- * EEPROM NIC config.
- * ENABLE_DIVERSITY: 1:enable, 0:disable.
- * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
- * CARDBUS_ACCEL: 0:enable, 1:disable.
- * EXTERNAL_LNA_A: External LNA enable for 5G.
- */
-#define EEPROM_NIC 0x0011
-#define EEPROM_NIC_ENABLE_DIVERSITY FIELD16(0x0001)
-#define EEPROM_NIC_TX_DIVERSITY FIELD16(0x0002)
-#define EEPROM_NIC_TX_RX_FIXED FIELD16(0x000c)
-#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0010)
-#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0020)
-#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0040)
-
-/*
- * EEPROM geography.
- * GEO_A: Default geographical setting for 5GHz band
- * GEO: Default geographical setting.
- */
-#define EEPROM_GEOGRAPHY 0x0012
-#define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
-#define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
-
-/*
- * EEPROM BBP.
- */
-#define EEPROM_BBP_START 0x0013
-#define EEPROM_BBP_SIZE 16
-#define EEPROM_BBP_VALUE FIELD16(0x00ff)
-#define EEPROM_BBP_REG_ID FIELD16(0xff00)
-
-/*
- * EEPROM TXPOWER 802.11G
- */
-#define EEPROM_TXPOWER_G_START 0x0023
-#define EEPROM_TXPOWER_G_SIZE 7
-#define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
-#define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
-
-/*
- * EEPROM Frequency
- */
-#define EEPROM_FREQ 0x002f
-#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
-#define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
-#define EEPROM_FREQ_SEQ FIELD16(0x0300)
-
-/*
- * EEPROM LED.
- * POLARITY_RDY_G: Polarity RDY_G setting.
- * POLARITY_RDY_A: Polarity RDY_A setting.
- * POLARITY_ACT: Polarity ACT setting.
- * POLARITY_GPIO_0: Polarity GPIO0 setting.
- * POLARITY_GPIO_1: Polarity GPIO1 setting.
- * POLARITY_GPIO_2: Polarity GPIO2 setting.
- * POLARITY_GPIO_3: Polarity GPIO3 setting.
- * POLARITY_GPIO_4: Polarity GPIO4 setting.
- * LED_MODE: Led mode.
- */
-#define EEPROM_LED 0x0030
-#define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
-#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
-#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
-#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
-#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
-#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
-#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
-#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
-#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
-
-/*
- * EEPROM TXPOWER 802.11A
- */
-#define EEPROM_TXPOWER_A_START 0x0031
-#define EEPROM_TXPOWER_A_SIZE 12
-#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
-#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
-
-/*
- * EEPROM RSSI offset 802.11BG
- */
-#define EEPROM_RSSI_OFFSET_BG 0x004d
-#define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
-#define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
-
-/*
- * EEPROM RSSI offset 802.11A
- */
-#define EEPROM_RSSI_OFFSET_A 0x004e
-#define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
-#define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
-
-/*
- * MCU mailbox commands.
- */
-#define MCU_SLEEP 0x30
-#define MCU_WAKEUP 0x31
-#define MCU_LED 0x50
-#define MCU_LED_STRENGTH 0x52
-
-/*
- * DMA descriptor defines.
- */
-#define TXD_DESC_SIZE ( 16 * sizeof(struct data_desc) )
-#define RXD_DESC_SIZE ( 16 * sizeof(struct data_desc) )
-
-/*
- * TX descriptor format for TX, PRIO and Beacon Ring.
- */
-
-/*
- * Word0
- * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
- * KEY_TABLE: Use per-client pairwise KEY table.
- * KEY_INDEX:
- * Key index (0~31) to the pairwise KEY table.
- * 0~3 to shared KEY table 0 (BSS0).
- * 4~7 to shared KEY table 1 (BSS1).
- * 8~11 to shared KEY table 2 (BSS2).
- * 12~15 to shared KEY table 3 (BSS3).
- * BURST: Next frame belongs to same "burst" event.
- */
-#define TXD_W0_OWNER_NIC FIELD32(0x00000001)
-#define TXD_W0_VALID FIELD32(0x00000002)
-#define TXD_W0_MORE_FRAG FIELD32(0x00000004)
-#define TXD_W0_ACK FIELD32(0x00000008)
-#define TXD_W0_TIMESTAMP FIELD32(0x00000010)
-#define TXD_W0_OFDM FIELD32(0x00000020)
-#define TXD_W0_IFS FIELD32(0x00000040)
-#define TXD_W0_RETRY_MODE FIELD32(0x00000080)
-#define TXD_W0_TKIP_MIC FIELD32(0x00000100)
-#define TXD_W0_KEY_TABLE FIELD32(0x00000200)
-#define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
-#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
-#define TXD_W0_BURST FIELD32(0x10000000)
-#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
-
-/*
- * Word1
- * HOST_Q_ID: EDCA/HCCA queue ID.
- * HW_SEQUENCE: MAC overwrites the frame sequence number.
- * BUFFER_COUNT: Number of buffers in this TXD.
- */
-#define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
-#define TXD_W1_AIFSN FIELD32(0x000000f0)
-#define TXD_W1_CWMIN FIELD32(0x00000f00)
-#define TXD_W1_CWMAX FIELD32(0x0000f000)
-#define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
-#define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
-#define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
-#define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
-
-/*
- * Word2: PLCP information
- */
-#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
-#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
-#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
-#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
-
-/*
- * Word3
- */
-#define TXD_W3_IV FIELD32(0xffffffff)
-
-/*
- * Word4
- */
-#define TXD_W4_EIV FIELD32(0xffffffff)
-
-/*
- * Word5
- * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
- * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
- * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
- * WAITING_DMA_DONE_INT: TXD been filled with data
- * and waiting for TxDoneISR housekeeping.
- */
-#define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
-#define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
-#define TXD_W5_PID_TYPE FIELD32(0x0000e000)
-#define TXD_W5_TX_POWER FIELD32(0x00ff0000)
-#define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
-
-/*
- * the above 24-byte is called TXINFO and will be DMAed to MAC block
- * through TXFIFO. MAC block use this TXINFO to control the transmission
- * behavior of this frame.
- * The following fields are not used by MAC block.
- * They are used by DMA block and HOST driver only.
- * Once a frame has been DMA to ASIC, all the following fields are useless
- * to ASIC.
- */
-
-/*
- * Word6-10: Buffer physical address
- */
-#define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
-#define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
-#define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
-#define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
-#define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
-
-/*
- * Word11-13: Buffer length
- */
-#define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
-#define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
-#define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
-#define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
-#define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
-
-/*
- * Word14
- */
-#define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
-
-/*
- * Word15
- */
-#define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
-
-/*
- * RX descriptor format for RX Ring.
- */
-
-/*
- * Word0
- * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
- * KEY_INDEX: Decryption key actually used.
- */
-#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
-#define RXD_W0_DROP FIELD32(0x00000002)
-#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
-#define RXD_W0_MULTICAST FIELD32(0x00000008)
-#define RXD_W0_BROADCAST FIELD32(0x00000010)
-#define RXD_W0_MY_BSS FIELD32(0x00000020)
-#define RXD_W0_CRC_ERROR FIELD32(0x00000040)
-#define RXD_W0_OFDM FIELD32(0x00000080)
-#define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
-#define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
-#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
-#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
-
-/*
- * Word1
- * SIGNAL: RX raw data rate reported by BBP.
- */
-#define RXD_W1_SIGNAL FIELD32(0x000000ff)
-#define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
-#define RXD_W1_RSSI_LNA FIELD32(0x00006000)
-#define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
-
-/*
- * Word2
- * IV: Received IV of originally encrypted.
- */
-#define RXD_W2_IV FIELD32(0xffffffff)
-
-/*
- * Word3
- * EIV: Received EIV of originally encrypted.
- */
-#define RXD_W3_EIV FIELD32(0xffffffff)
-
-/*
- * Word4
- */
-#define RXD_W4_RESERVED FIELD32(0xffffffff)
-
-/*
- * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
- * and passed to the HOST driver.
- * The following fields are for DMA block and HOST usage only.
- * Can't be touched by ASIC MAC block.
- */
-
-/*
- * Word5
- */
-#define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
-
-/*
- * Word6-15: Reserved
- */
-#define RXD_W6_RESERVED FIELD32(0xffffffff)
-#define RXD_W7_RESERVED FIELD32(0xffffffff)
-#define RXD_W8_RESERVED FIELD32(0xffffffff)
-#define RXD_W9_RESERVED FIELD32(0xffffffff)
-#define RXD_W10_RESERVED FIELD32(0xffffffff)
-#define RXD_W11_RESERVED FIELD32(0xffffffff)
-#define RXD_W12_RESERVED FIELD32(0xffffffff)
-#define RXD_W13_RESERVED FIELD32(0xffffffff)
-#define RXD_W14_RESERVED FIELD32(0xffffffff)
-#define RXD_W15_RESERVED FIELD32(0xffffffff)
-
-/*
- * Macro's for converting txpower from EEPROM to dscape value
- * and from dscape value to register value.
- */
-#define MIN_TXPOWER 0
-#define MAX_TXPOWER 31
-#define DEFAULT_TXPOWER 24
-
-#define TXPOWER_FROM_DEV(__txpower) \
-({ \
- ((__txpower) > MAX_TXPOWER) ? \
- DEFAULT_TXPOWER : (__txpower); \
-})
-
-#define TXPOWER_TO_DEV(__txpower) \
-({ \
- ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
- (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
- (__txpower)); \
-})
-
-#endif /* RT61PCI_H */
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt73usb
- Abstract: rt73usb device specific routines.
- Supported chipsets: rt2571W & rt2671.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt73usb"
-
-#include <linux/delay.h>
-#include <linux/etherdevice.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/usb.h>
-
-#include "rt2x00.h"
-#include "rt2x00usb.h"
-#include "rt73usb.h"
-
-/*
- * Register access.
- * All access to the CSR registers will go through the methods
- * rt73usb_register_read and rt73usb_register_write.
- * BBP and RF register require indirect register access,
- * and use the CSR registers BBPCSR and RFCSR to achieve this.
- * These indirect registers work with busy bits,
- * and we will try maximal REGISTER_BUSY_COUNT times to access
- * the register while taking a REGISTER_BUSY_DELAY us delay
- * between each attampt. When the busy bit is still set at that time,
- * the access attempt is considered to have failed,
- * and we will print an error.
- */
-static inline void rt73usb_register_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned int offset, u32 *value)
-{
- __le32 reg;
- rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
- USB_VENDOR_REQUEST_IN, offset,
- ®, sizeof(u32), REGISTER_TIMEOUT);
- *value = le32_to_cpu(reg);
-}
-
-static inline void rt73usb_register_multiread(const struct rt2x00_dev
- *rt2x00dev,
- const unsigned int offset,
- void *value, const u32 length)
-{
- int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
- rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
- USB_VENDOR_REQUEST_IN, offset,
- value, length, timeout);
-}
-
-static inline void rt73usb_register_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int offset, u32 value)
-{
- __le32 reg = cpu_to_le32(value);
- rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
- USB_VENDOR_REQUEST_OUT, offset,
- ®, sizeof(u32), REGISTER_TIMEOUT);
-}
-
-static inline void rt73usb_register_multiwrite(const struct rt2x00_dev
- *rt2x00dev,
- const unsigned int offset,
- void *value, const u32 length)
-{
- int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
- rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
- USB_VENDOR_REQUEST_OUT, offset,
- value, length, timeout);
-}
-
-static u32 rt73usb_bbp_check(const struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- unsigned int i;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt73usb_register_read(rt2x00dev, PHY_CSR3, ®);
- if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
- break;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- return reg;
-}
-
-static void rt73usb_bbp_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u8 value)
-{
- u32 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt73usb_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
- ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
- return;
- }
-
- /*
- * Write the data into the BBP.
- */
- reg = 0;
- rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
- rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
- rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
- rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
-
- rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
-}
-
-static void rt73usb_bbp_read(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u8 *value)
-{
- u32 reg;
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt73usb_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
- ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
- return;
- }
-
- /*
- * Write the request into the BBP.
- */
- reg = 0;
- rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
- rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
- rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
-
- rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
-
- /*
- * Wait until the BBP becomes ready.
- */
- reg = rt73usb_bbp_check(rt2x00dev);
- if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
- ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
- *value = 0xff;
- return;
- }
-
- *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
-}
-
-static void rt73usb_rf_write(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, const u32 value)
-{
- u32 reg;
- unsigned int i;
-
- if (!word)
- return;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt73usb_register_read(rt2x00dev, PHY_CSR4, ®);
- if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
- goto rf_write;
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
- return;
-
-rf_write:
- reg = 0;
- rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
-
- /*
- * RF5225 and RF2527 contain 21 bits per RF register value,
- * all others contain 20 bits.
- */
- rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS,
- 20 + !!(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
- rt2x00_rf(&rt2x00dev->chip, RF2527)));
- rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
- rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
-
- rt73usb_register_write(rt2x00dev, PHY_CSR4, reg);
- rt2x00_rf_write(rt2x00dev, word, value);
-}
-
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
-
-static void rt73usb_read_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 *data)
-{
- rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static void rt73usb_write_csr(const struct rt2x00_dev *rt2x00dev,
- const unsigned int word, u32 data)
-{
- rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static const struct rt2x00debug rt73usb_rt2x00debug = {
- .owner = THIS_MODULE,
- .csr = {
- .read = rt73usb_read_csr,
- .write = rt73usb_write_csr,
- .word_size = sizeof(u32),
- .word_count = CSR_REG_SIZE / sizeof(u32),
- },
- .eeprom = {
- .read = rt2x00_eeprom_read,
- .write = rt2x00_eeprom_write,
- .word_size = sizeof(u16),
- .word_count = EEPROM_SIZE / sizeof(u16),
- },
- .bbp = {
- .read = rt73usb_bbp_read,
- .write = rt73usb_bbp_write,
- .word_size = sizeof(u8),
- .word_count = BBP_SIZE / sizeof(u8),
- },
- .rf = {
- .read = rt2x00_rf_read,
- .write = rt73usb_rf_write,
- .word_size = sizeof(u32),
- .word_count = RF_SIZE / sizeof(u32),
- },
-};
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
-/*
- * Configuration handlers.
- */
-static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
-{
- u32 tmp;
-
- tmp = le32_to_cpu(mac[1]);
- rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
- mac[1] = cpu_to_le32(tmp);
-
- rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
- (2 * sizeof(__le32)));
-}
-
-static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
-{
- u32 tmp;
-
- tmp = le32_to_cpu(bssid[1]);
- rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
- bssid[1] = cpu_to_le32(tmp);
-
- rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
- (2 * sizeof(__le32)));
-}
-
-static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
- const int tsf_sync)
-{
- u32 reg;
-
- /*
- * Clear current synchronisation setup.
- * For the Beacon base registers we only need to clear
- * the first byte since that byte contains the VALID and OWNER
- * bits which (when set to 0) will invalidate the entire beacon.
- */
- rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
- rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
- rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
- rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
- rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
-
- /*
- * Enable synchronisation.
- */
- rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
- rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
- rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
- rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
- rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, tsf_sync);
- rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
-}
-
-static void rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
- const int short_preamble,
- const int ack_timeout,
- const int ack_consume_time)
-{
- u32 reg;
-
- /*
- * When in atomic context, reschedule and let rt2x00lib
- * call this function again.
- */
- if (in_atomic()) {
- queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
- return;
- }
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
- rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
- rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
- !!short_preamble);
- rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
-}
-
-static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
- const int basic_rate_mask)
-{
- rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
-}
-
-static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
- struct rf_channel *rf, const int txpower)
-{
- u8 r3;
- u8 r94;
- u8 smart;
-
- rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
- rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
-
- smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
- rt2x00_rf(&rt2x00dev->chip, RF2527));
-
- rt73usb_bbp_read(rt2x00dev, 3, &r3);
- rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
- rt73usb_bbp_write(rt2x00dev, 3, r3);
-
- r94 = 6;
- if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
- r94 += txpower - MAX_TXPOWER;
- else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
- r94 += txpower;
- rt73usb_bbp_write(rt2x00dev, 94, r94);
-
- rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
- rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
- rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
- rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
-
- rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
- rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
- rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
- rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
-
- rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
- rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
- rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
- rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
-
- udelay(10);
-}
-
-static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
- const int txpower)
-{
- struct rf_channel rf;
-
- rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
- rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
- rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
- rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
-
- rt73usb_config_channel(rt2x00dev, &rf, txpower);
-}
-
-static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx,
- const int antenna_rx)
-{
- u8 r3;
- u8 r4;
- u8 r77;
-
- rt73usb_bbp_read(rt2x00dev, 3, &r3);
- rt73usb_bbp_read(rt2x00dev, 4, &r4);
- rt73usb_bbp_read(rt2x00dev, 77, &r77);
-
- rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
-
- switch (antenna_rx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
- !!(rt2x00dev->curr_hwmode != HWMODE_A));
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
-
- if (rt2x00dev->curr_hwmode == HWMODE_A)
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
- else
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
-
- if (rt2x00dev->curr_hwmode == HWMODE_A)
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
- else
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
- break;
- }
-
- rt73usb_bbp_write(rt2x00dev, 77, r77);
- rt73usb_bbp_write(rt2x00dev, 3, r3);
- rt73usb_bbp_write(rt2x00dev, 4, r4);
-}
-
-static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx,
- const int antenna_rx)
-{
- u8 r3;
- u8 r4;
- u8 r77;
-
- rt73usb_bbp_read(rt2x00dev, 3, &r3);
- rt73usb_bbp_read(rt2x00dev, 4, &r4);
- rt73usb_bbp_read(rt2x00dev, 77, &r77);
-
- rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
- rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
- !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
-
- switch (antenna_rx) {
- case ANTENNA_SW_DIVERSITY:
- case ANTENNA_HW_DIVERSITY:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
- break;
- case ANTENNA_A:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
- break;
- case ANTENNA_B:
- rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
- rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
- break;
- }
-
- rt73usb_bbp_write(rt2x00dev, 77, r77);
- rt73usb_bbp_write(rt2x00dev, 3, r3);
- rt73usb_bbp_write(rt2x00dev, 4, r4);
-}
-
-struct antenna_sel {
- u8 word;
- /*
- * value[0] -> non-LNA
- * value[1] -> LNA
- */
- u8 value[2];
-};
-
-static const struct antenna_sel antenna_sel_a[] = {
- { 96, { 0x58, 0x78 } },
- { 104, { 0x38, 0x48 } },
- { 75, { 0xfe, 0x80 } },
- { 86, { 0xfe, 0x80 } },
- { 88, { 0xfe, 0x80 } },
- { 35, { 0x60, 0x60 } },
- { 97, { 0x58, 0x58 } },
- { 98, { 0x58, 0x58 } },
-};
-
-static const struct antenna_sel antenna_sel_bg[] = {
- { 96, { 0x48, 0x68 } },
- { 104, { 0x2c, 0x3c } },
- { 75, { 0xfe, 0x80 } },
- { 86, { 0xfe, 0x80 } },
- { 88, { 0xfe, 0x80 } },
- { 35, { 0x50, 0x50 } },
- { 97, { 0x48, 0x48 } },
- { 98, { 0x48, 0x48 } },
-};
-
-static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
- const int antenna_tx, const int antenna_rx)
-{
- const struct antenna_sel *sel;
- unsigned int lna;
- unsigned int i;
- u32 reg;
-
- rt73usb_register_read(rt2x00dev, PHY_CSR0, ®);
-
- if (rt2x00dev->curr_hwmode == HWMODE_A) {
- sel = antenna_sel_a;
- lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
-
- rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 0);
- rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 1);
- } else {
- sel = antenna_sel_bg;
- lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
-
- rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 1);
- rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 0);
- }
-
- for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
- rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
-
- rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
-
- if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
- rt2x00_rf(&rt2x00dev->chip, RF5225))
- rt73usb_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
- else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
- rt2x00_rf(&rt2x00dev->chip, RF2527))
- rt73usb_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
-}
-
-static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
- struct rt2x00lib_conf *libconf)
-{
- u32 reg;
-
- rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
- rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
- rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
-
- rt73usb_register_read(rt2x00dev, MAC_CSR8, ®);
- rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
- rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
- rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
- rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
- rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
- rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
- rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
- rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
- libconf->conf->beacon_int * 16);
- rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
-}
-
-static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
- const unsigned int flags,
- struct rt2x00lib_conf *libconf)
-{
- if (flags & CONFIG_UPDATE_PHYMODE)
- rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
- if (flags & CONFIG_UPDATE_CHANNEL)
- rt73usb_config_channel(rt2x00dev, &libconf->rf,
- libconf->conf->power_level);
- if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
- rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
- if (flags & CONFIG_UPDATE_ANTENNA)
- rt73usb_config_antenna(rt2x00dev, libconf->conf->antenna_sel_tx,
- libconf->conf->antenna_sel_rx);
- if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
- rt73usb_config_duration(rt2x00dev, libconf);
-}
-
-/*
- * LED functions.
- */
-static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt73usb_register_read(rt2x00dev, MAC_CSR14, ®);
- rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
- rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
- rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
-
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
- if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
- rt2x00_set_field16(&rt2x00dev->led_reg,
- MCU_LEDCS_LINK_A_STATUS, 1);
- else
- rt2x00_set_field16(&rt2x00dev->led_reg,
- MCU_LEDCS_LINK_BG_STATUS, 1);
-
- rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
- rt2x00dev->led_reg, REGISTER_TIMEOUT);
-}
-
-static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
-{
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
-
- rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
- rt2x00dev->led_reg, REGISTER_TIMEOUT);
-}
-
-static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
-{
- u32 led;
-
- if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
- return;
-
- /*
- * Led handling requires a positive value for the rssi,
- * to do that correctly we need to add the correction.
- */
- rssi += rt2x00dev->rssi_offset;
-
- if (rssi <= 30)
- led = 0;
- else if (rssi <= 39)
- led = 1;
- else if (rssi <= 49)
- led = 2;
- else if (rssi <= 53)
- led = 3;
- else if (rssi <= 63)
- led = 4;
- else
- led = 5;
-
- rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
- rt2x00dev->led_reg, REGISTER_TIMEOUT);
-}
-
-/*
- * Link tuning
- */
-static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- /*
- * Update FCS error count from register.
- */
- rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
- rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
-
- /*
- * Update False CCA count from register.
- */
- rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
- reg = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
- rt2x00dev->link.false_cca =
- rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
-}
-
-static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
-{
- rt73usb_bbp_write(rt2x00dev, 17, 0x20);
- rt2x00dev->link.vgc_level = 0x20;
-}
-
-static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
- int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
- u8 r17;
- u8 up_bound;
- u8 low_bound;
-
- /*
- * Update Led strength
- */
- rt73usb_activity_led(rt2x00dev, rssi);
-
- rt73usb_bbp_read(rt2x00dev, 17, &r17);
-
- /*
- * Determine r17 bounds.
- */
- if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
- low_bound = 0x28;
- up_bound = 0x48;
-
- if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
- low_bound += 0x10;
- up_bound += 0x10;
- }
- } else {
- if (rssi > -82) {
- low_bound = 0x1c;
- up_bound = 0x40;
- } else if (rssi > -84) {
- low_bound = 0x1c;
- up_bound = 0x20;
- } else {
- low_bound = 0x1c;
- up_bound = 0x1c;
- }
-
- if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
- low_bound += 0x14;
- up_bound += 0x10;
- }
- }
-
- /*
- * Special big-R17 for very short distance
- */
- if (rssi > -35) {
- if (r17 != 0x60)
- rt73usb_bbp_write(rt2x00dev, 17, 0x60);
- return;
- }
-
- /*
- * Special big-R17 for short distance
- */
- if (rssi >= -58) {
- if (r17 != up_bound)
- rt73usb_bbp_write(rt2x00dev, 17, up_bound);
- return;
- }
-
- /*
- * Special big-R17 for middle-short distance
- */
- if (rssi >= -66) {
- low_bound += 0x10;
- if (r17 != low_bound)
- rt73usb_bbp_write(rt2x00dev, 17, low_bound);
- return;
- }
-
- /*
- * Special mid-R17 for middle distance
- */
- if (rssi >= -74) {
- if (r17 != (low_bound + 0x10))
- rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
- return;
- }
-
- /*
- * Special case: Change up_bound based on the rssi.
- * Lower up_bound when rssi is weaker then -74 dBm.
- */
- up_bound -= 2 * (-74 - rssi);
- if (low_bound > up_bound)
- up_bound = low_bound;
-
- if (r17 > up_bound) {
- rt73usb_bbp_write(rt2x00dev, 17, up_bound);
- return;
- }
-
- /*
- * r17 does not yet exceed upper limit, continue and base
- * the r17 tuning on the false CCA count.
- */
- if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
- r17 += 4;
- if (r17 > up_bound)
- r17 = up_bound;
- rt73usb_bbp_write(rt2x00dev, 17, r17);
- } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
- r17 -= 4;
- if (r17 < low_bound)
- r17 = low_bound;
- rt73usb_bbp_write(rt2x00dev, 17, r17);
- }
-}
-
-/*
- * Firmware name function.
- */
-static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
-{
- return FIRMWARE_RT2571;
-}
-
-/*
- * Initialization functions.
- */
-static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
- const size_t len)
-{
- unsigned int i;
- int status;
- u32 reg;
- char *ptr = data;
- char *cache;
- int buflen;
- int timeout;
-
- /*
- * Wait for stable hardware.
- */
- for (i = 0; i < 100; i++) {
- rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
- if (reg)
- break;
- msleep(1);
- }
-
- if (!reg) {
- ERROR(rt2x00dev, "Unstable hardware.\n");
- return -EBUSY;
- }
-
- /*
- * Write firmware to device.
- * We setup a seperate cache for this action,
- * since we are going to write larger chunks of data
- * then normally used cache size.
- */
- cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
- if (!cache) {
- ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
- return -ENOMEM;
- }
-
- for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
- buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
- timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
-
- memcpy(cache, ptr, buflen);
-
- rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
- USB_VENDOR_REQUEST_OUT,
- FIRMWARE_IMAGE_BASE + i, 0x0000,
- cache, buflen, timeout);
-
- ptr += buflen;
- }
-
- kfree(cache);
-
- /*
- * Send firmware request to device to load firmware,
- * we need to specify a long timeout time.
- */
- status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
- 0x0000, USB_MODE_FIRMWARE,
- REGISTER_TIMEOUT_FIRMWARE);
- if (status < 0) {
- ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
- return status;
- }
-
- rt73usb_disable_led(rt2x00dev);
-
- return 0;
-}
-
-static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
- rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
- rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
- rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR1, ®);
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
- rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
- rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
-
- /*
- * CCK TXD BBP registers
- */
- rt73usb_register_read(rt2x00dev, TXRX_CSR2, ®);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
- rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
- rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
-
- /*
- * OFDM TXD BBP registers
- */
- rt73usb_register_read(rt2x00dev, TXRX_CSR3, ®);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
- rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
- rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR7, ®);
- rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
- rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
- rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
- rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
- rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR8, ®);
- rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
- rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
- rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
- rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
- rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
-
- rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
-
- rt73usb_register_read(rt2x00dev, MAC_CSR6, ®);
- rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
- rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
-
- rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
-
- if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
- return -EBUSY;
-
- rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
-
- /*
- * Invalidate all Shared Keys (SEC_CSR0),
- * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
- */
- rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
- rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
- rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
-
- reg = 0x000023b0;
- if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
- rt2x00_rf(&rt2x00dev->chip, RF2527))
- rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1);
- rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
-
- rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
- rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
- rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
-
- rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
- rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
- rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
- rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
-
- rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
- rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
- rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
- rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
-
- rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
- rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
- rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
-
- /*
- * We must clear the error counters.
- * These registers are cleared on read,
- * so we may pass a useless variable to store the value.
- */
- rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
- rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
- rt73usb_register_read(rt2x00dev, STA_CSR2, ®);
-
- /*
- * Reset MAC and BBP registers.
- */
- rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
- rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
- rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
-
- rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
- rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
- rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
-
- rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
- rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
- rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
-
- return 0;
-}
-
-static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
-{
- unsigned int i;
- u16 eeprom;
- u8 reg_id;
- u8 value;
-
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt73usb_bbp_read(rt2x00dev, 0, &value);
- if ((value != 0xff) && (value != 0x00))
- goto continue_csr_init;
- NOTICE(rt2x00dev, "Waiting for BBP register.\n");
- udelay(REGISTER_BUSY_DELAY);
- }
-
- ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
- return -EACCES;
-
-continue_csr_init:
- rt73usb_bbp_write(rt2x00dev, 3, 0x80);
- rt73usb_bbp_write(rt2x00dev, 15, 0x30);
- rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
- rt73usb_bbp_write(rt2x00dev, 22, 0x38);
- rt73usb_bbp_write(rt2x00dev, 23, 0x06);
- rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
- rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
- rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
- rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
- rt73usb_bbp_write(rt2x00dev, 34, 0x12);
- rt73usb_bbp_write(rt2x00dev, 37, 0x07);
- rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
- rt73usb_bbp_write(rt2x00dev, 41, 0x60);
- rt73usb_bbp_write(rt2x00dev, 53, 0x10);
- rt73usb_bbp_write(rt2x00dev, 54, 0x18);
- rt73usb_bbp_write(rt2x00dev, 60, 0x10);
- rt73usb_bbp_write(rt2x00dev, 61, 0x04);
- rt73usb_bbp_write(rt2x00dev, 62, 0x04);
- rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
- rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
- rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
- rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
- rt73usb_bbp_write(rt2x00dev, 99, 0x00);
- rt73usb_bbp_write(rt2x00dev, 102, 0x16);
- rt73usb_bbp_write(rt2x00dev, 107, 0x04);
-
- DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
- for (i = 0; i < EEPROM_BBP_SIZE; i++) {
- rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
-
- if (eeprom != 0xffff && eeprom != 0x0000) {
- reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
- value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
- DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
- reg_id, value);
- rt73usb_bbp_write(rt2x00dev, reg_id, value);
- }
- }
- DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
-
- return 0;
-}
-
-/*
- * Device state switch handlers.
- */
-static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- u32 reg;
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
- state == STATE_RADIO_RX_OFF);
- rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
-}
-
-static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
- /*
- * Initialize all registers.
- */
- if (rt73usb_init_registers(rt2x00dev) ||
- rt73usb_init_bbp(rt2x00dev)) {
- ERROR(rt2x00dev, "Register initialization failed.\n");
- return -EIO;
- }
-
- rt2x00usb_enable_radio(rt2x00dev);
-
- /*
- * Enable LED
- */
- rt73usb_enable_led(rt2x00dev);
-
- return 0;
-}
-
-static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
- /*
- * Disable LED
- */
- rt73usb_disable_led(rt2x00dev);
-
- rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
-
- /*
- * Disable synchronisation.
- */
- rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
-
- rt2x00usb_disable_radio(rt2x00dev);
-}
-
-static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
-{
- u32 reg;
- unsigned int i;
- char put_to_sleep;
- char current_state;
-
- put_to_sleep = (state != STATE_AWAKE);
-
- rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
- rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
- rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
- rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
-
- /*
- * Device is not guaranteed to be in the requested state yet.
- * We must wait until the register indicates that the
- * device has entered the correct state.
- */
- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
- rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
- current_state =
- rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
- if (current_state == !put_to_sleep)
- return 0;
- msleep(10);
- }
-
- NOTICE(rt2x00dev, "Device failed to enter state %d, "
- "current device state %d.\n", !put_to_sleep, current_state);
-
- return -EBUSY;
-}
-
-static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
- enum dev_state state)
-{
- int retval = 0;
-
- switch (state) {
- case STATE_RADIO_ON:
- retval = rt73usb_enable_radio(rt2x00dev);
- break;
- case STATE_RADIO_OFF:
- rt73usb_disable_radio(rt2x00dev);
- break;
- case STATE_RADIO_RX_ON:
- case STATE_RADIO_RX_OFF:
- rt73usb_toggle_rx(rt2x00dev, state);
- break;
- case STATE_DEEP_SLEEP:
- case STATE_SLEEP:
- case STATE_STANDBY:
- case STATE_AWAKE:
- retval = rt73usb_set_state(rt2x00dev, state);
- break;
- default:
- retval = -ENOTSUPP;
- break;
- }
-
- return retval;
-}
-
-/*
- * TX descriptor initialization
- */
-static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
- struct data_desc *txd,
- struct txdata_entry_desc *desc,
- struct ieee80211_hdr *ieee80211hdr,
- unsigned int length,
- struct ieee80211_tx_control *control)
-{
- u32 word;
-
- /*
- * Start writing the descriptor words.
- */
- rt2x00_desc_read(txd, 1, &word);
- rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
- rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
- rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
- rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
- rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
- rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
- rt2x00_desc_write(txd, 1, word);
-
- rt2x00_desc_read(txd, 2, &word);
- rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
- rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
- rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
- rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
- rt2x00_desc_write(txd, 2, word);
-
- rt2x00_desc_read(txd, 5, &word);
- rt2x00_set_field32(&word, TXD_W5_TX_POWER,
- TXPOWER_TO_DEV(control->power_level));
- rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
- rt2x00_desc_write(txd, 5, word);
-
- rt2x00_desc_read(txd, 0, &word);
- rt2x00_set_field32(&word, TXD_W0_BURST,
- test_bit(ENTRY_TXD_BURST, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_VALID, 1);
- rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
- test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_ACK,
- !(control->flags & IEEE80211_TXCTL_NO_ACK));
- rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
- test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_OFDM,
- test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
- rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
- !!(control->flags &
- IEEE80211_TXCTL_LONG_RETRY_LIMIT));
- rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
- rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
- rt2x00_set_field32(&word, TXD_W0_BURST2,
- test_bit(ENTRY_TXD_BURST, &desc->flags));
- rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
- rt2x00_desc_write(txd, 0, word);
-}
-
-static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
- struct sk_buff *skb)
-{
- int length;
-
- /*
- * The length _must_ be a multiple of 4,
- * but it must _not_ be a multiple of the USB packet size.
- */
- length = roundup(skb->len, 4);
- length += (4 * !(length % rt2x00dev->usb_maxpacket));
-
- return length;
-}
-
-/*
- * TX data initialization
- */
-static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
- unsigned int queue)
-{
- u32 reg;
-
- if (queue != IEEE80211_TX_QUEUE_BEACON)
- return;
-
- /*
- * For Wi-Fi faily generated beacons between participating stations.
- * Set TBTT phase adaptive adjustment step to 8us (default 16us)
- */
- rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
- if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
- rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
- rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
- }
-}
-
-/*
- * RX control handlers
- */
-static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
-{
- u16 eeprom;
- u8 offset;
- u8 lna;
-
- lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
- switch (lna) {
- case 3:
- offset = 90;
- break;
- case 2:
- offset = 74;
- break;
- case 1:
- offset = 64;
- break;
- default:
- return 0;
- }
-
- if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
- if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
- if (lna == 3 || lna == 2)
- offset += 10;
- } else {
- if (lna == 3)
- offset += 6;
- else if (lna == 2)
- offset += 8;
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
- offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
- } else {
- if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
- offset += 14;
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
- offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
- }
-
- return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
-}
-
-static void rt73usb_fill_rxdone(struct data_entry *entry,
- struct rxdata_entry_desc *desc)
-{
- struct data_desc *rxd = (struct data_desc *)entry->skb->data;
- u32 word0;
- u32 word1;
-
- rt2x00_desc_read(rxd, 0, &word0);
- rt2x00_desc_read(rxd, 1, &word1);
-
- desc->flags = 0;
- if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
- desc->flags |= RX_FLAG_FAILED_FCS_CRC;
-
- /*
- * Obtain the status about this packet.
- */
- desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
- desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
- desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
- desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
-
- /*
- * Pull the skb to clear the descriptor area.
- */
- skb_pull(entry->skb, entry->ring->desc_size);
-
- return;
-}
-
-/*
- * Device probe functions.
- */
-static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- u16 word;
- u8 *mac;
- s8 value;
-
- rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
-
- /*
- * Start validation of the data that has been read.
- */
- mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
- if (!is_valid_ether_addr(mac)) {
- DECLARE_MAC_BUF(macbuf);
-
- random_ether_addr(mac);
- EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
- rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
- EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
- EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
- rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
- rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
- rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
- rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
- rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
- rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
- rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
- rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
- LED_MODE_DEFAULT);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
- EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
- rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
- EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
- EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
- } else {
- value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
- if (value < -10 || value > 10)
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
- value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
- if (value < -10 || value > 10)
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
- }
-
- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
- if (word == 0xffff) {
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
- EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
- } else {
- value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
- if (value < -10 || value > 10)
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
- value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
- if (value < -10 || value > 10)
- rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
- rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
- }
-
- return 0;
-}
-
-static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
-{
- u32 reg;
- u16 value;
- u16 eeprom;
-
- /*
- * Read EEPROM word for configuration.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-
- /*
- * Identify RF chipset.
- */
- value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
- rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
- rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
-
- if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
- ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
- return -ENODEV;
- }
-
- if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
- !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
- !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
- ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
- return -ENODEV;
- }
-
- /*
- * Identify default antenna configuration.
- */
- rt2x00dev->hw->conf.antenna_sel_tx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
- rt2x00dev->hw->conf.antenna_sel_rx =
- rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
-
- /*
- * Read the Frame type.
- */
- if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
- __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
-
- /*
- * Read frequency offset.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
- rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
-
- /*
- * Read external LNA informations.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
-
- if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
- __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
- __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
- }
-
- /*
- * Store led settings, for correct led behaviour.
- */
- rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
-
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
- rt2x00dev->led_mode);
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_0));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_1));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_2));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_3));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_GPIO_4));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
- rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_RDY_G));
- rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
- rt2x00_get_field16(eeprom,
- EEPROM_LED_POLARITY_RDY_A));
-
- return 0;
-}
-
-/*
- * RF value list for RF2528
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2528[] = {
- { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
- { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
- { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
- { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
- { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
- { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
- { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
- { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
- { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
- { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
- { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
- { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
- { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
- { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
-};
-
-/*
- * RF value list for RF5226
- * Supports: 2.4 GHz & 5.2 GHz
- */
-static const struct rf_channel rf_vals_5226[] = {
- { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
- { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
- { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
- { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
- { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
- { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
- { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
- { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
- { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
- { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
- { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
- { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
- { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
- { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
-
- /* 802.11 UNI / HyperLan 2 */
- { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
- { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
- { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
- { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
- { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
- { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
- { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
- { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
-
- /* 802.11 HyperLan 2 */
- { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
- { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
- { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
- { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
- { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
- { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
- { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
- { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
- { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
- { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
-
- /* 802.11 UNII */
- { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
- { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
- { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
- { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
- { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
- { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
-
- /* MMAC(Japan)J52 ch 34,38,42,46 */
- { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
- { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
- { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
- { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
-};
-
-/*
- * RF value list for RF5225 & RF2527
- * Supports: 2.4 GHz & 5.2 GHz
- */
-static const struct rf_channel rf_vals_5225_2527[] = {
- { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
- { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
- { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
- { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
- { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
- { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
- { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
- { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
- { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
- { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
- { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
- { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
- { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
- { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
-
- /* 802.11 UNI / HyperLan 2 */
- { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
- { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
- { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
- { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
- { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
- { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
- { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
- { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
-
- /* 802.11 HyperLan 2 */
- { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
- { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
- { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
- { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
- { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
- { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
- { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
- { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
- { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
- { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
-
- /* 802.11 UNII */
- { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
- { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
- { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
- { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
- { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
- { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
-
- /* MMAC(Japan)J52 ch 34,38,42,46 */
- { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
- { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
- { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
- { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
-};
-
-
-static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
-{
- struct hw_mode_spec *spec = &rt2x00dev->spec;
- u8 *txpower;
- unsigned int i;
-
- /*
- * Initialize all hw fields.
- */
- rt2x00dev->hw->flags =
- IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
- IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
- rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
- rt2x00dev->hw->max_signal = MAX_SIGNAL;
- rt2x00dev->hw->max_rssi = MAX_RX_SSI;
- rt2x00dev->hw->queues = 5;
-
- SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
- SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
- rt2x00_eeprom_addr(rt2x00dev,
- EEPROM_MAC_ADDR_0));
-
- /*
- * Convert tx_power array in eeprom.
- */
- txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
- for (i = 0; i < 14; i++)
- txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
- /*
- * Initialize hw_mode information.
- */
- spec->num_modes = 2;
- spec->num_rates = 12;
- spec->tx_power_a = NULL;
- spec->tx_power_bg = txpower;
- spec->tx_power_default = DEFAULT_TXPOWER;
-
- if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
- spec->channels = rf_vals_bg_2528;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_5226);
- spec->channels = rf_vals_5226;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
- spec->num_channels = 14;
- spec->channels = rf_vals_5225_2527;
- } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
- spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
- spec->channels = rf_vals_5225_2527;
- }
-
- if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
- rt2x00_rf(&rt2x00dev->chip, RF5226)) {
- spec->num_modes = 3;
-
- txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
- for (i = 0; i < 14; i++)
- txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
- spec->tx_power_a = txpower;
- }
-}
-
-static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
-{
- int retval;
-
- /*
- * Allocate eeprom data.
- */
- retval = rt73usb_validate_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- retval = rt73usb_init_eeprom(rt2x00dev);
- if (retval)
- return retval;
-
- /*
- * Initialize hw specifications.
- */
- rt73usb_probe_hw_mode(rt2x00dev);
-
- /*
- * This device requires firmware
- */
- __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
-
- /*
- * Set the rssi offset.
- */
- rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
-
- return 0;
-}
-
-/*
- * IEEE80211 stack callback functions.
- */
-static void rt73usb_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed_flags,
- unsigned int *total_flags,
- int mc_count,
- struct dev_addr_list *mc_list)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- struct interface *intf = &rt2x00dev->interface;
- u32 reg;
-
- /*
- * Mask off any flags we are going to ignore from
- * the total_flags field.
- */
- *total_flags &=
- FIF_ALLMULTI |
- FIF_FCSFAIL |
- FIF_PLCPFAIL |
- FIF_CONTROL |
- FIF_OTHER_BSS |
- FIF_PROMISC_IN_BSS;
-
- /*
- * Apply some rules to the filters:
- * - Some filters imply different filters to be set.
- * - Some things we can't filter out at all.
- * - Some filters are set based on interface type.
- */
- if (mc_count)
- *total_flags |= FIF_ALLMULTI;
- if (*total_flags & FIF_OTHER_BSS ||
- *total_flags & FIF_PROMISC_IN_BSS)
- *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
- if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
- *total_flags |= FIF_PROMISC_IN_BSS;
-
- /*
- * Check if there is any work left for us.
- */
- if (intf->filter == *total_flags)
- return;
- intf->filter = *total_flags;
-
- /*
- * When in atomic context, reschedule and let rt2x00lib
- * call this function again.
- */
- if (in_atomic()) {
- queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
- return;
- }
-
- /*
- * Start configuration steps.
- * Note that the version error will always be dropped
- * and broadcast frames will always be accepted since
- * there is no filter for it at this time.
- */
- rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
- rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
- !(*total_flags & FIF_FCSFAIL));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
- !(*total_flags & FIF_PLCPFAIL));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
- !(*total_flags & FIF_CONTROL));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
- !(*total_flags & FIF_PROMISC_IN_BSS));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
- rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
- !(*total_flags & FIF_ALLMULTI));
- rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
- rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1);
- rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
-}
-
-static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
- u32 short_retry, u32 long_retry)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u32 reg;
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
- rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
- rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
- rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
-
- return 0;
-}
-
-#if 0
-/*
- * Mac80211 demands get_tsf must be atomic.
- * This is not possible for rt73usb since all register access
- * functions require sleeping. Untill mac80211 no longer needs
- * get_tsf to be atomic, this function should be disabled.
- */
-static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- u64 tsf;
- u32 reg;
-
- rt73usb_register_read(rt2x00dev, TXRX_CSR13, ®);
- tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
- rt73usb_register_read(rt2x00dev, TXRX_CSR12, ®);
- tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
-
- return tsf;
-}
-#else
-#define rt73usb_get_tsf NULL
-#endif
-
-static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
-
- rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
- rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
-}
-
-static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
- struct ieee80211_tx_control *control)
-{
- struct rt2x00_dev *rt2x00dev = hw->priv;
- int timeout;
-
- /*
- * Just in case the ieee80211 doesn't set this,
- * but we need this queue set for the descriptor
- * initialization.
- */
- control->queue = IEEE80211_TX_QUEUE_BEACON;
-
- /*
- * First we create the beacon.
- */
- skb_push(skb, TXD_DESC_SIZE);
- memset(skb->data, 0, TXD_DESC_SIZE);
-
- rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
- (struct ieee80211_hdr *)(skb->data +
- TXD_DESC_SIZE),
- skb->len - TXD_DESC_SIZE, control);
-
- /*
- * Write entire beacon with descriptor to register,
- * and kick the beacon generator.
- */
- timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
- rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
- USB_VENDOR_REQUEST_OUT,
- HW_BEACON_BASE0, 0x0000,
- skb->data, skb->len, timeout);
- rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
-
- return 0;
-}
-
-static const struct ieee80211_ops rt73usb_mac80211_ops = {
- .tx = rt2x00mac_tx,
- .start = rt2x00mac_start,
- .stop = rt2x00mac_stop,
- .add_interface = rt2x00mac_add_interface,
- .remove_interface = rt2x00mac_remove_interface,
- .config = rt2x00mac_config,
- .config_interface = rt2x00mac_config_interface,
- .configure_filter = rt73usb_configure_filter,
- .get_stats = rt2x00mac_get_stats,
- .set_retry_limit = rt73usb_set_retry_limit,
- .erp_ie_changed = rt2x00mac_erp_ie_changed,
- .conf_tx = rt2x00mac_conf_tx,
- .get_tx_stats = rt2x00mac_get_tx_stats,
- .get_tsf = rt73usb_get_tsf,
- .reset_tsf = rt73usb_reset_tsf,
- .beacon_update = rt73usb_beacon_update,
-};
-
-static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
- .probe_hw = rt73usb_probe_hw,
- .get_firmware_name = rt73usb_get_firmware_name,
- .load_firmware = rt73usb_load_firmware,
- .initialize = rt2x00usb_initialize,
- .uninitialize = rt2x00usb_uninitialize,
- .set_device_state = rt73usb_set_device_state,
- .link_stats = rt73usb_link_stats,
- .reset_tuner = rt73usb_reset_tuner,
- .link_tuner = rt73usb_link_tuner,
- .write_tx_desc = rt73usb_write_tx_desc,
- .write_tx_data = rt2x00usb_write_tx_data,
- .get_tx_data_len = rt73usb_get_tx_data_len,
- .kick_tx_queue = rt73usb_kick_tx_queue,
- .fill_rxdone = rt73usb_fill_rxdone,
- .config_mac_addr = rt73usb_config_mac_addr,
- .config_bssid = rt73usb_config_bssid,
- .config_type = rt73usb_config_type,
- .config_preamble = rt73usb_config_preamble,
- .config = rt73usb_config,
-};
-
-static const struct rt2x00_ops rt73usb_ops = {
- .name = DRV_NAME,
- .rxd_size = RXD_DESC_SIZE,
- .txd_size = TXD_DESC_SIZE,
- .eeprom_size = EEPROM_SIZE,
- .rf_size = RF_SIZE,
- .lib = &rt73usb_rt2x00_ops,
- .hw = &rt73usb_mac80211_ops,
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
- .debugfs = &rt73usb_rt2x00debug,
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-};
-
-/*
- * rt73usb module information.
- */
-static struct usb_device_id rt73usb_device_table[] = {
- /* AboCom */
- { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Askey */
- { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
- /* ASUS */
- { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Belkin */
- { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Billionton */
- { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Buffalo */
- { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
- /* CNet */
- { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Conceptronic */
- { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
- /* D-Link */
- { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Gemtek */
- { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Gigabyte */
- { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Huawei-3Com */
- { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Hercules */
- { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Linksys */
- { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
- /* MSI */
- { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Ralink */
- { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Qcom */
- { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Senao */
- { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Sitecom */
- { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Surecom */
- { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
- /* Planex */
- { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
- { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
- { 0, }
-};
-
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
-MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
-MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
-MODULE_FIRMWARE(FIRMWARE_RT2571);
-MODULE_LICENSE("GPL");
-
-static struct usb_driver rt73usb_driver = {
- .name = DRV_NAME,
- .id_table = rt73usb_device_table,
- .probe = rt2x00usb_probe,
- .disconnect = rt2x00usb_disconnect,
- .suspend = rt2x00usb_suspend,
- .resume = rt2x00usb_resume,
-};
-
-static int __init rt73usb_init(void)
-{
- return usb_register(&rt73usb_driver);
-}
-
-static void __exit rt73usb_exit(void)
-{
- usb_deregister(&rt73usb_driver);
-}
-
-module_init(rt73usb_init);
-module_exit(rt73usb_exit);
+++ /dev/null
-/*
- Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
- <http://rt2x00.serialmonkey.com>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the
- Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
- Module: rt73usb
- Abstract: Data structures and registers for the rt73usb module.
- Supported chipsets: rt2571W & rt2671.
- */
-
-#ifndef RT73USB_H
-#define RT73USB_H
-
-/*
- * RF chip defines.
- */
-#define RF5226 0x0001
-#define RF2528 0x0002
-#define RF5225 0x0003
-#define RF2527 0x0004
-
-/*
- * Signal information.
- * Defaul offset is required for RSSI <-> dBm conversion.
- */
-#define MAX_SIGNAL 100
-#define MAX_RX_SSI -1
-#define DEFAULT_RSSI_OFFSET 120
-
-/*
- * Register layout information.
- */
-#define CSR_REG_BASE 0x3000
-#define CSR_REG_SIZE 0x04b0
-#define EEPROM_BASE 0x0000
-#define EEPROM_SIZE 0x0100
-#define BBP_SIZE 0x0080
-#define RF_SIZE 0x0014
-
-/*
- * USB registers.
- */
-
-/*
- * MCU_LEDCS: LED control for MCU Mailbox.
- */
-#define MCU_LEDCS_LED_MODE FIELD16(0x001f)
-#define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
-#define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
-#define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
-#define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
-#define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
-#define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
-#define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
-#define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
-#define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
-#define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
-#define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
-
-/*
- * 8051 firmware image.
- */
-#define FIRMWARE_RT2571 "rt73.bin"
-#define FIRMWARE_IMAGE_BASE 0x0800
-
-/*
- * Security key table memory.
- * 16 entries 32-byte for shared key table
- * 64 entries 32-byte for pairwise key table
- * 64 entries 8-byte for pairwise ta key table
- */
-#define SHARED_KEY_TABLE_BASE 0x1000
-#define PAIRWISE_KEY_TABLE_BASE 0x1200
-#define PAIRWISE_TA_TABLE_BASE 0x1a00
-
-struct hw_key_entry {
- u8 key[16];
- u8 tx_mic[8];
- u8 rx_mic[8];
-} __attribute__ ((packed));
-
-struct hw_pairwise_ta_entry {
- u8 address[6];
- u8 reserved[2];
-} __attribute__ ((packed));
-
-/*
- * Since NULL frame won't be that long (256 byte),
- * We steal 16 tail bytes to save debugging settings.
- */
-#define HW_DEBUG_SETTING_BASE 0x2bf0
-
-/*
- * On-chip BEACON frame space.
- */
-#define HW_BEACON_BASE0 0x2400
-#define HW_BEACON_BASE1 0x2500
-#define HW_BEACON_BASE2 0x2600
-#define HW_BEACON_BASE3 0x2700
-
-/*
- * MAC Control/Status Registers(CSR).
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * MAC_CSR0: ASIC revision number.
- */
-#define MAC_CSR0 0x3000
-
-/*
- * MAC_CSR1: System control register.
- * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
- * BBP_RESET: Hardware reset BBP.
- * HOST_READY: Host is ready after initialization, 1: ready.
- */
-#define MAC_CSR1 0x3004
-#define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
-#define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
-#define MAC_CSR1_HOST_READY FIELD32(0x00000004)
-
-/*
- * MAC_CSR2: STA MAC register 0.
- */
-#define MAC_CSR2 0x3008
-#define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
-#define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
-#define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
-#define MAC_CSR2_BYTE3 FIELD32(0xff000000)
-
-/*
- * MAC_CSR3: STA MAC register 1.
- */
-#define MAC_CSR3 0x300c
-#define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
-#define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
-#define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
-
-/*
- * MAC_CSR4: BSSID register 0.
- */
-#define MAC_CSR4 0x3010
-#define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
-#define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
-#define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
-#define MAC_CSR4_BYTE3 FIELD32(0xff000000)
-
-/*
- * MAC_CSR5: BSSID register 1.
- * BSS_ID_MASK: 3: one BSSID, 0: 4 BSSID, 2 or 1: 2 BSSID.
- */
-#define MAC_CSR5 0x3014
-#define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
-#define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
-#define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
-
-/*
- * MAC_CSR6: Maximum frame length register.
- */
-#define MAC_CSR6 0x3018
-#define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
-
-/*
- * MAC_CSR7: Reserved
- */
-#define MAC_CSR7 0x301c
-
-/*
- * MAC_CSR8: SIFS/EIFS register.
- * All units are in US.
- */
-#define MAC_CSR8 0x3020
-#define MAC_CSR8_SIFS FIELD32(0x000000ff)
-#define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
-#define MAC_CSR8_EIFS FIELD32(0xffff0000)
-
-/*
- * MAC_CSR9: Back-Off control register.
- * SLOT_TIME: Slot time, default is 20us for 802.11BG.
- * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
- * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
- * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
- */
-#define MAC_CSR9 0x3024
-#define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
-#define MAC_CSR9_CWMIN FIELD32(0x00000f00)
-#define MAC_CSR9_CWMAX FIELD32(0x0000f000)
-#define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
-
-/*
- * MAC_CSR10: Power state configuration.
- */
-#define MAC_CSR10 0x3028
-
-/*
- * MAC_CSR11: Power saving transition time register.
- * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
- * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
- * WAKEUP_LATENCY: In unit of TU.
- */
-#define MAC_CSR11 0x302c
-#define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
-#define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
-#define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
-#define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
-
-/*
- * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
- * CURRENT_STATE: 0:sleep, 1:awake.
- * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
- * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
- */
-#define MAC_CSR12 0x3030
-#define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
-#define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
-#define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
-#define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
-
-/*
- * MAC_CSR13: GPIO.
- */
-#define MAC_CSR13 0x3034
-
-/*
- * MAC_CSR14: LED control register.
- * ON_PERIOD: On period, default 70ms.
- * OFF_PERIOD: Off period, default 30ms.
- * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
- * SW_LED: s/w LED, 1: ON, 0: OFF.
- * HW_LED_POLARITY: 0: active low, 1: active high.
- */
-#define MAC_CSR14 0x3038
-#define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
-#define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
-#define MAC_CSR14_HW_LED FIELD32(0x00010000)
-#define MAC_CSR14_SW_LED FIELD32(0x00020000)
-#define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
-#define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
-
-/*
- * MAC_CSR15: NAV control.
- */
-#define MAC_CSR15 0x303c
-
-/*
- * TXRX control registers.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * TXRX_CSR0: TX/RX configuration register.
- * TSF_OFFSET: Default is 24.
- * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
- * DISABLE_RX: Disable Rx engine.
- * DROP_CRC: Drop CRC error.
- * DROP_PHYSICAL: Drop physical error.
- * DROP_CONTROL: Drop control frame.
- * DROP_NOT_TO_ME: Drop not to me unicast frame.
- * DROP_TO_DS: Drop fram ToDs bit is true.
- * DROP_VERSION_ERROR: Drop version error frame.
- * DROP_MULTICAST: Drop multicast frames.
- * DROP_BORADCAST: Drop broadcast frames.
- * ROP_ACK_CTS: Drop received ACK and CTS.
- */
-#define TXRX_CSR0 0x3040
-#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
-#define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
-#define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
-#define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
-#define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
-#define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
-#define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
-#define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
-#define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
-#define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
-#define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
-#define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
-#define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
-#define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
-
-/*
- * TXRX_CSR1
- */
-#define TXRX_CSR1 0x3044
-#define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
-#define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
-#define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
-#define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
-#define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
-#define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
-#define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
-#define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
-
-/*
- * TXRX_CSR2
- */
-#define TXRX_CSR2 0x3048
-#define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
-#define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
-#define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
-#define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
-#define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
-#define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
-#define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
-#define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
-
-/*
- * TXRX_CSR3
- */
-#define TXRX_CSR3 0x304c
-#define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
-#define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
-#define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
-#define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
-#define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
-#define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
-#define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
-#define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
-
-/*
- * TXRX_CSR4: Auto-Responder/Tx-retry register.
- * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
- * OFDM_TX_RATE_DOWN: 1:enable.
- * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
- * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
- */
-#define TXRX_CSR4 0x3050
-#define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
-#define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
-#define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
-#define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
-#define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
-#define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
-#define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
-#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
-#define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
-#define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
-
-/*
- * TXRX_CSR5
- */
-#define TXRX_CSR5 0x3054
-
-/*
- * TXRX_CSR6: ACK/CTS payload consumed time
- */
-#define TXRX_CSR6 0x3058
-
-/*
- * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
- */
-#define TXRX_CSR7 0x305c
-#define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
-#define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
-#define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
-#define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
-
-/*
- * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
- */
-#define TXRX_CSR8 0x3060
-#define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
-#define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
-#define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
-#define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
-
-/*
- * TXRX_CSR9: Synchronization control register.
- * BEACON_INTERVAL: In unit of 1/16 TU.
- * TSF_TICKING: Enable TSF auto counting.
- * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
- * BEACON_GEN: Enable beacon generator.
- */
-#define TXRX_CSR9 0x3064
-#define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
-#define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
-#define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
-#define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
-#define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
-#define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
-
-/*
- * TXRX_CSR10: BEACON alignment.
- */
-#define TXRX_CSR10 0x3068
-
-/*
- * TXRX_CSR11: AES mask.
- */
-#define TXRX_CSR11 0x306c
-
-/*
- * TXRX_CSR12: TSF low 32.
- */
-#define TXRX_CSR12 0x3070
-#define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
-
-/*
- * TXRX_CSR13: TSF high 32.
- */
-#define TXRX_CSR13 0x3074
-#define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
-
-/*
- * TXRX_CSR14: TBTT timer.
- */
-#define TXRX_CSR14 0x3078
-
-/*
- * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
- */
-#define TXRX_CSR15 0x307c
-
-/*
- * PHY control registers.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * PHY_CSR0: RF/PS control.
- */
-#define PHY_CSR0 0x3080
-#define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
-#define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
-
-/*
- * PHY_CSR1
- */
-#define PHY_CSR1 0x3084
-#define PHY_CSR1_RF_RPI FIELD32(0x00010000)
-
-/*
- * PHY_CSR2: Pre-TX BBP control.
- */
-#define PHY_CSR2 0x3088
-
-/*
- * PHY_CSR3: BBP serial control register.
- * VALUE: Register value to program into BBP.
- * REG_NUM: Selected BBP register.
- * READ_CONTROL: 0: Write BBP, 1: Read BBP.
- * BUSY: 1: ASIC is busy execute BBP programming.
- */
-#define PHY_CSR3 0x308c
-#define PHY_CSR3_VALUE FIELD32(0x000000ff)
-#define PHY_CSR3_REGNUM FIELD32(0x00007f00)
-#define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
-#define PHY_CSR3_BUSY FIELD32(0x00010000)
-
-/*
- * PHY_CSR4: RF serial control register
- * VALUE: Register value (include register id) serial out to RF/IF chip.
- * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
- * IF_SELECT: 1: select IF to program, 0: select RF to program.
- * PLL_LD: RF PLL_LD status.
- * BUSY: 1: ASIC is busy execute RF programming.
- */
-#define PHY_CSR4 0x3090
-#define PHY_CSR4_VALUE FIELD32(0x00ffffff)
-#define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
-#define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
-#define PHY_CSR4_PLL_LD FIELD32(0x40000000)
-#define PHY_CSR4_BUSY FIELD32(0x80000000)
-
-/*
- * PHY_CSR5: RX to TX signal switch timing control.
- */
-#define PHY_CSR5 0x3094
-#define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
-
-/*
- * PHY_CSR6: TX to RX signal timing control.
- */
-#define PHY_CSR6 0x3098
-#define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
-
-/*
- * PHY_CSR7: TX DAC switching timing control.
- */
-#define PHY_CSR7 0x309c
-
-/*
- * Security control register.
- */
-
-/*
- * SEC_CSR0: Shared key table control.
- */
-#define SEC_CSR0 0x30a0
-#define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
-#define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
-#define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
-#define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
-#define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
-#define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
-#define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
-#define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
-#define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
-#define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
-#define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
-#define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
-#define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
-#define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
-#define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
-#define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
-
-/*
- * SEC_CSR1: Shared key table security mode register.
- */
-#define SEC_CSR1 0x30a4
-#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
-#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
-#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
-#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
-#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
-#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
-#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
-#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
-
-/*
- * Pairwise key table valid bitmap registers.
- * SEC_CSR2: pairwise key table valid bitmap 0.
- * SEC_CSR3: pairwise key table valid bitmap 1.
- */
-#define SEC_CSR2 0x30a8
-#define SEC_CSR3 0x30ac
-
-/*
- * SEC_CSR4: Pairwise key table lookup control.
- */
-#define SEC_CSR4 0x30b0
-
-/*
- * SEC_CSR5: shared key table security mode register.
- */
-#define SEC_CSR5 0x30b4
-#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
-#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
-#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
-#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
-#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
-#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
-#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
-#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
-
-/*
- * STA control registers.
- */
-
-/*
- * STA_CSR0: RX PLCP error count & RX FCS error count.
- */
-#define STA_CSR0 0x30c0
-#define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
-#define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
-
-/*
- * STA_CSR1: RX False CCA count & RX LONG frame count.
- */
-#define STA_CSR1 0x30c4
-#define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
-#define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
-
-/*
- * STA_CSR2: TX Beacon count and RX FIFO overflow count.
- */
-#define STA_CSR2 0x30c8
-#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
-#define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
-
-/*
- * STA_CSR3: TX Beacon count.
- */
-#define STA_CSR3 0x30cc
-#define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
-
-/*
- * STA_CSR4: TX Retry count.
- */
-#define STA_CSR4 0x30d0
-#define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
-#define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
-
-/*
- * STA_CSR5: TX Retry count.
- */
-#define STA_CSR5 0x30d4
-#define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
-#define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
-
-/*
- * QOS control registers.
- */
-
-/*
- * QOS_CSR1: TXOP holder MAC address register.
- */
-#define QOS_CSR1 0x30e4
-#define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
-#define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
-
-/*
- * QOS_CSR2: TXOP holder timeout register.
- */
-#define QOS_CSR2 0x30e8
-
-/*
- * RX QOS-CFPOLL MAC address register.
- * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
- * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
- */
-#define QOS_CSR3 0x30ec
-#define QOS_CSR4 0x30f0
-
-/*
- * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
- */
-#define QOS_CSR5 0x30f4
-
-/*
- * WMM Scheduler Register
- */
-
-/*
- * AIFSN_CSR: AIFSN for each EDCA AC.
- * AIFSN0: For AC_BK.
- * AIFSN1: For AC_BE.
- * AIFSN2: For AC_VI.
- * AIFSN3: For AC_VO.
- */
-#define AIFSN_CSR 0x0400
-#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
-#define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
-#define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
-#define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
-
-/*
- * CWMIN_CSR: CWmin for each EDCA AC.
- * CWMIN0: For AC_BK.
- * CWMIN1: For AC_BE.
- * CWMIN2: For AC_VI.
- * CWMIN3: For AC_VO.
- */
-#define CWMIN_CSR 0x0404
-#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
-#define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
-#define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
-#define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
-
-/*
- * CWMAX_CSR: CWmax for each EDCA AC.
- * CWMAX0: For AC_BK.
- * CWMAX1: For AC_BE.
- * CWMAX2: For AC_VI.
- * CWMAX3: For AC_VO.
- */
-#define CWMAX_CSR 0x0408
-#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
-#define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
-#define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
-#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
-
-/*
- * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
- * AC0_TX_OP: For AC_BK, in unit of 32us.
- * AC1_TX_OP: For AC_BE, in unit of 32us.
- */
-#define AC_TXOP_CSR0 0x040c
-#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
-#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
-
-/*
- * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
- * AC2_TX_OP: For AC_VI, in unit of 32us.
- * AC3_TX_OP: For AC_VO, in unit of 32us.
- */
-#define AC_TXOP_CSR1 0x0410
-#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
-#define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
-
-/*
- * BBP registers.
- * The wordsize of the BBP is 8 bits.
- */
-
-/*
- * R2
- */
-#define BBP_R2_BG_MODE FIELD8(0x20)
-
-/*
- * R3
- */
-#define BBP_R3_SMART_MODE FIELD8(0x01)
-
-/*
- * R4: RX antenna control
- * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
- */
-#define BBP_R4_RX_ANTENNA FIELD8(0x03)
-#define BBP_R4_RX_FRAME_END FIELD8(0x20)
-
-/*
- * R77
- */
-#define BBP_R77_PAIR FIELD8(0x03)
-
-/*
- * RF registers
- */
-
-/*
- * RF 3
- */
-#define RF3_TXPOWER FIELD32(0x00003e00)
-
-/*
- * RF 4
- */
-#define RF4_FREQ_OFFSET FIELD32(0x0003f000)
-
-/*
- * EEPROM content.
- * The wordsize of the EEPROM is 16 bits.
- */
-
-/*
- * HW MAC address.
- */
-#define EEPROM_MAC_ADDR_0 0x0002
-#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR1 0x0003
-#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
-#define EEPROM_MAC_ADDR_2 0x0004
-#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
-
-/*
- * EEPROM antenna.
- * ANTENNA_NUM: Number of antenna's.
- * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
- * DYN_TXAGC: Dynamic TX AGC control.
- * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
- * RF_TYPE: Rf_type of this adapter.
- */
-#define EEPROM_ANTENNA 0x0010
-#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
-#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
-#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
-#define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
-#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
-#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
-#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
-
-/*
- * EEPROM NIC config.
- * EXTERNAL_LNA: External LNA.
- */
-#define EEPROM_NIC 0x0011
-#define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
-
-/*
- * EEPROM geography.
- * GEO_A: Default geographical setting for 5GHz band
- * GEO: Default geographical setting.
- */
-#define EEPROM_GEOGRAPHY 0x0012
-#define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
-#define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
-
-/*
- * EEPROM BBP.
- */
-#define EEPROM_BBP_START 0x0013
-#define EEPROM_BBP_SIZE 16
-#define EEPROM_BBP_VALUE FIELD16(0x00ff)
-#define EEPROM_BBP_REG_ID FIELD16(0xff00)
-
-/*
- * EEPROM TXPOWER 802.11G
- */
-#define EEPROM_TXPOWER_G_START 0x0023
-#define EEPROM_TXPOWER_G_SIZE 7
-#define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
-#define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
-
-/*
- * EEPROM Frequency
- */
-#define EEPROM_FREQ 0x002f
-#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
-#define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
-#define EEPROM_FREQ_SEQ FIELD16(0x0300)
-
-/*
- * EEPROM LED.
- * POLARITY_RDY_G: Polarity RDY_G setting.
- * POLARITY_RDY_A: Polarity RDY_A setting.
- * POLARITY_ACT: Polarity ACT setting.
- * POLARITY_GPIO_0: Polarity GPIO0 setting.
- * POLARITY_GPIO_1: Polarity GPIO1 setting.
- * POLARITY_GPIO_2: Polarity GPIO2 setting.
- * POLARITY_GPIO_3: Polarity GPIO3 setting.
- * POLARITY_GPIO_4: Polarity GPIO4 setting.
- * LED_MODE: Led mode.
- */
-#define EEPROM_LED 0x0030
-#define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
-#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
-#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
-#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
-#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
-#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
-#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
-#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
-#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
-
-/*
- * EEPROM TXPOWER 802.11A
- */
-#define EEPROM_TXPOWER_A_START 0x0031
-#define EEPROM_TXPOWER_A_SIZE 12
-#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
-#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
-
-/*
- * EEPROM RSSI offset 802.11BG
- */
-#define EEPROM_RSSI_OFFSET_BG 0x004d
-#define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
-#define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
-
-/*
- * EEPROM RSSI offset 802.11A
- */
-#define EEPROM_RSSI_OFFSET_A 0x004e
-#define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
-#define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
-
-/*
- * DMA descriptor defines.
- */
-#define TXD_DESC_SIZE ( 6 * sizeof(struct data_desc) )
-#define RXD_DESC_SIZE ( 6 * sizeof(struct data_desc) )
-
-/*
- * TX descriptor format for TX, PRIO and Beacon Ring.
- */
-
-/*
- * Word0
- * BURST: Next frame belongs to same "burst" event.
- * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
- * KEY_TABLE: Use per-client pairwise KEY table.
- * KEY_INDEX:
- * Key index (0~31) to the pairwise KEY table.
- * 0~3 to shared KEY table 0 (BSS0).
- * 4~7 to shared KEY table 1 (BSS1).
- * 8~11 to shared KEY table 2 (BSS2).
- * 12~15 to shared KEY table 3 (BSS3).
- * BURST2: For backward compatibility, set to same value as BURST.
- */
-#define TXD_W0_BURST FIELD32(0x00000001)
-#define TXD_W0_VALID FIELD32(0x00000002)
-#define TXD_W0_MORE_FRAG FIELD32(0x00000004)
-#define TXD_W0_ACK FIELD32(0x00000008)
-#define TXD_W0_TIMESTAMP FIELD32(0x00000010)
-#define TXD_W0_OFDM FIELD32(0x00000020)
-#define TXD_W0_IFS FIELD32(0x00000040)
-#define TXD_W0_RETRY_MODE FIELD32(0x00000080)
-#define TXD_W0_TKIP_MIC FIELD32(0x00000100)
-#define TXD_W0_KEY_TABLE FIELD32(0x00000200)
-#define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
-#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
-#define TXD_W0_BURST2 FIELD32(0x10000000)
-#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
-
-/*
- * Word1
- * HOST_Q_ID: EDCA/HCCA queue ID.
- * HW_SEQUENCE: MAC overwrites the frame sequence number.
- * BUFFER_COUNT: Number of buffers in this TXD.
- */
-#define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
-#define TXD_W1_AIFSN FIELD32(0x000000f0)
-#define TXD_W1_CWMIN FIELD32(0x00000f00)
-#define TXD_W1_CWMAX FIELD32(0x0000f000)
-#define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
-#define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
-#define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
-
-/*
- * Word2: PLCP information
- */
-#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
-#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
-#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
-#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
-
-/*
- * Word3
- */
-#define TXD_W3_IV FIELD32(0xffffffff)
-
-/*
- * Word4
- */
-#define TXD_W4_EIV FIELD32(0xffffffff)
-
-/*
- * Word5
- * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
- * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
- * WAITING_DMA_DONE_INT: TXD been filled with data
- * and waiting for TxDoneISR housekeeping.
- */
-#define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
-#define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
-#define TXD_W5_TX_POWER FIELD32(0x00ff0000)
-#define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
-
-/*
- * RX descriptor format for RX Ring.
- */
-
-/*
- * Word0
- * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
- * KEY_INDEX: Decryption key actually used.
- */
-#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
-#define RXD_W0_DROP FIELD32(0x00000002)
-#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
-#define RXD_W0_MULTICAST FIELD32(0x00000008)
-#define RXD_W0_BROADCAST FIELD32(0x00000010)
-#define RXD_W0_MY_BSS FIELD32(0x00000020)
-#define RXD_W0_CRC_ERROR FIELD32(0x00000040)
-#define RXD_W0_OFDM FIELD32(0x00000080)
-#define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
-#define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
-#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
-#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
-
-/*
- * WORD1
- * SIGNAL: RX raw data rate reported by BBP.
- * RSSI: RSSI reported by BBP.
- */
-#define RXD_W1_SIGNAL FIELD32(0x000000ff)
-#define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
-#define RXD_W1_RSSI_LNA FIELD32(0x00006000)
-#define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
-
-/*
- * Word2
- * IV: Received IV of originally encrypted.
- */
-#define RXD_W2_IV FIELD32(0xffffffff)
-
-/*
- * Word3
- * EIV: Received EIV of originally encrypted.
- */
-#define RXD_W3_EIV FIELD32(0xffffffff)
-
-/*
- * Word4
- */
-#define RXD_W4_RESERVED FIELD32(0xffffffff)
-
-/*
- * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
- * and passed to the HOST driver.
- * The following fields are for DMA block and HOST usage only.
- * Can't be touched by ASIC MAC block.
- */
-
-/*
- * Word5
- */
-#define RXD_W5_RESERVED FIELD32(0xffffffff)
-
-/*
- * Macro's for converting txpower from EEPROM to dscape value
- * and from dscape value to register value.
- */
-#define MIN_TXPOWER 0
-#define MAX_TXPOWER 31
-#define DEFAULT_TXPOWER 24
-
-#define TXPOWER_FROM_DEV(__txpower) \
-({ \
- ((__txpower) > MAX_TXPOWER) ? \
- DEFAULT_TXPOWER : (__txpower); \
-})
-
-#define TXPOWER_TO_DEV(__txpower) \
-({ \
- ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
- (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
- (__txpower)); \
-})
-
-#endif /* RT73USB_H */
projects / openwrt / staging / jogo.git / commitdiff