Enable and setup multi-cpu for qca8k switch for ipq806x based devices.
Rework each DTS to enable the secondary CPU port on QCA8K switch and
apply the required values originally set by the OEM in the old swconfig
node.
In original firmware the first CPU port was always assigned to the WAN
port and the secondary CPU port was assigned to the rest of the LAN
port. Follow this original implementation using an init.d script.
To setup the CPU port ip tools is required. Add additional default
package ip-tiny to correctly setup the CPU port.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \
kmod-phy-qcom-ipq806x-usb kmod-usb3 kmod-usb-dwc3-qcom \
kmod-ath10k-ct wpad-basic-mbedtls \
- uboot-envtools
+ uboot-envtools ip-tiny
$(eval $(call BuildTarget))
--- /dev/null
+#!/bin/sh /etc/rc.common
+
+START=15
+
+set_qca8k_port() {
+ local port=$1
+ local master=$2
+
+ ip link set $port type dsa conduit $master
+}
+
+boot() {
+ # Restore original implementation where the eth1 (port 6) was used
+ # for the lan port and the eth0 (port 0) was used for the wan port
+ case $(board_name) in
+ askey,rt4230w-rev6 |\
+ asrock,g10 |\
+ buffalo,wxr-2533dhp |\
+ compex,wpq864 |\
+ nec,wg2600hp |\
+ nec,wg2600hp3 |\
+ netgear,d7800 |\
+ netgear,r7500 |\
+ netgear,r7500v2 |\
+ netgear,r7800 |\
+ netgear,xr450 |\
+ netgear,xr500 |\
+ nokia,ac400i |\
+ tplink,ad7200 |\
+ tplink,c2600 |\
+ tplink,vr2600v |\
+ zyxel,nbg6817)
+ set_qca8k_port lan1 eth1
+ set_qca8k_port lan2 eth1
+ set_qca8k_port lan3 eth1
+ set_qca8k_port lan4 eth1
+ set_qca8k_port wan eth0
+ ;;
+ asus,onhub |\
+ tplink,onhub)
+ set_qca8k_port lan1 eth1
+ set_qca8k_port wan eth0
+ ;;
+ esac
+}
phy-handle = <&phy_port5>;
};
- /*
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
+ qca,sgmii-rxclk-falling-edge;
fixed-link {
speed = <1000>;
full-duplex;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port2>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
+ qca,sgmii-rxclk-falling-edge;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port5>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "rgmii";
+ ethernet = <&gmac1>;
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
phy-handle = <&phy_port4>;
};
- /*
port@6 {
- reg = <0>;
+ reg = <6>;
label = "cpu";
ethernet = <&gmac1>;
- phy-mode = "rgmii";
+ phy-mode = "sgmii";
+ qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
- pause;
- asym-pause;
};
};
- */
};
mdio {
projects / openwrt / staging / dangole.git / commitdiff