cxgb4: specify IQTYPE in fw_iq_cmd
authorArjun Vynipadath <arjun@chelsio.com>
Mon, 9 Jul 2018 11:22:03 +0000 (16:52 +0530)
committerDavid S. Miller <davem@davemloft.net>
Thu, 12 Jul 2018 05:52:10 +0000 (22:52 -0700)
congestion argument passed to t4_sge_alloc_rxq() is used
to differentiate between nic/ofld queues.

Signed-off-by: Arjun Vynipadath <arjun@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/chelsio/cxgb4/sge.c
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

index ebb46c472d523f27b5ffbe56f5d97c1eda85e62e..6807bc3a44fb7fad1fd6c229bafef6b5a8c063a1 100644 (file)
@@ -3412,7 +3412,9 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
        c.iqsize = htons(iq->size);
        c.iqaddr = cpu_to_be64(iq->phys_addr);
        if (cong >= 0)
-               c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F);
+               c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F |
+                               FW_IQ_CMD_IQTYPE_V(cong ? FW_IQ_IQTYPE_NIC
+                                                       :  FW_IQ_IQTYPE_OFLD));
 
        if (fl) {
                enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
index f1967cf6d43c4b614aba152b7e6e53d0e8b5e644..5dc6c4154af8a6e5961290f84e31e9a10d551598 100644 (file)
@@ -1472,6 +1472,12 @@ enum fw_iq_type {
        FW_IQ_TYPE_NO_FL_INT_CAP
 };
 
+enum fw_iq_iqtype {
+       FW_IQ_IQTYPE_OTHER,
+       FW_IQ_IQTYPE_NIC,
+       FW_IQ_IQTYPE_OFLD,
+};
+
 struct fw_iq_cmd {
        __be32 op_to_vfn;
        __be32 alloc_to_len16;
@@ -1586,6 +1592,12 @@ struct fw_iq_cmd {
 #define FW_IQ_CMD_IQFLINTISCSIC_S      26
 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)   ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
 
+#define FW_IQ_CMD_IQTYPE_S             24
+#define FW_IQ_CMD_IQTYPE_M             0x3
+#define FW_IQ_CMD_IQTYPE_V(x)          ((x) << FW_IQ_CMD_IQTYPE_S)
+#define FW_IQ_CMD_IQTYPE_G(x)          \
+       (((x) >> FW_IQ_CMD_IQTYPE_S) & FW_IQ_CMD_IQTYPE_M)
+
 #define FW_IQ_CMD_FL0CNGCHMAP_S                20
 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)     ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)