drm/amdgpu: enable DF clock gating for rn

Enable DF clock gating during DF IP early init.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 50242384a163825377ce55b66aaedf9c5555b90d..c367b5f1b395172b97a58f00cd3d0fd4fa7de942 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1172,7 +1172,8 @@ static int soc15_common_early_init(void *handle)
                                 AMD_CG_SUPPORT_VCN_MGCG |
                                 AMD_CG_SUPPORT_IH_CG |
                                 AMD_CG_SUPPORT_ATHUB_LS |
-                                AMD_CG_SUPPORT_ATHUB_MGCG;
+                                AMD_CG_SUPPORT_ATHUB_MGCG |
+                                AMD_CG_SUPPORT_DF_MGCG;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x91;