net: fsl: fec: handle 10Mbps speed in RMII mode
authorEric Benard <eric@eukrea.com>
Thu, 12 Jan 2012 06:10:28 +0000 (06:10 +0000)
committerDavid S. Miller <davem@davemloft.net>
Fri, 13 Jan 2012 04:05:28 +0000 (20:05 -0800)
when the link is 10 Mbps and the mode is RMII, it's necessary
to set FRCONT to 1 in MIIGSK_CFGR to divide the RMII source
clock by 10 in order to support 10 Mbps operations.

Signed-off-by: Eric BĂ©nard <eric@eukrea.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/freescale/fec.c
drivers/net/ethernet/freescale/fec.h

index 236cc892ec3efaea0a7deba2161cf1a8d70f71e6..7b25e9cf13f6ff5a6c141cd6c6bd478fe5e5c6fb 100644 (file)
@@ -476,6 +476,7 @@ fec_restart(struct net_device *ndev, int duplex)
        } else {
 #ifdef FEC_MIIGSK_ENR
                if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
+                       u32 cfgr;
                        /* disable the gasket and wait */
                        writel(0, fep->hwp + FEC_MIIGSK_ENR);
                        while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
@@ -486,9 +487,11 @@ fec_restart(struct net_device *ndev, int duplex)
                         *   RMII, 50 MHz, no loopback, no echo
                         *   MII, 25 MHz, no loopback, no echo
                         */
-                       writel((fep->phy_interface == PHY_INTERFACE_MODE_RMII) ?
-                                       1 : 0, fep->hwp + FEC_MIIGSK_CFGR);
-
+                       cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
+                               ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
+                       if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
+                               cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
+                       writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
 
                        /* re-enable the gasket */
                        writel(2, fep->hwp + FEC_MIIGSK_ENR);
index 8b2c6d797e6ddee6fe6dd165a22ba2ea9a8e8567..8408c627b1953a230c1f25d24b05217b0718d19f 100644 (file)
 #define FEC_MIIGSK_CFGR                0x300 /* MIIGSK Configuration reg */
 #define FEC_MIIGSK_ENR         0x308 /* MIIGSK Enable reg */
 
+#define BM_MIIGSK_CFGR_MII             0x00
+#define BM_MIIGSK_CFGR_RMII            0x01
+#define BM_MIIGSK_CFGR_FRCONT_10M      0x40
+
 #else
 
 #define FEC_ECNTRL             0x000 /* Ethernet control reg */