ARM: uniphier: refactor MEMCONF init code
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Sun, 15 Jan 2017 05:59:04 +0000 (14:59 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Tue, 17 Jan 2017 00:00:40 +0000 (09:00 +0900)
Currently, memconf-sld3.c and memconf-pxs2.c duplicate the code.

There are 3 patterns in terms of MEMCONF init:
  - DRAM 2 channels: LD4, sLD8, Pro4, Pro5, LD11
  - DRAM 3 channels: sLD3
  - DRAM 3 channels (Ch2 is disable by MEMCONF[21]): Pxs2, LD20

All of them can be moved into a single file by a little more
refactoring.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
15 files changed:
arch/arm/mach-uniphier/Makefile
arch/arm/mach-uniphier/init.h
arch/arm/mach-uniphier/init/init-ld11.c
arch/arm/mach-uniphier/init/init-ld20.c
arch/arm/mach-uniphier/init/init-ld4.c
arch/arm/mach-uniphier/init/init-pro4.c
arch/arm/mach-uniphier/init/init-pro5.c
arch/arm/mach-uniphier/init/init-pxs2.c
arch/arm/mach-uniphier/init/init-sld3.c
arch/arm/mach-uniphier/init/init-sld8.c
arch/arm/mach-uniphier/memconf.c [new file with mode: 0644]
arch/arm/mach-uniphier/memconf/Makefile [deleted file]
arch/arm/mach-uniphier/memconf/memconf-pxs2.c [deleted file]
arch/arm/mach-uniphier/memconf/memconf-sld3.c [deleted file]
arch/arm/mach-uniphier/memconf/memconf.c [deleted file]

index ae78548670836b015507ac09b9a309b42bf62dec..98b42a06ce589a3172ec56d7283d4600dc75d2f3 100644 (file)
@@ -4,7 +4,8 @@
 
 ifdef CONFIG_SPL_BUILD
 
-obj-y += init/ bcu/ memconf/
+obj-y += memconf.o
+obj-y += init/ bcu/
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
 
 else
index 327fa8b188d4a416435b3e6169a9c6af14675e59..0708aa0c66b375e4cabb13b15bc743d926865c4f 100644 (file)
@@ -77,9 +77,9 @@ static inline int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd)
 int uniphier_sld3_bcu_init(const struct uniphier_board_data *bd);
 int uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
 
-int memconf_init(const struct uniphier_board_data *bd);
-int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd);
-int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd);
+int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
+int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd);
+int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd);
 
 int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
index 9d43a13f79fc339890251c82151573cdecd04120..93b21625babb273ff6d7a8603be2c67ed80b274e 100644 (file)
@@ -25,7 +25,7 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd)
 
        led_puts("L0");
 
-       memconf_init(bd);
+       uniphier_memconf_2ch_init(bd);
 
        led_puts("L1");
 
index 670243014a0048c99fe02018e05c718503247973..de39b9aece5076d1d10ceb277159b01a4b9fdd94 100644 (file)
@@ -25,8 +25,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
 
        led_puts("L0");
 
-       memconf_init(bd);
-       uniphier_pxs2_memconf_init(bd);
+       uniphier_memconf_3ch_init(bd);
 
        led_puts("L1");
 
index 5f4880ce1c5b5e6d9e9f56f03237e65d36f5ef9b..caf02a52579c211575795e7c60d73fcb6ff1aa00 100644 (file)
@@ -27,7 +27,7 @@ int uniphier_ld4_init(const struct uniphier_board_data *bd)
 
        led_puts("L0");
 
-       memconf_init(bd);
+       uniphier_memconf_2ch_init(bd);
 
        led_puts("L1");
 
index e57eb86f694b8f81469a563443fbaf5d2a50d85d..32d09bb8d5f3dbdfc23bac436227df3e2580aee1 100644 (file)
@@ -24,7 +24,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd)
 
        led_puts("L0");
 
-       memconf_init(bd);
+       uniphier_memconf_2ch_init(bd);
 
        led_puts("L1");
 
index ea53dcf208f7ca3a1d4ec65940b4ac827d31b8d0..3fc09a42cad6c390774c5f31bf102772df9e4fb4 100644 (file)
@@ -20,7 +20,7 @@ int uniphier_pro5_init(const struct uniphier_board_data *bd)
 
        led_puts("L0");
 
-       memconf_init(bd);
+       uniphier_memconf_2ch_init(bd);
 
        led_puts("L1");
 
index 7cdf4bdc11c3cba601e5507ab7722fc72454eed5..38e37e406741725ac62641a71c904514c4e109bf 100644 (file)
@@ -23,8 +23,7 @@ int uniphier_pxs2_init(const struct uniphier_board_data *bd)
 
        led_puts("L0");
 
-       memconf_init(bd);
-       uniphier_pxs2_memconf_init(bd);
+       uniphier_memconf_3ch_init(bd);
 
        led_puts("L1");
 
index a2e9cc71284f8811f73dcda11646bd2cf1edad67..9dc51bfeadf405331f883afba98901a23eb68621 100644 (file)
@@ -26,8 +26,7 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
 
        led_puts("L0");
 
-       memconf_init(bd);
-       uniphier_sld3_memconf_init(bd);
+       uniphier_memconf_3ch_no_disbit_init(bd);
 
        led_puts("L1");
 
index 07fccb110759ccd2b310b44e0daeda9408740bc7..8e8d62b28da74d58199f1c97d912485841b9d8b4 100644 (file)
@@ -27,7 +27,7 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd)
 
        led_puts("L0");
 
-       memconf_init(bd);
+       uniphier_memconf_2ch_init(bd);
 
        led_puts("L1");
 
diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c
new file mode 100644 (file)
index 0000000..205ccf1
--- /dev/null
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2016      Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "sg-regs.h"
+#include "init.h"
+
+static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
+                                  int have_ch2, int have_ch2_disable_bit)
+{
+       u32 val = 0;
+       unsigned long size_per_word;
+
+       /* set up ch0 */
+       switch (bd->dram_ch[0].width) {
+       case 16:
+               val |= SG_MEMCONF_CH0_NUM_1;
+               size_per_word = bd->dram_ch[0].size;
+               break;
+       case 32:
+               val |= SG_MEMCONF_CH0_NUM_2;
+               size_per_word = bd->dram_ch[0].size >> 1;
+               break;
+       default:
+               pr_err("error: unsupported DRAM ch0 width\n");
+               return -EINVAL;
+       }
+
+       switch (size_per_word) {
+       case SZ_64M:
+               val |= SG_MEMCONF_CH0_SZ_64M;
+               break;
+       case SZ_128M:
+               val |= SG_MEMCONF_CH0_SZ_128M;
+               break;
+       case SZ_256M:
+               val |= SG_MEMCONF_CH0_SZ_256M;
+               break;
+       case SZ_512M:
+               val |= SG_MEMCONF_CH0_SZ_512M;
+               break;
+       case SZ_1G:
+               val |= SG_MEMCONF_CH0_SZ_1G;
+               break;
+       default:
+               pr_err("error: unsupported DRAM ch0 size\n");
+               return -EINVAL;
+       }
+
+       /* set up ch1 */
+       switch (bd->dram_ch[1].width) {
+       case 16:
+               val |= SG_MEMCONF_CH1_NUM_1;
+               size_per_word = bd->dram_ch[1].size;
+               break;
+       case 32:
+               val |= SG_MEMCONF_CH1_NUM_2;
+               size_per_word = bd->dram_ch[1].size >> 1;
+               break;
+       default:
+               pr_err("error: unsupported DRAM ch1 width\n");
+               return -EINVAL;
+       }
+
+       switch (size_per_word) {
+       case SZ_64M:
+               val |= SG_MEMCONF_CH1_SZ_64M;
+               break;
+       case SZ_128M:
+               val |= SG_MEMCONF_CH1_SZ_128M;
+               break;
+       case SZ_256M:
+               val |= SG_MEMCONF_CH1_SZ_256M;
+               break;
+       case SZ_512M:
+               val |= SG_MEMCONF_CH1_SZ_512M;
+               break;
+       case SZ_1G:
+               val |= SG_MEMCONF_CH1_SZ_1G;
+               break;
+       default:
+               pr_err("error: unsupported DRAM ch1 size\n");
+               return -EINVAL;
+       }
+
+       /* is sparse mem? */
+       if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
+               val |= SG_MEMCONF_SPARSEMEM;
+
+       if (!have_ch2)
+               goto out;
+
+       if (!bd->dram_ch[2].size) {
+               if (have_ch2_disable_bit)
+                       val |= SG_MEMCONF_CH2_DISABLE;
+               goto out;
+       }
+
+       /* set up ch2 */
+       switch (bd->dram_ch[2].width) {
+       case 16:
+               val |= SG_MEMCONF_CH2_NUM_1;
+               size_per_word = bd->dram_ch[2].size;
+               break;
+       case 32:
+               val |= SG_MEMCONF_CH2_NUM_2;
+               size_per_word = bd->dram_ch[2].size >> 1;
+               break;
+       default:
+               pr_err("error: unsupported DRAM ch2 width\n");
+               return -EINVAL;
+       }
+
+       switch (size_per_word) {
+       case SZ_64M:
+               val |= SG_MEMCONF_CH2_SZ_64M;
+               break;
+       case SZ_128M:
+               val |= SG_MEMCONF_CH2_SZ_128M;
+               break;
+       case SZ_256M:
+               val |= SG_MEMCONF_CH2_SZ_256M;
+               break;
+       case SZ_512M:
+               val |= SG_MEMCONF_CH2_SZ_512M;
+               break;
+       case SZ_1G:
+               val |= SG_MEMCONF_CH2_SZ_1G;
+               break;
+       default:
+               pr_err("error: unsupported DRAM ch2 size\n");
+               return -EINVAL;
+       }
+
+out:
+       writel(val, SG_MEMCONF);
+
+       return 0;
+}
+
+int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd)
+{
+       return __uniphier_memconf_init(bd, 0, 0);
+}
+
+int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd)
+{
+       return __uniphier_memconf_init(bd, 1, 0);
+}
+
+int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd)
+{
+       return __uniphier_memconf_init(bd, 1, 1);
+}
diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile
deleted file mode 100644 (file)
index 6ed1419..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y                                  += memconf.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)       += memconf-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2)       += memconf-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B)       += memconf-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20)       += memconf-pxs2.o
diff --git a/arch/arm/mach-uniphier/memconf/memconf-pxs2.c b/arch/arm/mach-uniphier/memconf/memconf-pxs2.c
deleted file mode 100644 (file)
index e98eb48..0000000
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd)
-{
-       u32 tmp;
-       unsigned long size_per_word;
-
-       tmp = readl(SG_MEMCONF);
-
-       tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
-
-       switch (bd->dram_ch[2].width) {
-       case 16:
-               tmp |= SG_MEMCONF_CH2_NUM_1;
-               size_per_word = bd->dram_ch[2].size;
-               break;
-       case 32:
-               tmp |= SG_MEMCONF_CH2_NUM_2;
-               size_per_word = bd->dram_ch[2].size >> 1;
-               break;
-       default:
-               pr_err("error: unsupported DRAM Ch2 width\n");
-               return -EINVAL;
-       }
-
-       /* Set DDR size */
-       switch (size_per_word) {
-       case SZ_64M:
-               tmp |= SG_MEMCONF_CH2_SZ_64M;
-               break;
-       case SZ_128M:
-               tmp |= SG_MEMCONF_CH2_SZ_128M;
-               break;
-       case SZ_256M:
-               tmp |= SG_MEMCONF_CH2_SZ_256M;
-               break;
-       case SZ_512M:
-               tmp |= SG_MEMCONF_CH2_SZ_512M;
-               break;
-       case SZ_1G:
-               tmp |= SG_MEMCONF_CH2_SZ_1G;
-               break;
-       default:
-               pr_err("error: unsupported DRAM Ch2 size\n");
-               return -EINVAL;
-       }
-
-       if (size_per_word)
-               tmp &= ~SG_MEMCONF_CH2_DISABLE;
-       else
-               tmp |= SG_MEMCONF_CH2_DISABLE;
-
-       writel(tmp, SG_MEMCONF);
-
-       return 0;
-}
diff --git a/arch/arm/mach-uniphier/memconf/memconf-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-sld3.c
deleted file mode 100644 (file)
index 948f82c..0000000
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd)
-{
-       u32 tmp;
-       unsigned long size_per_word;
-
-       tmp = readl(SG_MEMCONF);
-
-       tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
-
-       switch (bd->dram_ch[2].width) {
-       case 16:
-               tmp |= SG_MEMCONF_CH2_NUM_1;
-               size_per_word = bd->dram_ch[2].size;
-               break;
-       case 32:
-               tmp |= SG_MEMCONF_CH2_NUM_2;
-               size_per_word = bd->dram_ch[2].size >> 1;
-               break;
-       default:
-               pr_err("error: unsupported DRAM Ch2 width\n");
-               return -EINVAL;
-       }
-
-       /* Set DDR size */
-       switch (size_per_word) {
-       case SZ_64M:
-               tmp |= SG_MEMCONF_CH2_SZ_64M;
-               break;
-       case SZ_128M:
-               tmp |= SG_MEMCONF_CH2_SZ_128M;
-               break;
-       case SZ_256M:
-               tmp |= SG_MEMCONF_CH2_SZ_256M;
-               break;
-       case SZ_512M:
-               tmp |= SG_MEMCONF_CH2_SZ_512M;
-               break;
-       default:
-               pr_err("error: unsupported DRAM Ch2 size\n");
-               return -EINVAL;
-       }
-
-       writel(tmp, SG_MEMCONF);
-
-       return 0;
-}
diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c
deleted file mode 100644 (file)
index e607ac9..0000000
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2016      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int memconf_init(const struct uniphier_board_data *bd)
-{
-       u32 tmp;
-       unsigned long size_per_word;
-
-       tmp = readl(SG_MEMCONF);
-
-       tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
-
-       switch (bd->dram_ch[0].width) {
-       case 16:
-               tmp |= SG_MEMCONF_CH0_NUM_1;
-               size_per_word = bd->dram_ch[0].size;
-               break;
-       case 32:
-               tmp |= SG_MEMCONF_CH0_NUM_2;
-               size_per_word = bd->dram_ch[0].size >> 1;
-               break;
-       default:
-               pr_err("error: unsupported DRAM Ch0 width\n");
-               return -EINVAL;
-       }
-
-       /* Set DDR size */
-       switch (size_per_word) {
-       case SZ_64M:
-               tmp |= SG_MEMCONF_CH0_SZ_64M;
-               break;
-       case SZ_128M:
-               tmp |= SG_MEMCONF_CH0_SZ_128M;
-               break;
-       case SZ_256M:
-               tmp |= SG_MEMCONF_CH0_SZ_256M;
-               break;
-       case SZ_512M:
-               tmp |= SG_MEMCONF_CH0_SZ_512M;
-               break;
-       case SZ_1G:
-               tmp |= SG_MEMCONF_CH0_SZ_1G;
-               break;
-       default:
-               pr_err("error: unsupported DRAM Ch0 size\n");
-               return -EINVAL;
-       }
-
-       tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
-
-       switch (bd->dram_ch[1].width) {
-       case 16:
-               tmp |= SG_MEMCONF_CH1_NUM_1;
-               size_per_word = bd->dram_ch[1].size;
-               break;
-       case 32:
-               tmp |= SG_MEMCONF_CH1_NUM_2;
-               size_per_word = bd->dram_ch[1].size >> 1;
-               break;
-       default:
-               pr_err("error: unsupported DRAM Ch1 width\n");
-               return -EINVAL;
-       }
-
-       switch (size_per_word) {
-       case SZ_64M:
-               tmp |= SG_MEMCONF_CH1_SZ_64M;
-               break;
-       case SZ_128M:
-               tmp |= SG_MEMCONF_CH1_SZ_128M;
-               break;
-       case SZ_256M:
-               tmp |= SG_MEMCONF_CH1_SZ_256M;
-               break;
-       case SZ_512M:
-               tmp |= SG_MEMCONF_CH1_SZ_512M;
-               break;
-       case SZ_1G:
-               tmp |= SG_MEMCONF_CH1_SZ_1G;
-               break;
-       default:
-               pr_err("error: unsupported DRAM Ch1 size\n");
-               return -EINVAL;
-       }
-
-       if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
-               tmp |= SG_MEMCONF_SPARSEMEM;
-       else
-               tmp &= ~SG_MEMCONF_SPARSEMEM;
-
-       writel(tmp, SG_MEMCONF);
-
-       return 0;
-}