For all SoC in the ath79 target, the PLL controller provides 3 main
clocks "cpu", "ddr" and "ahb" through the input clock "ref".
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
bootargs = "console=ttyATH0,115200";
};
+ ref: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "ref";
+ };
+
ahb {
apb {
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar9330-pll";
reg = <0x18050000 0x100>;
+ clocks = <&ref>;
+ clock-names = "ref";
+
#clock-cells = <1>;
+ clock-output-names = "cpu", "ddr", "ahb";
};
wdt: wdt@18060008 {
/ {
compatible = "qca,ar9331";
-
- ref: ref {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
};
#clock-cells = <1>;
clock-output-names = "cpu", "ddr", "ahb";
+
clocks = <&extosc>;
+ clock-names = "ref";
};
wdt: wdt@18060008 {
clock-output-names = "cpu", "ddr", "ahb";
clocks = <&extosc>;
+ clock-names = "ref";
};
wdt: wdt@18060008 {
clock-output-names = "cpu", "ddr", "ahb";
clocks = <&extosc>;
+ clock-names = "ref";
};
wdt: wdt@18060008 {